mpc8xxx_wdt.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
  4. *
  5. * Authors: Dave Updegraff <dave@cray.org>
  6. * Kumar Gala <galak@kernel.crashing.org>
  7. * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
  8. * ..and from sc520_wdt
  9. * Copyright (c) 2008 MontaVista Software, Inc.
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * Note: it appears that you can only actually ENABLE or DISABLE the thing
  13. * once after POR. Once enabled, you cannot disable, and vice versa.
  14. */
  15. #include <linux/fs.h>
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/module.h>
  21. #include <linux/watchdog.h>
  22. #include <linux/io.h>
  23. #include <linux/uaccess.h>
  24. #include <sysdev/fsl_soc.h>
  25. #define WATCHDOG_TIMEOUT 10
  26. struct mpc8xxx_wdt {
  27. __be32 res0;
  28. __be32 swcrr; /* System watchdog control register */
  29. #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
  30. #define SWCRR_SWF 0x00000008 /* Software Watchdog Freeze (mpc8xx). */
  31. #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
  32. #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
  33. #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
  34. __be32 swcnr; /* System watchdog count register */
  35. u8 res1[2];
  36. __be16 swsrr; /* System watchdog service register */
  37. u8 res2[0xF0];
  38. };
  39. struct mpc8xxx_wdt_type {
  40. int prescaler;
  41. bool hw_enabled;
  42. u32 rsr_mask;
  43. };
  44. struct mpc8xxx_wdt_ddata {
  45. struct mpc8xxx_wdt __iomem *base;
  46. struct watchdog_device wdd;
  47. spinlock_t lock;
  48. u16 swtc;
  49. };
  50. static u16 timeout;
  51. module_param(timeout, ushort, 0);
  52. MODULE_PARM_DESC(timeout,
  53. "Watchdog timeout in seconds. (1<timeout<65535, default="
  54. __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
  55. static bool reset = 1;
  56. module_param(reset, bool, 0);
  57. MODULE_PARM_DESC(reset,
  58. "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
  59. static bool nowayout = WATCHDOG_NOWAYOUT;
  60. module_param(nowayout, bool, 0);
  61. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  62. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  63. static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
  64. {
  65. /* Ping the WDT */
  66. spin_lock(&ddata->lock);
  67. out_be16(&ddata->base->swsrr, 0x556c);
  68. out_be16(&ddata->base->swsrr, 0xaa39);
  69. spin_unlock(&ddata->lock);
  70. }
  71. static int mpc8xxx_wdt_start(struct watchdog_device *w)
  72. {
  73. struct mpc8xxx_wdt_ddata *ddata =
  74. container_of(w, struct mpc8xxx_wdt_ddata, wdd);
  75. u32 tmp = in_be32(&ddata->base->swcrr);
  76. /* Good, fire up the show */
  77. tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
  78. tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
  79. if (reset)
  80. tmp |= SWCRR_SWRI;
  81. out_be32(&ddata->base->swcrr, tmp);
  82. tmp = in_be32(&ddata->base->swcrr);
  83. if (!(tmp & SWCRR_SWEN))
  84. return -EOPNOTSUPP;
  85. ddata->swtc = tmp >> 16;
  86. set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
  87. return 0;
  88. }
  89. static int mpc8xxx_wdt_ping(struct watchdog_device *w)
  90. {
  91. struct mpc8xxx_wdt_ddata *ddata =
  92. container_of(w, struct mpc8xxx_wdt_ddata, wdd);
  93. mpc8xxx_wdt_keepalive(ddata);
  94. return 0;
  95. }
  96. static struct watchdog_info mpc8xxx_wdt_info = {
  97. .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
  98. .firmware_version = 1,
  99. .identity = "MPC8xxx",
  100. };
  101. static struct watchdog_ops mpc8xxx_wdt_ops = {
  102. .owner = THIS_MODULE,
  103. .start = mpc8xxx_wdt_start,
  104. .ping = mpc8xxx_wdt_ping,
  105. };
  106. static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
  107. {
  108. int ret;
  109. struct resource *res;
  110. const struct mpc8xxx_wdt_type *wdt_type;
  111. struct mpc8xxx_wdt_ddata *ddata;
  112. u32 freq = fsl_get_sys_freq();
  113. bool enabled;
  114. struct device *dev = &ofdev->dev;
  115. wdt_type = of_device_get_match_data(dev);
  116. if (!wdt_type)
  117. return -EINVAL;
  118. if (!freq || freq == -1)
  119. return -EINVAL;
  120. ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
  121. if (!ddata)
  122. return -ENOMEM;
  123. ddata->base = devm_platform_ioremap_resource(ofdev, 0);
  124. if (IS_ERR(ddata->base))
  125. return PTR_ERR(ddata->base);
  126. enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
  127. if (!enabled && wdt_type->hw_enabled) {
  128. dev_info(dev, "could not be enabled in software\n");
  129. return -ENODEV;
  130. }
  131. res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
  132. if (res) {
  133. bool status;
  134. u32 __iomem *rsr = ioremap(res->start, resource_size(res));
  135. if (!rsr)
  136. return -ENOMEM;
  137. status = in_be32(rsr) & wdt_type->rsr_mask;
  138. ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
  139. /* clear reset status bits related to watchdog timer */
  140. out_be32(rsr, wdt_type->rsr_mask);
  141. iounmap(rsr);
  142. dev_info(dev, "Last boot was %scaused by watchdog\n",
  143. status ? "" : "not ");
  144. }
  145. spin_lock_init(&ddata->lock);
  146. ddata->wdd.info = &mpc8xxx_wdt_info,
  147. ddata->wdd.ops = &mpc8xxx_wdt_ops,
  148. ddata->wdd.timeout = WATCHDOG_TIMEOUT;
  149. watchdog_init_timeout(&ddata->wdd, timeout, dev);
  150. watchdog_set_nowayout(&ddata->wdd, nowayout);
  151. ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
  152. 0xffffU);
  153. /*
  154. * If the watchdog was previously enabled or we're running on
  155. * MPC8xxx, we should ping the wdt from the kernel until the
  156. * userspace handles it.
  157. */
  158. if (enabled)
  159. mpc8xxx_wdt_start(&ddata->wdd);
  160. ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
  161. (freq / 1000);
  162. ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
  163. if (ddata->wdd.timeout < ddata->wdd.min_timeout)
  164. ddata->wdd.timeout = ddata->wdd.min_timeout;
  165. ret = devm_watchdog_register_device(dev, &ddata->wdd);
  166. if (ret)
  167. return ret;
  168. dev_info(dev,
  169. "WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
  170. reset ? "reset" : "interrupt", ddata->wdd.timeout);
  171. platform_set_drvdata(ofdev, ddata);
  172. return 0;
  173. }
  174. static const struct of_device_id mpc8xxx_wdt_match[] = {
  175. {
  176. .compatible = "mpc83xx_wdt",
  177. .data = &(struct mpc8xxx_wdt_type) {
  178. .prescaler = 0x10000,
  179. .rsr_mask = BIT(3), /* RSR Bit SWRS */
  180. },
  181. },
  182. {
  183. .compatible = "fsl,mpc8610-wdt",
  184. .data = &(struct mpc8xxx_wdt_type) {
  185. .prescaler = 0x10000,
  186. .hw_enabled = true,
  187. .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
  188. },
  189. },
  190. {
  191. .compatible = "fsl,mpc823-wdt",
  192. .data = &(struct mpc8xxx_wdt_type) {
  193. .prescaler = 0x800,
  194. .hw_enabled = true,
  195. .rsr_mask = BIT(28), /* RSR Bit SWRS */
  196. },
  197. },
  198. {},
  199. };
  200. MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
  201. static struct platform_driver mpc8xxx_wdt_driver = {
  202. .probe = mpc8xxx_wdt_probe,
  203. .driver = {
  204. .name = "mpc8xxx_wdt",
  205. .of_match_table = mpc8xxx_wdt_match,
  206. },
  207. };
  208. static int __init mpc8xxx_wdt_init(void)
  209. {
  210. return platform_driver_register(&mpc8xxx_wdt_driver);
  211. }
  212. arch_initcall(mpc8xxx_wdt_init);
  213. static void __exit mpc8xxx_wdt_exit(void)
  214. {
  215. platform_driver_unregister(&mpc8xxx_wdt_driver);
  216. }
  217. module_exit(mpc8xxx_wdt_exit);
  218. MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
  219. MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
  220. "uProcessors");
  221. MODULE_LICENSE("GPL");