imx7ulp_wdt.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/io.h>
  7. #include <linux/iopoll.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reboot.h>
  13. #include <linux/watchdog.h>
  14. #define WDOG_CS 0x0
  15. #define WDOG_CS_CMD32EN BIT(13)
  16. #define WDOG_CS_ULK BIT(11)
  17. #define WDOG_CS_RCS BIT(10)
  18. #define LPO_CLK 0x1
  19. #define LPO_CLK_SHIFT 8
  20. #define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT)
  21. #define WDOG_CS_EN BIT(7)
  22. #define WDOG_CS_UPDATE BIT(5)
  23. #define WDOG_CS_WAIT BIT(1)
  24. #define WDOG_CS_STOP BIT(0)
  25. #define WDOG_CNT 0x4
  26. #define WDOG_TOVAL 0x8
  27. #define REFRESH_SEQ0 0xA602
  28. #define REFRESH_SEQ1 0xB480
  29. #define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)
  30. #define UNLOCK_SEQ0 0xC520
  31. #define UNLOCK_SEQ1 0xD928
  32. #define UNLOCK ((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0)
  33. #define DEFAULT_TIMEOUT 60
  34. #define MAX_TIMEOUT 128
  35. #define WDOG_CLOCK_RATE 1000
  36. #define WDOG_WAIT_TIMEOUT 20
  37. static bool nowayout = WATCHDOG_NOWAYOUT;
  38. module_param(nowayout, bool, 0000);
  39. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  40. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  41. struct imx7ulp_wdt_device {
  42. struct watchdog_device wdd;
  43. void __iomem *base;
  44. struct clk *clk;
  45. };
  46. static int imx7ulp_wdt_wait(void __iomem *base, u32 mask)
  47. {
  48. u32 val = readl(base + WDOG_CS);
  49. if (!(val & mask) && readl_poll_timeout_atomic(base + WDOG_CS, val,
  50. val & mask, 0,
  51. WDOG_WAIT_TIMEOUT))
  52. return -ETIMEDOUT;
  53. return 0;
  54. }
  55. static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable)
  56. {
  57. struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
  58. u32 val = readl(wdt->base + WDOG_CS);
  59. int ret;
  60. local_irq_disable();
  61. writel(UNLOCK, wdt->base + WDOG_CNT);
  62. ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK);
  63. if (ret)
  64. goto enable_out;
  65. if (enable)
  66. writel(val | WDOG_CS_EN, wdt->base + WDOG_CS);
  67. else
  68. writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
  69. imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS);
  70. enable_out:
  71. local_irq_enable();
  72. return ret;
  73. }
  74. static bool imx7ulp_wdt_is_enabled(void __iomem *base)
  75. {
  76. u32 val = readl(base + WDOG_CS);
  77. return val & WDOG_CS_EN;
  78. }
  79. static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
  80. {
  81. struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
  82. writel(REFRESH, wdt->base + WDOG_CNT);
  83. return 0;
  84. }
  85. static int imx7ulp_wdt_start(struct watchdog_device *wdog)
  86. {
  87. return imx7ulp_wdt_enable(wdog, true);
  88. }
  89. static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
  90. {
  91. return imx7ulp_wdt_enable(wdog, false);
  92. }
  93. static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
  94. unsigned int timeout)
  95. {
  96. struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
  97. u32 val = WDOG_CLOCK_RATE * timeout;
  98. int ret;
  99. local_irq_disable();
  100. writel(UNLOCK, wdt->base + WDOG_CNT);
  101. ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK);
  102. if (ret)
  103. goto timeout_out;
  104. writel(val, wdt->base + WDOG_TOVAL);
  105. imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS);
  106. wdog->timeout = timeout;
  107. timeout_out:
  108. local_irq_enable();
  109. return ret;
  110. }
  111. static int imx7ulp_wdt_restart(struct watchdog_device *wdog,
  112. unsigned long action, void *data)
  113. {
  114. struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
  115. int ret;
  116. ret = imx7ulp_wdt_enable(wdog, true);
  117. if (ret)
  118. return ret;
  119. ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1);
  120. if (ret)
  121. return ret;
  122. /* wait for wdog to fire */
  123. while (true)
  124. ;
  125. return NOTIFY_DONE;
  126. }
  127. static const struct watchdog_ops imx7ulp_wdt_ops = {
  128. .owner = THIS_MODULE,
  129. .start = imx7ulp_wdt_start,
  130. .stop = imx7ulp_wdt_stop,
  131. .ping = imx7ulp_wdt_ping,
  132. .set_timeout = imx7ulp_wdt_set_timeout,
  133. .restart = imx7ulp_wdt_restart,
  134. };
  135. static const struct watchdog_info imx7ulp_wdt_info = {
  136. .identity = "i.MX7ULP watchdog timer",
  137. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  138. WDIOF_MAGICCLOSE,
  139. };
  140. static int imx7ulp_wdt_init(void __iomem *base, unsigned int timeout)
  141. {
  142. u32 val;
  143. int ret;
  144. local_irq_disable();
  145. /* unlock the wdog for reconfiguration */
  146. writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
  147. writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);
  148. ret = imx7ulp_wdt_wait(base, WDOG_CS_ULK);
  149. if (ret)
  150. goto init_out;
  151. /* set an initial timeout value in TOVAL */
  152. writel(timeout, base + WDOG_TOVAL);
  153. /* enable 32bit command sequence and reconfigure */
  154. val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE |
  155. WDOG_CS_WAIT | WDOG_CS_STOP;
  156. writel(val, base + WDOG_CS);
  157. imx7ulp_wdt_wait(base, WDOG_CS_RCS);
  158. init_out:
  159. local_irq_enable();
  160. return ret;
  161. }
  162. static void imx7ulp_wdt_action(void *data)
  163. {
  164. clk_disable_unprepare(data);
  165. }
  166. static int imx7ulp_wdt_probe(struct platform_device *pdev)
  167. {
  168. struct imx7ulp_wdt_device *imx7ulp_wdt;
  169. struct device *dev = &pdev->dev;
  170. struct watchdog_device *wdog;
  171. int ret;
  172. imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
  173. if (!imx7ulp_wdt)
  174. return -ENOMEM;
  175. platform_set_drvdata(pdev, imx7ulp_wdt);
  176. imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
  177. if (IS_ERR(imx7ulp_wdt->base))
  178. return PTR_ERR(imx7ulp_wdt->base);
  179. imx7ulp_wdt->clk = devm_clk_get(dev, NULL);
  180. if (IS_ERR(imx7ulp_wdt->clk)) {
  181. dev_err(dev, "Failed to get watchdog clock\n");
  182. return PTR_ERR(imx7ulp_wdt->clk);
  183. }
  184. ret = clk_prepare_enable(imx7ulp_wdt->clk);
  185. if (ret)
  186. return ret;
  187. ret = devm_add_action_or_reset(dev, imx7ulp_wdt_action, imx7ulp_wdt->clk);
  188. if (ret)
  189. return ret;
  190. wdog = &imx7ulp_wdt->wdd;
  191. wdog->info = &imx7ulp_wdt_info;
  192. wdog->ops = &imx7ulp_wdt_ops;
  193. wdog->min_timeout = 1;
  194. wdog->max_timeout = MAX_TIMEOUT;
  195. wdog->parent = dev;
  196. wdog->timeout = DEFAULT_TIMEOUT;
  197. watchdog_init_timeout(wdog, 0, dev);
  198. watchdog_stop_on_reboot(wdog);
  199. watchdog_stop_on_unregister(wdog);
  200. watchdog_set_drvdata(wdog, imx7ulp_wdt);
  201. ret = imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE);
  202. if (ret)
  203. return ret;
  204. return devm_watchdog_register_device(dev, wdog);
  205. }
  206. static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev)
  207. {
  208. struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
  209. if (watchdog_active(&imx7ulp_wdt->wdd))
  210. imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
  211. clk_disable_unprepare(imx7ulp_wdt->clk);
  212. return 0;
  213. }
  214. static int __maybe_unused imx7ulp_wdt_resume(struct device *dev)
  215. {
  216. struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
  217. u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE;
  218. int ret;
  219. ret = clk_prepare_enable(imx7ulp_wdt->clk);
  220. if (ret)
  221. return ret;
  222. if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
  223. imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);
  224. if (watchdog_active(&imx7ulp_wdt->wdd))
  225. imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
  226. return 0;
  227. }
  228. static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend,
  229. imx7ulp_wdt_resume);
  230. static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
  231. { .compatible = "fsl,imx7ulp-wdt", },
  232. { /* sentinel */ }
  233. };
  234. MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
  235. static struct platform_driver imx7ulp_wdt_driver = {
  236. .probe = imx7ulp_wdt_probe,
  237. .driver = {
  238. .name = "imx7ulp-wdt",
  239. .pm = &imx7ulp_wdt_pm_ops,
  240. .of_match_table = imx7ulp_wdt_dt_ids,
  241. },
  242. };
  243. module_platform_driver(imx7ulp_wdt_driver);
  244. MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
  245. MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
  246. MODULE_LICENSE("GPL v2");