imx2_wdt.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Watchdog driver for IMX2 and later processors
  4. *
  5. * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
  6. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  7. *
  8. * some parts adapted by similar drivers from Darius Augulis and Vladimir
  9. * Zapolskiy, additional improvements by Wim Van Sebroeck.
  10. *
  11. * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  12. *
  13. * MX1: MX2+:
  14. * ---- -----
  15. * Registers: 32-bit 16-bit
  16. * Stopable timer: Yes No
  17. * Need to enable clk: No Yes
  18. * Halt on suspend: Manual Can be automatic
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/delay.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/io.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/of_address.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/regmap.h>
  31. #include <linux/watchdog.h>
  32. #define DRIVER_NAME "imx2-wdt"
  33. #define IMX2_WDT_WCR 0x00 /* Control Register */
  34. #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
  35. #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
  36. #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
  37. #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
  38. #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
  39. #define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
  40. #define IMX2_WDT_WSR 0x02 /* Service Register */
  41. #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
  42. #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
  43. #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
  44. #define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
  45. #define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
  46. #define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
  47. #define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
  48. #define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
  49. #define IMX2_WDT_WMCR 0x08 /* Misc Register */
  50. #define IMX2_WDT_MAX_TIME 128U
  51. #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
  52. #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
  53. struct imx2_wdt_device {
  54. struct clk *clk;
  55. struct regmap *regmap;
  56. struct watchdog_device wdog;
  57. bool ext_reset;
  58. };
  59. static bool nowayout = WATCHDOG_NOWAYOUT;
  60. module_param(nowayout, bool, 0);
  61. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  62. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  63. static unsigned timeout;
  64. module_param(timeout, uint, 0);
  65. MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  66. __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  67. static const struct watchdog_info imx2_wdt_info = {
  68. .identity = "imx2+ watchdog",
  69. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  70. };
  71. static const struct watchdog_info imx2_wdt_pretimeout_info = {
  72. .identity = "imx2+ watchdog",
  73. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
  74. WDIOF_PRETIMEOUT,
  75. };
  76. static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
  77. void *data)
  78. {
  79. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  80. unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
  81. /* Use internal reset or external - not both */
  82. if (wdev->ext_reset)
  83. wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
  84. else
  85. wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
  86. /* Assert SRS signal */
  87. regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  88. /*
  89. * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
  90. * written twice), we add another two writes to ensure there must be at
  91. * least two writes happen in the same one 32kHz clock period. We save
  92. * the target check here, since the writes shouldn't be a huge burden
  93. * for other platforms.
  94. */
  95. regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  96. regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  97. /* wait for reset to assert... */
  98. mdelay(500);
  99. return 0;
  100. }
  101. static inline void imx2_wdt_setup(struct watchdog_device *wdog)
  102. {
  103. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  104. u32 val;
  105. regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
  106. /* Suspend timer in low power mode, write once-only */
  107. val |= IMX2_WDT_WCR_WDZST;
  108. /* Strip the old watchdog Time-Out value */
  109. val &= ~IMX2_WDT_WCR_WT;
  110. /* Generate internal chip-level reset if WDOG times out */
  111. if (!wdev->ext_reset)
  112. val &= ~IMX2_WDT_WCR_WRE;
  113. /* Or if external-reset assert WDOG_B reset only on time-out */
  114. else
  115. val |= IMX2_WDT_WCR_WRE;
  116. /* Keep Watchdog Disabled */
  117. val &= ~IMX2_WDT_WCR_WDE;
  118. /* Set the watchdog's Time-Out value */
  119. val |= WDOG_SEC_TO_COUNT(wdog->timeout);
  120. regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
  121. /* enable the watchdog */
  122. val |= IMX2_WDT_WCR_WDE;
  123. regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
  124. }
  125. static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
  126. {
  127. u32 val;
  128. regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
  129. return val & IMX2_WDT_WCR_WDE;
  130. }
  131. static int imx2_wdt_ping(struct watchdog_device *wdog)
  132. {
  133. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  134. regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
  135. regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
  136. return 0;
  137. }
  138. static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
  139. unsigned int new_timeout)
  140. {
  141. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  142. regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
  143. WDOG_SEC_TO_COUNT(new_timeout));
  144. }
  145. static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
  146. unsigned int new_timeout)
  147. {
  148. unsigned int actual;
  149. actual = min(new_timeout, IMX2_WDT_MAX_TIME);
  150. __imx2_wdt_set_timeout(wdog, actual);
  151. wdog->timeout = new_timeout;
  152. return 0;
  153. }
  154. static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
  155. unsigned int new_pretimeout)
  156. {
  157. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  158. if (new_pretimeout >= IMX2_WDT_MAX_TIME)
  159. return -EINVAL;
  160. wdog->pretimeout = new_pretimeout;
  161. regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
  162. IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
  163. IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
  164. return 0;
  165. }
  166. static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
  167. {
  168. struct watchdog_device *wdog = wdog_arg;
  169. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  170. regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
  171. IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
  172. watchdog_notify_pretimeout(wdog);
  173. return IRQ_HANDLED;
  174. }
  175. static int imx2_wdt_start(struct watchdog_device *wdog)
  176. {
  177. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  178. if (imx2_wdt_is_running(wdev))
  179. imx2_wdt_set_timeout(wdog, wdog->timeout);
  180. else
  181. imx2_wdt_setup(wdog);
  182. set_bit(WDOG_HW_RUNNING, &wdog->status);
  183. return imx2_wdt_ping(wdog);
  184. }
  185. static const struct watchdog_ops imx2_wdt_ops = {
  186. .owner = THIS_MODULE,
  187. .start = imx2_wdt_start,
  188. .ping = imx2_wdt_ping,
  189. .set_timeout = imx2_wdt_set_timeout,
  190. .set_pretimeout = imx2_wdt_set_pretimeout,
  191. .restart = imx2_wdt_restart,
  192. };
  193. static const struct regmap_config imx2_wdt_regmap_config = {
  194. .reg_bits = 16,
  195. .reg_stride = 2,
  196. .val_bits = 16,
  197. .max_register = 0x8,
  198. };
  199. static void imx2_wdt_action(void *data)
  200. {
  201. clk_disable_unprepare(data);
  202. }
  203. static int __init imx2_wdt_probe(struct platform_device *pdev)
  204. {
  205. struct device *dev = &pdev->dev;
  206. struct imx2_wdt_device *wdev;
  207. struct watchdog_device *wdog;
  208. void __iomem *base;
  209. int ret;
  210. u32 val;
  211. wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
  212. if (!wdev)
  213. return -ENOMEM;
  214. base = devm_platform_ioremap_resource(pdev, 0);
  215. if (IS_ERR(base))
  216. return PTR_ERR(base);
  217. wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
  218. &imx2_wdt_regmap_config);
  219. if (IS_ERR(wdev->regmap)) {
  220. dev_err(dev, "regmap init failed\n");
  221. return PTR_ERR(wdev->regmap);
  222. }
  223. wdev->clk = devm_clk_get(dev, NULL);
  224. if (IS_ERR(wdev->clk)) {
  225. dev_err(dev, "can't get Watchdog clock\n");
  226. return PTR_ERR(wdev->clk);
  227. }
  228. wdog = &wdev->wdog;
  229. wdog->info = &imx2_wdt_info;
  230. wdog->ops = &imx2_wdt_ops;
  231. wdog->min_timeout = 1;
  232. wdog->timeout = IMX2_WDT_DEFAULT_TIME;
  233. wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
  234. wdog->parent = dev;
  235. ret = platform_get_irq(pdev, 0);
  236. if (ret > 0)
  237. if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
  238. dev_name(dev), wdog))
  239. wdog->info = &imx2_wdt_pretimeout_info;
  240. ret = clk_prepare_enable(wdev->clk);
  241. if (ret)
  242. return ret;
  243. ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
  244. if (ret)
  245. return ret;
  246. regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
  247. wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
  248. wdev->ext_reset = of_property_read_bool(dev->of_node,
  249. "fsl,ext-reset-output");
  250. platform_set_drvdata(pdev, wdog);
  251. watchdog_set_drvdata(wdog, wdev);
  252. watchdog_set_nowayout(wdog, nowayout);
  253. watchdog_set_restart_priority(wdog, 128);
  254. watchdog_init_timeout(wdog, timeout, dev);
  255. if (imx2_wdt_is_running(wdev)) {
  256. imx2_wdt_set_timeout(wdog, wdog->timeout);
  257. set_bit(WDOG_HW_RUNNING, &wdog->status);
  258. }
  259. /*
  260. * Disable the watchdog power down counter at boot. Otherwise the power
  261. * down counter will pull down the #WDOG interrupt line for one clock
  262. * cycle.
  263. */
  264. regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
  265. return devm_watchdog_register_device(dev, wdog);
  266. }
  267. static void imx2_wdt_shutdown(struct platform_device *pdev)
  268. {
  269. struct watchdog_device *wdog = platform_get_drvdata(pdev);
  270. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  271. if (imx2_wdt_is_running(wdev)) {
  272. /*
  273. * We are running, configure max timeout before reboot
  274. * will take place.
  275. */
  276. imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
  277. imx2_wdt_ping(wdog);
  278. dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
  279. }
  280. }
  281. /* Disable watchdog if it is active or non-active but still running */
  282. static int __maybe_unused imx2_wdt_suspend(struct device *dev)
  283. {
  284. struct watchdog_device *wdog = dev_get_drvdata(dev);
  285. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  286. /* The watchdog IP block is running */
  287. if (imx2_wdt_is_running(wdev)) {
  288. /*
  289. * Don't update wdog->timeout, we'll restore the current value
  290. * during resume.
  291. */
  292. __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
  293. imx2_wdt_ping(wdog);
  294. }
  295. clk_disable_unprepare(wdev->clk);
  296. return 0;
  297. }
  298. /* Enable watchdog and configure it if necessary */
  299. static int __maybe_unused imx2_wdt_resume(struct device *dev)
  300. {
  301. struct watchdog_device *wdog = dev_get_drvdata(dev);
  302. struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  303. int ret;
  304. ret = clk_prepare_enable(wdev->clk);
  305. if (ret)
  306. return ret;
  307. if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
  308. /*
  309. * If the watchdog is still active and resumes
  310. * from deep sleep state, need to restart the
  311. * watchdog again.
  312. */
  313. imx2_wdt_setup(wdog);
  314. }
  315. if (imx2_wdt_is_running(wdev)) {
  316. imx2_wdt_set_timeout(wdog, wdog->timeout);
  317. imx2_wdt_ping(wdog);
  318. }
  319. return 0;
  320. }
  321. static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
  322. imx2_wdt_resume);
  323. static const struct of_device_id imx2_wdt_dt_ids[] = {
  324. { .compatible = "fsl,imx21-wdt", },
  325. { /* sentinel */ }
  326. };
  327. MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
  328. static struct platform_driver imx2_wdt_driver = {
  329. .shutdown = imx2_wdt_shutdown,
  330. .driver = {
  331. .name = DRIVER_NAME,
  332. .pm = &imx2_wdt_pm_ops,
  333. .of_match_table = imx2_wdt_dt_ids,
  334. },
  335. };
  336. module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
  337. MODULE_AUTHOR("Wolfram Sang");
  338. MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
  339. MODULE_LICENSE("GPL v2");
  340. MODULE_ALIAS("platform:" DRIVER_NAME);