ibmasr.c 9.4 KB

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  1. /*
  2. * IBM Automatic Server Restart driver.
  3. *
  4. * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
  5. *
  6. * Based on driver written by Pete Reynolds.
  7. * Copyright (c) IBM Corporation, 1998-2004.
  8. *
  9. * This software may be used and distributed according to the terms
  10. * of the GNU Public License, incorporated herein by reference.
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/fs.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/timer.h>
  18. #include <linux/miscdevice.h>
  19. #include <linux/watchdog.h>
  20. #include <linux/dmi.h>
  21. #include <linux/io.h>
  22. #include <linux/uaccess.h>
  23. enum {
  24. ASMTYPE_UNKNOWN,
  25. ASMTYPE_TOPAZ,
  26. ASMTYPE_JASPER,
  27. ASMTYPE_PEARL,
  28. ASMTYPE_JUNIPER,
  29. ASMTYPE_SPRUCE,
  30. };
  31. #define TOPAZ_ASR_REG_OFFSET 4
  32. #define TOPAZ_ASR_TOGGLE 0x40
  33. #define TOPAZ_ASR_DISABLE 0x80
  34. /* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
  35. #define PEARL_BASE 0xe04
  36. #define PEARL_WRITE 0xe06
  37. #define PEARL_READ 0xe07
  38. #define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
  39. #define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
  40. /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
  41. #define JASPER_ASR_REG_OFFSET 0x38
  42. #define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
  43. #define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
  44. #define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
  45. #define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
  46. #define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
  47. #define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
  48. #define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */
  49. #define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */
  50. static bool nowayout = WATCHDOG_NOWAYOUT;
  51. static unsigned long asr_is_open;
  52. static char asr_expect_close;
  53. static unsigned int asr_type, asr_base, asr_length;
  54. static unsigned int asr_read_addr, asr_write_addr;
  55. static unsigned char asr_toggle_mask, asr_disable_mask;
  56. static DEFINE_SPINLOCK(asr_lock);
  57. static void __asr_toggle(void)
  58. {
  59. unsigned char reg;
  60. reg = inb(asr_read_addr);
  61. outb(reg & ~asr_toggle_mask, asr_write_addr);
  62. reg = inb(asr_read_addr);
  63. outb(reg | asr_toggle_mask, asr_write_addr);
  64. reg = inb(asr_read_addr);
  65. outb(reg & ~asr_toggle_mask, asr_write_addr);
  66. reg = inb(asr_read_addr);
  67. }
  68. static void asr_toggle(void)
  69. {
  70. spin_lock(&asr_lock);
  71. __asr_toggle();
  72. spin_unlock(&asr_lock);
  73. }
  74. static void asr_enable(void)
  75. {
  76. unsigned char reg;
  77. spin_lock(&asr_lock);
  78. if (asr_type == ASMTYPE_TOPAZ) {
  79. /* asr_write_addr == asr_read_addr */
  80. reg = inb(asr_read_addr);
  81. outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE),
  82. asr_read_addr);
  83. } else {
  84. /*
  85. * First make sure the hardware timer is reset by toggling
  86. * ASR hardware timer line.
  87. */
  88. __asr_toggle();
  89. reg = inb(asr_read_addr);
  90. outb(reg & ~asr_disable_mask, asr_write_addr);
  91. }
  92. reg = inb(asr_read_addr);
  93. spin_unlock(&asr_lock);
  94. }
  95. static void asr_disable(void)
  96. {
  97. unsigned char reg;
  98. spin_lock(&asr_lock);
  99. reg = inb(asr_read_addr);
  100. if (asr_type == ASMTYPE_TOPAZ)
  101. /* asr_write_addr == asr_read_addr */
  102. outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE,
  103. asr_read_addr);
  104. else {
  105. outb(reg | asr_toggle_mask, asr_write_addr);
  106. reg = inb(asr_read_addr);
  107. outb(reg | asr_disable_mask, asr_write_addr);
  108. }
  109. reg = inb(asr_read_addr);
  110. spin_unlock(&asr_lock);
  111. }
  112. static int __init asr_get_base_address(void)
  113. {
  114. unsigned char low, high;
  115. const char *type = "";
  116. asr_length = 1;
  117. switch (asr_type) {
  118. case ASMTYPE_TOPAZ:
  119. /* SELECT SuperIO CHIP FOR QUERYING
  120. (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
  121. outb(0x07, 0x2e);
  122. outb(0x07, 0x2f);
  123. /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
  124. outb(0x60, 0x2e);
  125. high = inb(0x2f);
  126. /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
  127. outb(0x61, 0x2e);
  128. low = inb(0x2f);
  129. asr_base = (high << 16) | low;
  130. asr_read_addr = asr_write_addr =
  131. asr_base + TOPAZ_ASR_REG_OFFSET;
  132. asr_length = 5;
  133. break;
  134. case ASMTYPE_JASPER:
  135. type = "Jaspers ";
  136. #if 0
  137. u32 r;
  138. /* Suggested fix */
  139. pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
  140. if (pdev == NULL)
  141. return -ENODEV;
  142. pci_read_config_dword(pdev, 0x58, &r);
  143. asr_base = r & 0xFFFE;
  144. pci_dev_put(pdev);
  145. #else
  146. /* FIXME: need to use pci_config_lock here,
  147. but it's not exported */
  148. /* spin_lock_irqsave(&pci_config_lock, flags);*/
  149. /* Select the SuperIO chip in the PCI I/O port register */
  150. outl(0x8000f858, 0xcf8);
  151. /* BUS 0, Slot 1F, fnc 0, offset 58 */
  152. /*
  153. * Read the base address for the SuperIO chip.
  154. * Only the lower 16 bits are valid, but the address is word
  155. * aligned so the last bit must be masked off.
  156. */
  157. asr_base = inl(0xcfc) & 0xfffe;
  158. /* spin_unlock_irqrestore(&pci_config_lock, flags);*/
  159. #endif
  160. asr_read_addr = asr_write_addr =
  161. asr_base + JASPER_ASR_REG_OFFSET;
  162. asr_toggle_mask = JASPER_ASR_TOGGLE_MASK;
  163. asr_disable_mask = JASPER_ASR_DISABLE_MASK;
  164. asr_length = JASPER_ASR_REG_OFFSET + 1;
  165. break;
  166. case ASMTYPE_PEARL:
  167. type = "Pearls ";
  168. asr_base = PEARL_BASE;
  169. asr_read_addr = PEARL_READ;
  170. asr_write_addr = PEARL_WRITE;
  171. asr_toggle_mask = PEARL_ASR_TOGGLE_MASK;
  172. asr_disable_mask = PEARL_ASR_DISABLE_MASK;
  173. asr_length = 4;
  174. break;
  175. case ASMTYPE_JUNIPER:
  176. type = "Junipers ";
  177. asr_base = JUNIPER_BASE_ADDRESS;
  178. asr_read_addr = asr_write_addr = asr_base;
  179. asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK;
  180. asr_disable_mask = JUNIPER_ASR_DISABLE_MASK;
  181. break;
  182. case ASMTYPE_SPRUCE:
  183. type = "Spruce's ";
  184. asr_base = SPRUCE_BASE_ADDRESS;
  185. asr_read_addr = asr_write_addr = asr_base;
  186. asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK;
  187. asr_disable_mask = SPRUCE_ASR_DISABLE_MASK;
  188. break;
  189. }
  190. if (!request_region(asr_base, asr_length, "ibmasr")) {
  191. pr_err("address %#x already in use\n", asr_base);
  192. return -EBUSY;
  193. }
  194. pr_info("found %sASR @ addr %#x\n", type, asr_base);
  195. return 0;
  196. }
  197. static ssize_t asr_write(struct file *file, const char __user *buf,
  198. size_t count, loff_t *ppos)
  199. {
  200. if (count) {
  201. if (!nowayout) {
  202. size_t i;
  203. /* In case it was set long ago */
  204. asr_expect_close = 0;
  205. for (i = 0; i != count; i++) {
  206. char c;
  207. if (get_user(c, buf + i))
  208. return -EFAULT;
  209. if (c == 'V')
  210. asr_expect_close = 42;
  211. }
  212. }
  213. asr_toggle();
  214. }
  215. return count;
  216. }
  217. static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  218. {
  219. static const struct watchdog_info ident = {
  220. .options = WDIOF_KEEPALIVEPING |
  221. WDIOF_MAGICCLOSE,
  222. .identity = "IBM ASR",
  223. };
  224. void __user *argp = (void __user *)arg;
  225. int __user *p = argp;
  226. int heartbeat;
  227. switch (cmd) {
  228. case WDIOC_GETSUPPORT:
  229. return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
  230. case WDIOC_GETSTATUS:
  231. case WDIOC_GETBOOTSTATUS:
  232. return put_user(0, p);
  233. case WDIOC_SETOPTIONS:
  234. {
  235. int new_options, retval = -EINVAL;
  236. if (get_user(new_options, p))
  237. return -EFAULT;
  238. if (new_options & WDIOS_DISABLECARD) {
  239. asr_disable();
  240. retval = 0;
  241. }
  242. if (new_options & WDIOS_ENABLECARD) {
  243. asr_enable();
  244. asr_toggle();
  245. retval = 0;
  246. }
  247. return retval;
  248. }
  249. case WDIOC_KEEPALIVE:
  250. asr_toggle();
  251. return 0;
  252. /*
  253. * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
  254. * and WDIOC_GETTIMEOUT always returns 256.
  255. */
  256. case WDIOC_GETTIMEOUT:
  257. heartbeat = 256;
  258. return put_user(heartbeat, p);
  259. default:
  260. return -ENOTTY;
  261. }
  262. }
  263. static int asr_open(struct inode *inode, struct file *file)
  264. {
  265. if (test_and_set_bit(0, &asr_is_open))
  266. return -EBUSY;
  267. asr_toggle();
  268. asr_enable();
  269. return stream_open(inode, file);
  270. }
  271. static int asr_release(struct inode *inode, struct file *file)
  272. {
  273. if (asr_expect_close == 42)
  274. asr_disable();
  275. else {
  276. pr_crit("unexpected close, not stopping watchdog!\n");
  277. asr_toggle();
  278. }
  279. clear_bit(0, &asr_is_open);
  280. asr_expect_close = 0;
  281. return 0;
  282. }
  283. static const struct file_operations asr_fops = {
  284. .owner = THIS_MODULE,
  285. .llseek = no_llseek,
  286. .write = asr_write,
  287. .unlocked_ioctl = asr_ioctl,
  288. .compat_ioctl = compat_ptr_ioctl,
  289. .open = asr_open,
  290. .release = asr_release,
  291. };
  292. static struct miscdevice asr_miscdev = {
  293. .minor = WATCHDOG_MINOR,
  294. .name = "watchdog",
  295. .fops = &asr_fops,
  296. };
  297. struct ibmasr_id {
  298. const char *desc;
  299. int type;
  300. };
  301. static struct ibmasr_id ibmasr_id_table[] __initdata = {
  302. { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ },
  303. { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL },
  304. { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER },
  305. { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER },
  306. { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE },
  307. { NULL }
  308. };
  309. static int __init ibmasr_init(void)
  310. {
  311. struct ibmasr_id *id;
  312. int rc;
  313. for (id = ibmasr_id_table; id->desc; id++) {
  314. if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) {
  315. asr_type = id->type;
  316. break;
  317. }
  318. }
  319. if (!asr_type)
  320. return -ENODEV;
  321. rc = asr_get_base_address();
  322. if (rc)
  323. return rc;
  324. rc = misc_register(&asr_miscdev);
  325. if (rc < 0) {
  326. release_region(asr_base, asr_length);
  327. pr_err("failed to register misc device\n");
  328. return rc;
  329. }
  330. return 0;
  331. }
  332. static void __exit ibmasr_exit(void)
  333. {
  334. if (!nowayout)
  335. asr_disable();
  336. misc_deregister(&asr_miscdev);
  337. release_region(asr_base, asr_length);
  338. }
  339. module_init(ibmasr_init);
  340. module_exit(ibmasr_exit);
  341. module_param(nowayout, bool, 0);
  342. MODULE_PARM_DESC(nowayout,
  343. "Watchdog cannot be stopped once started (default="
  344. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  345. MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
  346. MODULE_AUTHOR("Andrey Panin");
  347. MODULE_LICENSE("GPL");