iTCO_wdt.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * intel TCO Watchdog Driver
  4. *
  5. * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
  6. *
  7. * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  8. * provide warranty for any of this software. This material is
  9. * provided "AS-IS" and at no charge.
  10. *
  11. * The TCO watchdog is implemented in the following I/O controller hubs:
  12. * (See the intel documentation on http://developer.intel.com.)
  13. * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  14. * document number 290687-002, 298242-027: 82801BA (ICH2)
  15. * document number 290733-003, 290739-013: 82801CA (ICH3-S)
  16. * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  17. * document number 290744-001, 290745-025: 82801DB (ICH4)
  18. * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  19. * document number 273599-001, 273645-002: 82801E (C-ICH)
  20. * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  21. * document number 300641-004, 300884-013: 6300ESB
  22. * document number 301473-002, 301474-026: 82801F (ICH6)
  23. * document number 313082-001, 313075-006: 631xESB, 632xESB
  24. * document number 307013-003, 307014-024: 82801G (ICH7)
  25. * document number 322896-001, 322897-001: NM10
  26. * document number 313056-003, 313057-017: 82801H (ICH8)
  27. * document number 316972-004, 316973-012: 82801I (ICH9)
  28. * document number 319973-002, 319974-002: 82801J (ICH10)
  29. * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  30. * document number 320066-003, 320257-008: EP80597 (IICH)
  31. * document number 324645-001, 324646-001: Cougar Point (CPT)
  32. * document number TBD : Patsburg (PBG)
  33. * document number TBD : DH89xxCC
  34. * document number TBD : Panther Point
  35. * document number TBD : Lynx Point
  36. * document number TBD : Lynx Point-LP
  37. */
  38. /*
  39. * Includes, defines, variables, module parameters, ...
  40. */
  41. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42. /* Module and version information */
  43. #define DRV_NAME "iTCO_wdt"
  44. #define DRV_VERSION "1.11"
  45. /* Includes */
  46. #include <linux/acpi.h> /* For ACPI support */
  47. #include <linux/bits.h> /* For BIT() */
  48. #include <linux/module.h> /* For module specific items */
  49. #include <linux/moduleparam.h> /* For new moduleparam's */
  50. #include <linux/types.h> /* For standard types (like size_t) */
  51. #include <linux/errno.h> /* For the -ENODEV/... values */
  52. #include <linux/kernel.h> /* For printk/panic/... */
  53. #include <linux/watchdog.h> /* For the watchdog specific items */
  54. #include <linux/init.h> /* For __init/__exit/... */
  55. #include <linux/fs.h> /* For file operations */
  56. #include <linux/platform_device.h> /* For platform_driver framework */
  57. #include <linux/pci.h> /* For pci functions */
  58. #include <linux/ioport.h> /* For io-port access */
  59. #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
  60. #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
  61. #include <linux/io.h> /* For inb/outb/... */
  62. #include <linux/platform_data/itco_wdt.h>
  63. #include <linux/mfd/intel_pmc_bxt.h>
  64. #include "iTCO_vendor.h"
  65. /* Address definitions for the TCO */
  66. /* TCO base address */
  67. #define TCOBASE(p) ((p)->tco_res->start)
  68. /* SMI Control and Enable Register */
  69. #define SMI_EN(p) ((p)->smi_res->start)
  70. #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
  71. #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
  72. #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
  73. #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
  74. #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
  75. #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
  76. #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
  77. #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
  78. #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
  79. /* internal variables */
  80. struct iTCO_wdt_private {
  81. struct watchdog_device wddev;
  82. /* TCO version/generation */
  83. unsigned int iTCO_version;
  84. struct resource *tco_res;
  85. struct resource *smi_res;
  86. /*
  87. * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
  88. * or memory-mapped PMC register bit 4 (TCO version 3).
  89. */
  90. struct resource *gcs_pmc_res;
  91. unsigned long __iomem *gcs_pmc;
  92. /* the lock for io operations */
  93. spinlock_t io_lock;
  94. /* the PCI-device */
  95. struct pci_dev *pci_dev;
  96. /* whether or not the watchdog has been suspended */
  97. bool suspended;
  98. /* no reboot API private data */
  99. void *no_reboot_priv;
  100. /* no reboot update function pointer */
  101. int (*update_no_reboot_bit)(void *p, bool set);
  102. };
  103. /* module parameters */
  104. #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
  105. static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
  106. module_param(heartbeat, int, 0);
  107. MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
  108. "5..76 (TCO v1) or 3..614 (TCO v2), default="
  109. __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
  110. static bool nowayout = WATCHDOG_NOWAYOUT;
  111. module_param(nowayout, bool, 0);
  112. MODULE_PARM_DESC(nowayout,
  113. "Watchdog cannot be stopped once started (default="
  114. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  115. static int turn_SMI_watchdog_clear_off = 1;
  116. module_param(turn_SMI_watchdog_clear_off, int, 0);
  117. MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
  118. "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
  119. /*
  120. * Some TCO specific functions
  121. */
  122. /*
  123. * The iTCO v1 and v2's internal timer is stored as ticks which decrement
  124. * every 0.6 seconds. v3's internal timer is stored as seconds (some
  125. * datasheets incorrectly state 0.6 seconds).
  126. */
  127. static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
  128. int secs)
  129. {
  130. return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
  131. }
  132. static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
  133. int ticks)
  134. {
  135. return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
  136. }
  137. static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
  138. {
  139. u32 enable_bit;
  140. switch (p->iTCO_version) {
  141. case 5:
  142. case 3:
  143. enable_bit = 0x00000010;
  144. break;
  145. case 2:
  146. enable_bit = 0x00000020;
  147. break;
  148. case 4:
  149. case 1:
  150. default:
  151. enable_bit = 0x00000002;
  152. break;
  153. }
  154. return enable_bit;
  155. }
  156. static int update_no_reboot_bit_def(void *priv, bool set)
  157. {
  158. return 0;
  159. }
  160. static int update_no_reboot_bit_pci(void *priv, bool set)
  161. {
  162. struct iTCO_wdt_private *p = priv;
  163. u32 val32 = 0, newval32 = 0;
  164. pci_read_config_dword(p->pci_dev, 0xd4, &val32);
  165. if (set)
  166. val32 |= no_reboot_bit(p);
  167. else
  168. val32 &= ~no_reboot_bit(p);
  169. pci_write_config_dword(p->pci_dev, 0xd4, val32);
  170. pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
  171. /* make sure the update is successful */
  172. if (val32 != newval32)
  173. return -EIO;
  174. return 0;
  175. }
  176. static int update_no_reboot_bit_mem(void *priv, bool set)
  177. {
  178. struct iTCO_wdt_private *p = priv;
  179. u32 val32 = 0, newval32 = 0;
  180. val32 = readl(p->gcs_pmc);
  181. if (set)
  182. val32 |= no_reboot_bit(p);
  183. else
  184. val32 &= ~no_reboot_bit(p);
  185. writel(val32, p->gcs_pmc);
  186. newval32 = readl(p->gcs_pmc);
  187. /* make sure the update is successful */
  188. if (val32 != newval32)
  189. return -EIO;
  190. return 0;
  191. }
  192. static int update_no_reboot_bit_cnt(void *priv, bool set)
  193. {
  194. struct iTCO_wdt_private *p = priv;
  195. u16 val, newval;
  196. val = inw(TCO1_CNT(p));
  197. if (set)
  198. val |= BIT(0);
  199. else
  200. val &= ~BIT(0);
  201. outw(val, TCO1_CNT(p));
  202. newval = inw(TCO1_CNT(p));
  203. /* make sure the update is successful */
  204. return val != newval ? -EIO : 0;
  205. }
  206. static int update_no_reboot_bit_pmc(void *priv, bool set)
  207. {
  208. struct intel_pmc_dev *pmc = priv;
  209. u32 bits = PMC_CFG_NO_REBOOT_EN;
  210. u32 value = set ? bits : 0;
  211. return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
  212. }
  213. static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
  214. struct platform_device *pdev,
  215. struct itco_wdt_platform_data *pdata)
  216. {
  217. if (pdata->no_reboot_use_pmc) {
  218. struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
  219. p->update_no_reboot_bit = update_no_reboot_bit_pmc;
  220. p->no_reboot_priv = pmc;
  221. return;
  222. }
  223. if (p->iTCO_version >= 6)
  224. p->update_no_reboot_bit = update_no_reboot_bit_cnt;
  225. else if (p->iTCO_version >= 2)
  226. p->update_no_reboot_bit = update_no_reboot_bit_mem;
  227. else if (p->iTCO_version == 1)
  228. p->update_no_reboot_bit = update_no_reboot_bit_pci;
  229. else
  230. p->update_no_reboot_bit = update_no_reboot_bit_def;
  231. p->no_reboot_priv = p;
  232. }
  233. static int iTCO_wdt_start(struct watchdog_device *wd_dev)
  234. {
  235. struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
  236. unsigned int val;
  237. spin_lock(&p->io_lock);
  238. iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
  239. /* disable chipset's NO_REBOOT bit */
  240. if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
  241. spin_unlock(&p->io_lock);
  242. pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
  243. return -EIO;
  244. }
  245. /* Force the timer to its reload value by writing to the TCO_RLD
  246. register */
  247. if (p->iTCO_version >= 2)
  248. outw(0x01, TCO_RLD(p));
  249. else if (p->iTCO_version == 1)
  250. outb(0x01, TCO_RLD(p));
  251. /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
  252. val = inw(TCO1_CNT(p));
  253. val &= 0xf7ff;
  254. outw(val, TCO1_CNT(p));
  255. val = inw(TCO1_CNT(p));
  256. spin_unlock(&p->io_lock);
  257. if (val & 0x0800)
  258. return -1;
  259. return 0;
  260. }
  261. static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
  262. {
  263. struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
  264. unsigned int val;
  265. spin_lock(&p->io_lock);
  266. iTCO_vendor_pre_stop(p->smi_res);
  267. /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
  268. val = inw(TCO1_CNT(p));
  269. val |= 0x0800;
  270. outw(val, TCO1_CNT(p));
  271. val = inw(TCO1_CNT(p));
  272. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  273. p->update_no_reboot_bit(p->no_reboot_priv, true);
  274. spin_unlock(&p->io_lock);
  275. if ((val & 0x0800) == 0)
  276. return -1;
  277. return 0;
  278. }
  279. static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
  280. {
  281. struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
  282. spin_lock(&p->io_lock);
  283. /* Reload the timer by writing to the TCO Timer Counter register */
  284. if (p->iTCO_version >= 2) {
  285. outw(0x01, TCO_RLD(p));
  286. } else if (p->iTCO_version == 1) {
  287. /* Reset the timeout status bit so that the timer
  288. * needs to count down twice again before rebooting */
  289. outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
  290. outb(0x01, TCO_RLD(p));
  291. }
  292. spin_unlock(&p->io_lock);
  293. return 0;
  294. }
  295. static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
  296. {
  297. struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
  298. unsigned int val16;
  299. unsigned char val8;
  300. unsigned int tmrval;
  301. tmrval = seconds_to_ticks(p, t);
  302. /* For TCO v1 the timer counts down twice before rebooting */
  303. if (p->iTCO_version == 1)
  304. tmrval /= 2;
  305. /* from the specs: */
  306. /* "Values of 0h-3h are ignored and should not be attempted" */
  307. if (tmrval < 0x04)
  308. return -EINVAL;
  309. if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
  310. (p->iTCO_version == 1 && tmrval > 0x03f))
  311. return -EINVAL;
  312. /* Write new heartbeat to watchdog */
  313. if (p->iTCO_version >= 2) {
  314. spin_lock(&p->io_lock);
  315. val16 = inw(TCOv2_TMR(p));
  316. val16 &= 0xfc00;
  317. val16 |= tmrval;
  318. outw(val16, TCOv2_TMR(p));
  319. val16 = inw(TCOv2_TMR(p));
  320. spin_unlock(&p->io_lock);
  321. if ((val16 & 0x3ff) != tmrval)
  322. return -EINVAL;
  323. } else if (p->iTCO_version == 1) {
  324. spin_lock(&p->io_lock);
  325. val8 = inb(TCOv1_TMR(p));
  326. val8 &= 0xc0;
  327. val8 |= (tmrval & 0xff);
  328. outb(val8, TCOv1_TMR(p));
  329. val8 = inb(TCOv1_TMR(p));
  330. spin_unlock(&p->io_lock);
  331. if ((val8 & 0x3f) != tmrval)
  332. return -EINVAL;
  333. }
  334. wd_dev->timeout = t;
  335. return 0;
  336. }
  337. static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
  338. {
  339. struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
  340. unsigned int val16;
  341. unsigned char val8;
  342. unsigned int time_left = 0;
  343. /* read the TCO Timer */
  344. if (p->iTCO_version >= 2) {
  345. spin_lock(&p->io_lock);
  346. val16 = inw(TCO_RLD(p));
  347. val16 &= 0x3ff;
  348. spin_unlock(&p->io_lock);
  349. time_left = ticks_to_seconds(p, val16);
  350. } else if (p->iTCO_version == 1) {
  351. spin_lock(&p->io_lock);
  352. val8 = inb(TCO_RLD(p));
  353. val8 &= 0x3f;
  354. if (!(inw(TCO1_STS(p)) & 0x0008))
  355. val8 += (inb(TCOv1_TMR(p)) & 0x3f);
  356. spin_unlock(&p->io_lock);
  357. time_left = ticks_to_seconds(p, val8);
  358. }
  359. return time_left;
  360. }
  361. /*
  362. * Kernel Interfaces
  363. */
  364. static const struct watchdog_info ident = {
  365. .options = WDIOF_SETTIMEOUT |
  366. WDIOF_KEEPALIVEPING |
  367. WDIOF_MAGICCLOSE,
  368. .firmware_version = 0,
  369. .identity = DRV_NAME,
  370. };
  371. static const struct watchdog_ops iTCO_wdt_ops = {
  372. .owner = THIS_MODULE,
  373. .start = iTCO_wdt_start,
  374. .stop = iTCO_wdt_stop,
  375. .ping = iTCO_wdt_ping,
  376. .set_timeout = iTCO_wdt_set_timeout,
  377. .get_timeleft = iTCO_wdt_get_timeleft,
  378. };
  379. /*
  380. * Init & exit routines
  381. */
  382. static int iTCO_wdt_probe(struct platform_device *pdev)
  383. {
  384. struct device *dev = &pdev->dev;
  385. struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
  386. struct iTCO_wdt_private *p;
  387. unsigned long val32;
  388. int ret;
  389. if (!pdata)
  390. return -ENODEV;
  391. p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
  392. if (!p)
  393. return -ENOMEM;
  394. spin_lock_init(&p->io_lock);
  395. p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
  396. if (!p->tco_res)
  397. return -ENODEV;
  398. p->iTCO_version = pdata->version;
  399. p->pci_dev = to_pci_dev(dev->parent);
  400. p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
  401. if (p->smi_res) {
  402. /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
  403. if (!devm_request_region(dev, p->smi_res->start,
  404. resource_size(p->smi_res),
  405. pdev->name)) {
  406. pr_err("I/O address 0x%04llx already in use, device disabled\n",
  407. (u64)SMI_EN(p));
  408. return -EBUSY;
  409. }
  410. } else if (iTCO_vendorsupport ||
  411. turn_SMI_watchdog_clear_off >= p->iTCO_version) {
  412. pr_err("SMI I/O resource is missing\n");
  413. return -ENODEV;
  414. }
  415. iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
  416. /*
  417. * Get the Memory-Mapped GCS or PMC register, we need it for the
  418. * NO_REBOOT flag (TCO v2 and v3).
  419. */
  420. if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
  421. !pdata->no_reboot_use_pmc) {
  422. p->gcs_pmc_res = platform_get_resource(pdev,
  423. IORESOURCE_MEM,
  424. ICH_RES_MEM_GCS_PMC);
  425. p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
  426. if (IS_ERR(p->gcs_pmc))
  427. return PTR_ERR(p->gcs_pmc);
  428. }
  429. /* Check chipset's NO_REBOOT bit */
  430. if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
  431. iTCO_vendor_check_noreboot_on()) {
  432. pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
  433. return -ENODEV; /* Cannot reset NO_REBOOT bit */
  434. }
  435. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  436. p->update_no_reboot_bit(p->no_reboot_priv, true);
  437. if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
  438. /*
  439. * Bit 13: TCO_EN -> 0
  440. * Disables TCO logic generating an SMI#
  441. */
  442. val32 = inl(SMI_EN(p));
  443. val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
  444. outl(val32, SMI_EN(p));
  445. }
  446. if (!devm_request_region(dev, p->tco_res->start,
  447. resource_size(p->tco_res),
  448. pdev->name)) {
  449. pr_err("I/O address 0x%04llx already in use, device disabled\n",
  450. (u64)TCOBASE(p));
  451. return -EBUSY;
  452. }
  453. pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
  454. pdata->name, pdata->version, (u64)TCOBASE(p));
  455. /* Clear out the (probably old) status */
  456. switch (p->iTCO_version) {
  457. case 6:
  458. case 5:
  459. case 4:
  460. outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
  461. outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
  462. break;
  463. case 3:
  464. outl(0x20008, TCO1_STS(p));
  465. break;
  466. case 2:
  467. case 1:
  468. default:
  469. outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
  470. outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
  471. outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
  472. break;
  473. }
  474. p->wddev.info = &ident,
  475. p->wddev.ops = &iTCO_wdt_ops,
  476. p->wddev.bootstatus = 0;
  477. p->wddev.timeout = WATCHDOG_TIMEOUT;
  478. watchdog_set_nowayout(&p->wddev, nowayout);
  479. p->wddev.parent = dev;
  480. watchdog_set_drvdata(&p->wddev, p);
  481. platform_set_drvdata(pdev, p);
  482. /* Make sure the watchdog is not running */
  483. iTCO_wdt_stop(&p->wddev);
  484. /* Check that the heartbeat value is within it's range;
  485. if not reset to the default */
  486. if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
  487. iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
  488. pr_info("timeout value out of range, using %d\n",
  489. WATCHDOG_TIMEOUT);
  490. }
  491. watchdog_stop_on_reboot(&p->wddev);
  492. watchdog_stop_on_unregister(&p->wddev);
  493. ret = devm_watchdog_register_device(dev, &p->wddev);
  494. if (ret != 0) {
  495. pr_err("cannot register watchdog device (err=%d)\n", ret);
  496. return ret;
  497. }
  498. pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
  499. heartbeat, nowayout);
  500. return 0;
  501. }
  502. #ifdef CONFIG_PM_SLEEP
  503. /*
  504. * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
  505. * the watchdog cannot be pinged while in that state. In ACPI sleep states the
  506. * watchdog is stopped by the platform firmware.
  507. */
  508. #ifdef CONFIG_ACPI
  509. static inline bool need_suspend(void)
  510. {
  511. return acpi_target_system_state() == ACPI_STATE_S0;
  512. }
  513. #else
  514. static inline bool need_suspend(void) { return true; }
  515. #endif
  516. static int iTCO_wdt_suspend_noirq(struct device *dev)
  517. {
  518. struct iTCO_wdt_private *p = dev_get_drvdata(dev);
  519. int ret = 0;
  520. p->suspended = false;
  521. if (watchdog_active(&p->wddev) && need_suspend()) {
  522. ret = iTCO_wdt_stop(&p->wddev);
  523. if (!ret)
  524. p->suspended = true;
  525. }
  526. return ret;
  527. }
  528. static int iTCO_wdt_resume_noirq(struct device *dev)
  529. {
  530. struct iTCO_wdt_private *p = dev_get_drvdata(dev);
  531. if (p->suspended)
  532. iTCO_wdt_start(&p->wddev);
  533. return 0;
  534. }
  535. static const struct dev_pm_ops iTCO_wdt_pm = {
  536. .suspend_noirq = iTCO_wdt_suspend_noirq,
  537. .resume_noirq = iTCO_wdt_resume_noirq,
  538. };
  539. #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
  540. #else
  541. #define ITCO_WDT_PM_OPS NULL
  542. #endif /* CONFIG_PM_SLEEP */
  543. static struct platform_driver iTCO_wdt_driver = {
  544. .probe = iTCO_wdt_probe,
  545. .driver = {
  546. .name = DRV_NAME,
  547. .pm = ITCO_WDT_PM_OPS,
  548. },
  549. };
  550. static int __init iTCO_wdt_init_module(void)
  551. {
  552. pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
  553. return platform_driver_register(&iTCO_wdt_driver);
  554. }
  555. static void __exit iTCO_wdt_cleanup_module(void)
  556. {
  557. platform_driver_unregister(&iTCO_wdt_driver);
  558. pr_info("Watchdog Module Unloaded\n");
  559. }
  560. module_init(iTCO_wdt_init_module);
  561. module_exit(iTCO_wdt_cleanup_module);
  562. MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
  563. MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
  564. MODULE_VERSION(DRV_VERSION);
  565. MODULE_LICENSE("GPL");
  566. MODULE_ALIAS("platform:" DRV_NAME);