i6300esb.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
  4. *
  5. * (c) Copyright 2004 Google Inc.
  6. * (c) Copyright 2005 David Härdeman <david@2gen.com>
  7. *
  8. * based on i810-tco.c which is in turn based on softdog.c
  9. *
  10. * The timer is implemented in the following I/O controller hubs:
  11. * (See the intel documentation on http://developer.intel.com.)
  12. * 6300ESB chip : document number 300641-004
  13. *
  14. * 2004YYZZ Ross Biro
  15. * Initial version 0.01
  16. * 2004YYZZ Ross Biro
  17. * Version 0.02
  18. * 20050210 David Härdeman <david@2gen.com>
  19. * Ported driver to kernel 2.6
  20. * 20171016 Radu Rendec <rrendec@arista.com>
  21. * Change driver to use the watchdog subsystem
  22. * Add support for multiple 6300ESB devices
  23. */
  24. /*
  25. * Includes, defines, variables, module parameters, ...
  26. */
  27. #include <linux/module.h>
  28. #include <linux/types.h>
  29. #include <linux/kernel.h>
  30. #include <linux/fs.h>
  31. #include <linux/mm.h>
  32. #include <linux/miscdevice.h>
  33. #include <linux/watchdog.h>
  34. #include <linux/pci.h>
  35. #include <linux/ioport.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. /* Module and version information */
  39. #define ESB_MODULE_NAME "i6300ESB timer"
  40. /* PCI configuration registers */
  41. #define ESB_CONFIG_REG 0x60 /* Config register */
  42. #define ESB_LOCK_REG 0x68 /* WDT lock register */
  43. /* Memory mapped registers */
  44. #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
  45. #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
  46. #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
  47. #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
  48. /* Lock register bits */
  49. #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
  50. #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
  51. #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
  52. /* Config register bits */
  53. #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
  54. #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
  55. #define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
  56. /* Reload register bits */
  57. #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
  58. #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
  59. /* Magic constants */
  60. #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
  61. #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
  62. /* module parameters */
  63. /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
  64. #define ESB_HEARTBEAT_MIN 1
  65. #define ESB_HEARTBEAT_MAX 2046
  66. #define ESB_HEARTBEAT_DEFAULT 30
  67. #define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \
  68. "<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX)
  69. static int heartbeat; /* in seconds */
  70. module_param(heartbeat, int, 0);
  71. MODULE_PARM_DESC(heartbeat,
  72. "Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE
  73. ", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")");
  74. static bool nowayout = WATCHDOG_NOWAYOUT;
  75. module_param(nowayout, bool, 0);
  76. MODULE_PARM_DESC(nowayout,
  77. "Watchdog cannot be stopped once started (default="
  78. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  79. /* internal variables */
  80. struct esb_dev {
  81. struct watchdog_device wdd;
  82. void __iomem *base;
  83. struct pci_dev *pdev;
  84. };
  85. #define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)
  86. /*
  87. * Some i6300ESB specific functions
  88. */
  89. /*
  90. * Prepare for reloading the timer by unlocking the proper registers.
  91. * This is performed by first writing 0x80 followed by 0x86 to the
  92. * reload register. After this the appropriate registers can be written
  93. * to once before they need to be unlocked again.
  94. */
  95. static inline void esb_unlock_registers(struct esb_dev *edev)
  96. {
  97. writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev));
  98. writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev));
  99. }
  100. static int esb_timer_start(struct watchdog_device *wdd)
  101. {
  102. struct esb_dev *edev = to_esb_dev(wdd);
  103. int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status);
  104. u8 val;
  105. esb_unlock_registers(edev);
  106. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
  107. /* Enable or Enable + Lock? */
  108. val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00);
  109. pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val);
  110. return 0;
  111. }
  112. static int esb_timer_stop(struct watchdog_device *wdd)
  113. {
  114. struct esb_dev *edev = to_esb_dev(wdd);
  115. u8 val;
  116. /* First, reset timers as suggested by the docs */
  117. esb_unlock_registers(edev);
  118. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
  119. /* Then disable the WDT */
  120. pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0);
  121. pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val);
  122. /* Returns 0 if the timer was disabled, non-zero otherwise */
  123. return val & ESB_WDT_ENABLE;
  124. }
  125. static int esb_timer_keepalive(struct watchdog_device *wdd)
  126. {
  127. struct esb_dev *edev = to_esb_dev(wdd);
  128. esb_unlock_registers(edev);
  129. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
  130. /* FIXME: Do we need to flush anything here? */
  131. return 0;
  132. }
  133. static int esb_timer_set_heartbeat(struct watchdog_device *wdd,
  134. unsigned int time)
  135. {
  136. struct esb_dev *edev = to_esb_dev(wdd);
  137. u32 val;
  138. /* We shift by 9, so if we are passed a value of 1 sec,
  139. * val will be 1 << 9 = 512, then write that to two
  140. * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
  141. */
  142. val = time << 9;
  143. /* Write timer 1 */
  144. esb_unlock_registers(edev);
  145. writel(val, ESB_TIMER1_REG(edev));
  146. /* Write timer 2 */
  147. esb_unlock_registers(edev);
  148. writel(val, ESB_TIMER2_REG(edev));
  149. /* Reload */
  150. esb_unlock_registers(edev);
  151. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
  152. /* FIXME: Do we need to flush everything out? */
  153. /* Done */
  154. wdd->timeout = time;
  155. return 0;
  156. }
  157. /*
  158. * Watchdog Subsystem Interfaces
  159. */
  160. static struct watchdog_info esb_info = {
  161. .identity = ESB_MODULE_NAME,
  162. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  163. };
  164. static const struct watchdog_ops esb_ops = {
  165. .owner = THIS_MODULE,
  166. .start = esb_timer_start,
  167. .stop = esb_timer_stop,
  168. .set_timeout = esb_timer_set_heartbeat,
  169. .ping = esb_timer_keepalive,
  170. };
  171. /*
  172. * Data for PCI driver interface
  173. */
  174. static const struct pci_device_id esb_pci_tbl[] = {
  175. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
  176. { 0, }, /* End of list */
  177. };
  178. MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
  179. /*
  180. * Init & exit routines
  181. */
  182. static unsigned char esb_getdevice(struct esb_dev *edev)
  183. {
  184. if (pci_enable_device(edev->pdev)) {
  185. dev_err(&edev->pdev->dev, "failed to enable device\n");
  186. goto err_devput;
  187. }
  188. if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) {
  189. dev_err(&edev->pdev->dev, "failed to request region\n");
  190. goto err_disable;
  191. }
  192. edev->base = pci_ioremap_bar(edev->pdev, 0);
  193. if (edev->base == NULL) {
  194. /* Something's wrong here, BASEADDR has to be set */
  195. dev_err(&edev->pdev->dev, "failed to get BASEADDR\n");
  196. goto err_release;
  197. }
  198. /* Done */
  199. dev_set_drvdata(&edev->pdev->dev, edev);
  200. return 1;
  201. err_release:
  202. pci_release_region(edev->pdev, 0);
  203. err_disable:
  204. pci_disable_device(edev->pdev);
  205. err_devput:
  206. return 0;
  207. }
  208. static void esb_initdevice(struct esb_dev *edev)
  209. {
  210. u8 val1;
  211. u16 val2;
  212. /*
  213. * Config register:
  214. * Bit 5 : 0 = Enable WDT_OUTPUT
  215. * Bit 2 : 0 = set the timer frequency to the PCI clock
  216. * divided by 2^15 (approx 1KHz).
  217. * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
  218. * The watchdog has two timers, it can be setup so that the
  219. * expiry of timer1 results in an interrupt and the expiry of
  220. * timer2 results in a reboot. We set it to not generate
  221. * any interrupts as there is not much we can do with it
  222. * right now.
  223. */
  224. pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003);
  225. /* Check that the WDT isn't already locked */
  226. pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1);
  227. if (val1 & ESB_WDT_LOCK)
  228. dev_warn(&edev->pdev->dev, "nowayout already set\n");
  229. /* Set the timer to watchdog mode and disable it for now */
  230. pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00);
  231. /* Check if the watchdog was previously triggered */
  232. esb_unlock_registers(edev);
  233. val2 = readw(ESB_RELOAD_REG(edev));
  234. if (val2 & ESB_WDT_TIMEOUT)
  235. edev->wdd.bootstatus = WDIOF_CARDRESET;
  236. /* Reset WDT_TIMEOUT flag and timers */
  237. esb_unlock_registers(edev);
  238. writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG(edev));
  239. /* And set the correct timeout value */
  240. esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout);
  241. }
  242. static int esb_probe(struct pci_dev *pdev,
  243. const struct pci_device_id *ent)
  244. {
  245. struct esb_dev *edev;
  246. int ret;
  247. edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL);
  248. if (!edev)
  249. return -ENOMEM;
  250. /* Check whether or not the hardware watchdog is there */
  251. edev->pdev = pdev;
  252. if (!esb_getdevice(edev))
  253. return -ENODEV;
  254. /* Initialize the watchdog and make sure it does not run */
  255. edev->wdd.info = &esb_info;
  256. edev->wdd.ops = &esb_ops;
  257. edev->wdd.min_timeout = ESB_HEARTBEAT_MIN;
  258. edev->wdd.max_timeout = ESB_HEARTBEAT_MAX;
  259. edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT;
  260. watchdog_init_timeout(&edev->wdd, heartbeat, NULL);
  261. watchdog_set_nowayout(&edev->wdd, nowayout);
  262. watchdog_stop_on_reboot(&edev->wdd);
  263. watchdog_stop_on_unregister(&edev->wdd);
  264. esb_initdevice(edev);
  265. /* Register the watchdog so that userspace has access to it */
  266. ret = watchdog_register_device(&edev->wdd);
  267. if (ret != 0)
  268. goto err_unmap;
  269. dev_info(&pdev->dev,
  270. "initialized. heartbeat=%d sec (nowayout=%d)\n",
  271. edev->wdd.timeout, nowayout);
  272. return 0;
  273. err_unmap:
  274. iounmap(edev->base);
  275. pci_release_region(edev->pdev, 0);
  276. pci_disable_device(edev->pdev);
  277. return ret;
  278. }
  279. static void esb_remove(struct pci_dev *pdev)
  280. {
  281. struct esb_dev *edev = dev_get_drvdata(&pdev->dev);
  282. watchdog_unregister_device(&edev->wdd);
  283. iounmap(edev->base);
  284. pci_release_region(edev->pdev, 0);
  285. pci_disable_device(edev->pdev);
  286. }
  287. static struct pci_driver esb_driver = {
  288. .name = ESB_MODULE_NAME,
  289. .id_table = esb_pci_tbl,
  290. .probe = esb_probe,
  291. .remove = esb_remove,
  292. };
  293. module_pci_driver(esb_driver);
  294. MODULE_AUTHOR("Ross Biro and David Härdeman");
  295. MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
  296. MODULE_LICENSE("GPL");