dw_wdt.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2010-2011 Picochip Ltd., Jamie Iles
  4. * https://www.picochip.com
  5. *
  6. * This file implements a driver for the Synopsys DesignWare watchdog device
  7. * in the many subsystems. The watchdog has 16 different timeout periods
  8. * and these are a function of the input clock frequency.
  9. *
  10. * The DesignWare watchdog cannot be stopped once it has been started so we
  11. * do not implement a stop function. The watchdog core will continue to send
  12. * heartbeat requests after the watchdog device has been closed.
  13. */
  14. #include <linux/bitops.h>
  15. #include <linux/limits.h>
  16. #include <linux/kernel.h>
  17. #include <linux/clk.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. #include <linux/io.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/moduleparam.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/of.h>
  26. #include <linux/pm.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/reset.h>
  29. #include <linux/watchdog.h>
  30. #include <linux/debugfs.h>
  31. #define WDOG_CONTROL_REG_OFFSET 0x00
  32. #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
  33. #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
  34. #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
  35. #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
  36. #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
  37. #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
  38. #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
  39. #define WDOG_INTERRUPT_STATUS_REG_OFFSET 0x10
  40. #define WDOG_INTERRUPT_CLEAR_REG_OFFSET 0x14
  41. #define WDOG_COMP_PARAMS_5_REG_OFFSET 0xe4
  42. #define WDOG_COMP_PARAMS_4_REG_OFFSET 0xe8
  43. #define WDOG_COMP_PARAMS_3_REG_OFFSET 0xec
  44. #define WDOG_COMP_PARAMS_2_REG_OFFSET 0xf0
  45. #define WDOG_COMP_PARAMS_1_REG_OFFSET 0xf4
  46. #define WDOG_COMP_PARAMS_1_USE_FIX_TOP BIT(6)
  47. #define WDOG_COMP_VERSION_REG_OFFSET 0xf8
  48. #define WDOG_COMP_TYPE_REG_OFFSET 0xfc
  49. /* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
  50. #define DW_WDT_NUM_TOPS 16
  51. #define DW_WDT_FIX_TOP(_idx) (1U << (16 + _idx))
  52. #define DW_WDT_DEFAULT_SECONDS 30
  53. static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = {
  54. DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2),
  55. DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5),
  56. DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8),
  57. DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11),
  58. DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14),
  59. DW_WDT_FIX_TOP(15)
  60. };
  61. static bool nowayout = WATCHDOG_NOWAYOUT;
  62. module_param(nowayout, bool, 0);
  63. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  64. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  65. enum dw_wdt_rmod {
  66. DW_WDT_RMOD_RESET = 1,
  67. DW_WDT_RMOD_IRQ = 2
  68. };
  69. struct dw_wdt_timeout {
  70. u32 top_val;
  71. unsigned int sec;
  72. unsigned int msec;
  73. };
  74. struct dw_wdt {
  75. void __iomem *regs;
  76. struct clk *clk;
  77. struct clk *pclk;
  78. unsigned long rate;
  79. enum dw_wdt_rmod rmod;
  80. struct dw_wdt_timeout timeouts[DW_WDT_NUM_TOPS];
  81. struct watchdog_device wdd;
  82. struct reset_control *rst;
  83. /* Save/restore */
  84. u32 control;
  85. u32 timeout;
  86. #ifdef CONFIG_DEBUG_FS
  87. struct dentry *dbgfs_dir;
  88. #endif
  89. };
  90. #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
  91. static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
  92. {
  93. return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
  94. WDOG_CONTROL_REG_WDT_EN_MASK;
  95. }
  96. static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
  97. {
  98. u32 val;
  99. val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  100. if (rmod == DW_WDT_RMOD_IRQ)
  101. val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
  102. else
  103. val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
  104. writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  105. dw_wdt->rmod = rmod;
  106. }
  107. static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
  108. unsigned int timeout, u32 *top_val)
  109. {
  110. int idx;
  111. /*
  112. * Find a TOP with timeout greater or equal to the requested number.
  113. * Note we'll select a TOP with maximum timeout if the requested
  114. * timeout couldn't be reached.
  115. */
  116. for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
  117. if (dw_wdt->timeouts[idx].sec >= timeout)
  118. break;
  119. }
  120. if (idx == DW_WDT_NUM_TOPS)
  121. --idx;
  122. *top_val = dw_wdt->timeouts[idx].top_val;
  123. return dw_wdt->timeouts[idx].sec;
  124. }
  125. static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
  126. {
  127. int idx;
  128. /*
  129. * We'll find a timeout greater or equal to one second anyway because
  130. * the driver probe would have failed if there was none.
  131. */
  132. for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
  133. if (dw_wdt->timeouts[idx].sec)
  134. break;
  135. }
  136. return dw_wdt->timeouts[idx].sec;
  137. }
  138. static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
  139. {
  140. struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
  141. u64 msec;
  142. msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;
  143. return msec < UINT_MAX ? msec : UINT_MAX;
  144. }
  145. static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
  146. {
  147. int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
  148. int idx;
  149. for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
  150. if (dw_wdt->timeouts[idx].top_val == top_val)
  151. break;
  152. }
  153. /*
  154. * In IRQ mode due to the two stages counter, the actual timeout is
  155. * twice greater than the TOP setting.
  156. */
  157. return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
  158. }
  159. static int dw_wdt_ping(struct watchdog_device *wdd)
  160. {
  161. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  162. writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
  163. WDOG_COUNTER_RESTART_REG_OFFSET);
  164. return 0;
  165. }
  166. static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
  167. {
  168. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  169. unsigned int timeout;
  170. u32 top_val;
  171. /*
  172. * Note IRQ mode being enabled means having a non-zero pre-timeout
  173. * setup. In this case we try to find a TOP as close to the half of the
  174. * requested timeout as possible since DW Watchdog IRQ mode is designed
  175. * in two stages way - first timeout rises the pre-timeout interrupt,
  176. * second timeout performs the system reset. So basically the effective
  177. * watchdog-caused reset happens after two watchdog TOPs elapsed.
  178. */
  179. timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
  180. &top_val);
  181. if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
  182. wdd->pretimeout = timeout;
  183. else
  184. wdd->pretimeout = 0;
  185. /*
  186. * Set the new value in the watchdog. Some versions of dw_wdt
  187. * have have TOPINIT in the TIMEOUT_RANGE register (as per
  188. * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
  189. * effectively get a pat of the watchdog right here.
  190. */
  191. writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
  192. dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  193. /* Kick new TOP value into the watchdog counter if activated. */
  194. if (watchdog_active(wdd))
  195. dw_wdt_ping(wdd);
  196. /*
  197. * In case users set bigger timeout value than HW can support,
  198. * kernel(watchdog_dev.c) helps to feed watchdog before
  199. * wdd->max_hw_heartbeat_ms
  200. */
  201. if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
  202. wdd->timeout = timeout * dw_wdt->rmod;
  203. else
  204. wdd->timeout = top_s;
  205. return 0;
  206. }
  207. static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
  208. {
  209. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  210. /*
  211. * We ignore actual value of the timeout passed from user-space
  212. * using it as a flag whether the pretimeout functionality is intended
  213. * to be activated.
  214. */
  215. dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
  216. dw_wdt_set_timeout(wdd, wdd->timeout);
  217. return 0;
  218. }
  219. static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
  220. {
  221. u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  222. /* Disable/enable interrupt mode depending on the RMOD flag. */
  223. if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
  224. val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
  225. else
  226. val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
  227. /* Enable watchdog. */
  228. val |= WDOG_CONTROL_REG_WDT_EN_MASK;
  229. writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  230. }
  231. static int dw_wdt_start(struct watchdog_device *wdd)
  232. {
  233. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  234. dw_wdt_set_timeout(wdd, wdd->timeout);
  235. dw_wdt_ping(&dw_wdt->wdd);
  236. dw_wdt_arm_system_reset(dw_wdt);
  237. return 0;
  238. }
  239. static int dw_wdt_stop(struct watchdog_device *wdd)
  240. {
  241. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  242. if (!dw_wdt->rst) {
  243. set_bit(WDOG_HW_RUNNING, &wdd->status);
  244. return 0;
  245. }
  246. reset_control_assert(dw_wdt->rst);
  247. reset_control_deassert(dw_wdt->rst);
  248. return 0;
  249. }
  250. #ifdef CONFIG_DW_WDT_RESTART_ENA
  251. static int dw_wdt_restart(struct watchdog_device *wdd,
  252. unsigned long action, void *data)
  253. {
  254. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  255. writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  256. dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
  257. if (dw_wdt_is_enabled(dw_wdt))
  258. writel(WDOG_COUNTER_RESTART_KICK_VALUE,
  259. dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
  260. else
  261. dw_wdt_arm_system_reset(dw_wdt);
  262. /* wait for reset to assert... */
  263. mdelay(500);
  264. return 0;
  265. }
  266. #endif
  267. static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
  268. {
  269. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  270. unsigned int sec;
  271. u32 val;
  272. val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
  273. sec = val / dw_wdt->rate;
  274. if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
  275. val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
  276. if (!val)
  277. sec += wdd->pretimeout;
  278. }
  279. return sec;
  280. }
  281. static const struct watchdog_info dw_wdt_ident = {
  282. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
  283. WDIOF_MAGICCLOSE,
  284. .identity = "Synopsys DesignWare Watchdog",
  285. };
  286. static const struct watchdog_info dw_wdt_pt_ident = {
  287. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
  288. WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE,
  289. .identity = "Synopsys DesignWare Watchdog",
  290. };
  291. static const struct watchdog_ops dw_wdt_ops = {
  292. .owner = THIS_MODULE,
  293. .start = dw_wdt_start,
  294. .stop = dw_wdt_stop,
  295. .ping = dw_wdt_ping,
  296. .set_timeout = dw_wdt_set_timeout,
  297. .set_pretimeout = dw_wdt_set_pretimeout,
  298. .get_timeleft = dw_wdt_get_timeleft,
  299. #ifdef CONFIG_DW_WDT_RESTART_ENA
  300. .restart = dw_wdt_restart,
  301. #endif
  302. };
  303. static irqreturn_t dw_wdt_irq(int irq, void *devid)
  304. {
  305. struct dw_wdt *dw_wdt = devid;
  306. u32 val;
  307. /*
  308. * We don't clear the IRQ status. It's supposed to be done by the
  309. * following ping operations.
  310. */
  311. val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
  312. if (!val ) {
  313. pr_warn("watchdog irq enter. however status is 0\n");
  314. return IRQ_NONE;
  315. }
  316. WARN(1, "watchdog app was stuck! watchdog pretimeout event\n");
  317. watchdog_notify_pretimeout(&dw_wdt->wdd);
  318. dw_wdt_ping(&dw_wdt->wdd);
  319. return IRQ_HANDLED;
  320. }
  321. #ifdef CONFIG_PM_SLEEP
  322. static int dw_wdt_suspend(struct device *dev)
  323. {
  324. struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
  325. dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  326. dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  327. clk_disable_unprepare(dw_wdt->pclk);
  328. clk_disable_unprepare(dw_wdt->clk);
  329. return 0;
  330. }
  331. static int dw_wdt_resume(struct device *dev)
  332. {
  333. struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
  334. int err = clk_prepare_enable(dw_wdt->clk);
  335. if (err)
  336. return err;
  337. err = clk_prepare_enable(dw_wdt->pclk);
  338. if (err) {
  339. clk_disable_unprepare(dw_wdt->clk);
  340. return err;
  341. }
  342. writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  343. writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  344. dw_wdt_ping(&dw_wdt->wdd);
  345. return 0;
  346. }
  347. #endif /* CONFIG_PM_SLEEP */
  348. static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
  349. /*
  350. * In case if DW WDT IP core is synthesized with fixed TOP feature disabled the
  351. * TOPs array can be arbitrary ordered with nearly any sixteen uint numbers
  352. * depending on the system engineer imagination. The next method handles the
  353. * passed TOPs array to pre-calculate the effective timeouts and to sort the
  354. * TOP items out in the ascending order with respect to the timeouts.
  355. */
  356. static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
  357. {
  358. struct dw_wdt_timeout tout, *dst;
  359. int val, tidx;
  360. u64 msec;
  361. /*
  362. * We walk over the passed TOPs array and calculate corresponding
  363. * timeouts in seconds and milliseconds. The milliseconds granularity
  364. * is needed to distinguish the TOPs with very close timeouts and to
  365. * set the watchdog max heartbeat setting further.
  366. */
  367. for (val = 0; val < DW_WDT_NUM_TOPS; ++val) {
  368. tout.top_val = val;
  369. tout.sec = tops[val] / dw_wdt->rate;
  370. msec = (u64)tops[val] * MSEC_PER_SEC;
  371. do_div(msec, dw_wdt->rate);
  372. tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);
  373. /*
  374. * Find a suitable place for the current TOP in the timeouts
  375. * array so that the list is remained in the ascending order.
  376. */
  377. for (tidx = 0; tidx < val; ++tidx) {
  378. dst = &dw_wdt->timeouts[tidx];
  379. if (tout.sec > dst->sec || (tout.sec == dst->sec &&
  380. tout.msec >= dst->msec))
  381. continue;
  382. else
  383. swap(*dst, tout);
  384. }
  385. dw_wdt->timeouts[val] = tout;
  386. }
  387. }
  388. static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
  389. {
  390. u32 data, of_tops[DW_WDT_NUM_TOPS];
  391. const u32 *tops;
  392. int ret;
  393. /*
  394. * Retrieve custom or fixed counter values depending on the
  395. * WDT_USE_FIX_TOP flag found in the component specific parameters
  396. * #1 register.
  397. */
  398. data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
  399. if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) {
  400. tops = dw_wdt_fix_tops;
  401. } else {
  402. ret = of_property_read_variable_u32_array(dev_of_node(dev),
  403. "snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,
  404. DW_WDT_NUM_TOPS);
  405. if (ret < 0) {
  406. dev_warn(dev, "No valid TOPs array specified\n");
  407. tops = dw_wdt_fix_tops;
  408. } else {
  409. tops = of_tops;
  410. }
  411. }
  412. /* Convert the specified TOPs into an array of watchdog timeouts. */
  413. dw_wdt_handle_tops(dw_wdt, tops);
  414. if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
  415. dev_err(dev, "No any valid TOP detected\n");
  416. return -EINVAL;
  417. }
  418. return 0;
  419. }
  420. #ifdef CONFIG_DEBUG_FS
  421. #define DW_WDT_DBGFS_REG(_name, _off) \
  422. { \
  423. .name = _name, \
  424. .offset = _off \
  425. }
  426. static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = {
  427. DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET),
  428. DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET),
  429. DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET),
  430. DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET),
  431. DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET),
  432. DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET),
  433. DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET),
  434. DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET),
  435. DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET),
  436. DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET),
  437. DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET),
  438. DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET)
  439. };
  440. static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
  441. {
  442. struct device *dev = dw_wdt->wdd.parent;
  443. struct debugfs_regset32 *regset;
  444. regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
  445. if (!regset)
  446. return;
  447. regset->regs = dw_wdt_dbgfs_regs;
  448. regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);
  449. regset->base = dw_wdt->regs;
  450. dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
  451. debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
  452. }
  453. static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
  454. {
  455. debugfs_remove_recursive(dw_wdt->dbgfs_dir);
  456. }
  457. #else /* !CONFIG_DEBUG_FS */
  458. static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
  459. static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
  460. #endif /* !CONFIG_DEBUG_FS */
  461. static int dw_wdt_drv_probe(struct platform_device *pdev)
  462. {
  463. struct device *dev = &pdev->dev;
  464. struct watchdog_device *wdd;
  465. struct dw_wdt *dw_wdt;
  466. int ret;
  467. dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
  468. if (!dw_wdt)
  469. return -ENOMEM;
  470. dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
  471. if (IS_ERR(dw_wdt->regs))
  472. return PTR_ERR(dw_wdt->regs);
  473. /*
  474. * Try to request the watchdog dedicated timer clock source. It must
  475. * be supplied if asynchronous mode is enabled. Otherwise fallback
  476. * to the common timer/bus clocks configuration, in which the very
  477. * first found clock supply both timer and APB signals.
  478. */
  479. dw_wdt->clk = devm_clk_get(dev, "tclk");
  480. if (IS_ERR(dw_wdt->clk)) {
  481. dw_wdt->clk = devm_clk_get(dev, NULL);
  482. if (IS_ERR(dw_wdt->clk))
  483. return PTR_ERR(dw_wdt->clk);
  484. }
  485. ret = clk_prepare_enable(dw_wdt->clk);
  486. if (ret)
  487. return ret;
  488. dw_wdt->rate = clk_get_rate(dw_wdt->clk);
  489. if (dw_wdt->rate == 0) {
  490. ret = -EINVAL;
  491. goto out_disable_clk;
  492. }
  493. /*
  494. * Request APB clock if device is configured with async clocks mode.
  495. * In this case both tclk and pclk clocks are supposed to be specified.
  496. * Alas we can't know for sure whether async mode was really activated,
  497. * so the pclk phandle reference is left optional. If it couldn't be
  498. * found we consider the device configured in synchronous clocks mode.
  499. */
  500. dw_wdt->pclk = devm_clk_get_optional(dev, "pclk");
  501. if (IS_ERR(dw_wdt->pclk)) {
  502. ret = PTR_ERR(dw_wdt->pclk);
  503. goto out_disable_clk;
  504. }
  505. ret = clk_prepare_enable(dw_wdt->pclk);
  506. if (ret)
  507. goto out_disable_clk;
  508. dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  509. if (IS_ERR(dw_wdt->rst)) {
  510. ret = PTR_ERR(dw_wdt->rst);
  511. goto out_disable_pclk;
  512. }
  513. /* Enable normal reset without pre-timeout by default. */
  514. dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
  515. /*
  516. * Pre-timeout IRQ is optional, since some hardware may lack support
  517. * of it. Note we must request rising-edge IRQ, since the lane is left
  518. * pending either until the next watchdog kick event or up to the
  519. * system reset.
  520. */
  521. ret = platform_get_irq_optional(pdev, 0);
  522. if (ret > 0) {
  523. ret = devm_request_irq(dev, ret, dw_wdt_irq,
  524. IRQF_SHARED | IRQF_TRIGGER_RISING,
  525. pdev->name, dw_wdt);
  526. if (ret)
  527. goto out_disable_pclk;
  528. dw_wdt->wdd.info = &dw_wdt_pt_ident;
  529. } else {
  530. if (ret == -EPROBE_DEFER)
  531. goto out_disable_pclk;
  532. dw_wdt->wdd.info = &dw_wdt_ident;
  533. }
  534. reset_control_deassert(dw_wdt->rst);
  535. ret = dw_wdt_init_timeouts(dw_wdt, dev);
  536. if (ret)
  537. goto out_disable_clk;
  538. wdd = &dw_wdt->wdd;
  539. wdd->ops = &dw_wdt_ops;
  540. wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
  541. wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
  542. wdd->parent = dev;
  543. watchdog_set_drvdata(wdd, dw_wdt);
  544. watchdog_set_nowayout(wdd, nowayout);
  545. watchdog_init_timeout(wdd, 0, dev);
  546. /*
  547. * If the watchdog is already running, use its already configured
  548. * timeout. Otherwise use the default or the value provided through
  549. * devicetree.
  550. */
  551. if (dw_wdt_is_enabled(dw_wdt)) {
  552. wdd->timeout = dw_wdt_get_timeout(dw_wdt);
  553. set_bit(WDOG_HW_RUNNING, &wdd->status);
  554. } else {
  555. wdd->timeout = DW_WDT_DEFAULT_SECONDS;
  556. watchdog_init_timeout(wdd, 0, dev);
  557. }
  558. platform_set_drvdata(pdev, dw_wdt);
  559. watchdog_set_restart_priority(wdd, 128);
  560. ret = watchdog_register_device(wdd);
  561. if (ret)
  562. goto out_disable_pclk;
  563. dw_wdt_dbgfs_init(dw_wdt);
  564. return 0;
  565. out_disable_pclk:
  566. clk_disable_unprepare(dw_wdt->pclk);
  567. out_disable_clk:
  568. clk_disable_unprepare(dw_wdt->clk);
  569. return ret;
  570. }
  571. static int dw_wdt_drv_remove(struct platform_device *pdev)
  572. {
  573. struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
  574. dw_wdt_dbgfs_clear(dw_wdt);
  575. watchdog_unregister_device(&dw_wdt->wdd);
  576. reset_control_assert(dw_wdt->rst);
  577. clk_disable_unprepare(dw_wdt->pclk);
  578. clk_disable_unprepare(dw_wdt->clk);
  579. return 0;
  580. }
  581. #ifdef CONFIG_OF
  582. static const struct of_device_id dw_wdt_of_match[] = {
  583. { .compatible = "snps,dw-wdt", },
  584. { /* sentinel */ }
  585. };
  586. MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
  587. #endif
  588. static struct platform_driver dw_wdt_driver = {
  589. .probe = dw_wdt_drv_probe,
  590. .remove = dw_wdt_drv_remove,
  591. .driver = {
  592. .name = "dw_wdt",
  593. .of_match_table = of_match_ptr(dw_wdt_of_match),
  594. .pm = &dw_wdt_pm_ops,
  595. },
  596. };
  597. module_platform_driver(dw_wdt_driver);
  598. MODULE_AUTHOR("Jamie Iles");
  599. MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
  600. MODULE_LICENSE("GPL");