davinci_wdt.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/char/watchdog/davinci_wdt.c
  4. *
  5. * Watchdog driver for DaVinci DM644x/DM646x processors
  6. *
  7. * Copyright (C) 2006-2013 Texas Instruments.
  8. *
  9. * 2007 (c) MontaVista Software, Inc.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/mod_devicetable.h>
  14. #include <linux/types.h>
  15. #include <linux/kernel.h>
  16. #include <linux/watchdog.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/io.h>
  19. #include <linux/device.h>
  20. #include <linux/clk.h>
  21. #include <linux/err.h>
  22. #define MODULE_NAME "DAVINCI-WDT: "
  23. #define DEFAULT_HEARTBEAT 60
  24. #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
  25. /* Timer register set definition */
  26. #define PID12 (0x0)
  27. #define EMUMGT (0x4)
  28. #define TIM12 (0x10)
  29. #define TIM34 (0x14)
  30. #define PRD12 (0x18)
  31. #define PRD34 (0x1C)
  32. #define TCR (0x20)
  33. #define TGCR (0x24)
  34. #define WDTCR (0x28)
  35. /* TCR bit definitions */
  36. #define ENAMODE12_DISABLED (0 << 6)
  37. #define ENAMODE12_ONESHOT (1 << 6)
  38. #define ENAMODE12_PERIODIC (2 << 6)
  39. /* TGCR bit definitions */
  40. #define TIM12RS_UNRESET (1 << 0)
  41. #define TIM34RS_UNRESET (1 << 1)
  42. #define TIMMODE_64BIT_WDOG (2 << 2)
  43. /* WDTCR bit definitions */
  44. #define WDEN (1 << 14)
  45. #define WDFLAG (1 << 15)
  46. #define WDKEY_SEQ0 (0xa5c6 << 16)
  47. #define WDKEY_SEQ1 (0xda7e << 16)
  48. static int heartbeat;
  49. /*
  50. * struct to hold data for each WDT device
  51. * @base - base io address of WD device
  52. * @clk - source clock of WDT
  53. * @wdd - hold watchdog device as is in WDT core
  54. */
  55. struct davinci_wdt_device {
  56. void __iomem *base;
  57. struct clk *clk;
  58. struct watchdog_device wdd;
  59. };
  60. static int davinci_wdt_start(struct watchdog_device *wdd)
  61. {
  62. u32 tgcr;
  63. u32 timer_margin;
  64. unsigned long wdt_freq;
  65. struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
  66. wdt_freq = clk_get_rate(davinci_wdt->clk);
  67. /* disable, internal clock source */
  68. iowrite32(0, davinci_wdt->base + TCR);
  69. /* reset timer, set mode to 64-bit watchdog, and unreset */
  70. iowrite32(0, davinci_wdt->base + TGCR);
  71. tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
  72. iowrite32(tgcr, davinci_wdt->base + TGCR);
  73. /* clear counter regs */
  74. iowrite32(0, davinci_wdt->base + TIM12);
  75. iowrite32(0, davinci_wdt->base + TIM34);
  76. /* set timeout period */
  77. timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
  78. iowrite32(timer_margin, davinci_wdt->base + PRD12);
  79. timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
  80. iowrite32(timer_margin, davinci_wdt->base + PRD34);
  81. /* enable run continuously */
  82. iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
  83. /* Once the WDT is in pre-active state write to
  84. * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
  85. * write protected (except for the WDKEY field)
  86. */
  87. /* put watchdog in pre-active state */
  88. iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
  89. /* put watchdog in active state */
  90. iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
  91. return 0;
  92. }
  93. static int davinci_wdt_ping(struct watchdog_device *wdd)
  94. {
  95. struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
  96. /* put watchdog in service state */
  97. iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
  98. /* put watchdog in active state */
  99. iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
  100. return 0;
  101. }
  102. static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
  103. {
  104. u64 timer_counter;
  105. unsigned long freq;
  106. u32 val;
  107. struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
  108. /* if timeout has occured then return 0 */
  109. val = ioread32(davinci_wdt->base + WDTCR);
  110. if (val & WDFLAG)
  111. return 0;
  112. freq = clk_get_rate(davinci_wdt->clk);
  113. if (!freq)
  114. return 0;
  115. timer_counter = ioread32(davinci_wdt->base + TIM12);
  116. timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
  117. do_div(timer_counter, freq);
  118. return wdd->timeout - timer_counter;
  119. }
  120. static int davinci_wdt_restart(struct watchdog_device *wdd,
  121. unsigned long action, void *data)
  122. {
  123. struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
  124. u32 tgcr, wdtcr;
  125. /* disable, internal clock source */
  126. iowrite32(0, davinci_wdt->base + TCR);
  127. /* reset timer, set mode to 64-bit watchdog, and unreset */
  128. tgcr = 0;
  129. iowrite32(tgcr, davinci_wdt->base + TGCR);
  130. tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
  131. iowrite32(tgcr, davinci_wdt->base + TGCR);
  132. /* clear counter and period regs */
  133. iowrite32(0, davinci_wdt->base + TIM12);
  134. iowrite32(0, davinci_wdt->base + TIM34);
  135. iowrite32(0, davinci_wdt->base + PRD12);
  136. iowrite32(0, davinci_wdt->base + PRD34);
  137. /* put watchdog in pre-active state */
  138. wdtcr = WDKEY_SEQ0 | WDEN;
  139. iowrite32(wdtcr, davinci_wdt->base + WDTCR);
  140. /* put watchdog in active state */
  141. wdtcr = WDKEY_SEQ1 | WDEN;
  142. iowrite32(wdtcr, davinci_wdt->base + WDTCR);
  143. /* write an invalid value to the WDKEY field to trigger a restart */
  144. wdtcr = 0x00004000;
  145. iowrite32(wdtcr, davinci_wdt->base + WDTCR);
  146. return 0;
  147. }
  148. static const struct watchdog_info davinci_wdt_info = {
  149. .options = WDIOF_KEEPALIVEPING,
  150. .identity = "DaVinci/Keystone Watchdog",
  151. };
  152. static const struct watchdog_ops davinci_wdt_ops = {
  153. .owner = THIS_MODULE,
  154. .start = davinci_wdt_start,
  155. .stop = davinci_wdt_ping,
  156. .ping = davinci_wdt_ping,
  157. .get_timeleft = davinci_wdt_get_timeleft,
  158. .restart = davinci_wdt_restart,
  159. };
  160. static void davinci_clk_disable_unprepare(void *data)
  161. {
  162. clk_disable_unprepare(data);
  163. }
  164. static int davinci_wdt_probe(struct platform_device *pdev)
  165. {
  166. int ret = 0;
  167. struct device *dev = &pdev->dev;
  168. struct watchdog_device *wdd;
  169. struct davinci_wdt_device *davinci_wdt;
  170. davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
  171. if (!davinci_wdt)
  172. return -ENOMEM;
  173. davinci_wdt->clk = devm_clk_get(dev, NULL);
  174. if (IS_ERR(davinci_wdt->clk))
  175. return dev_err_probe(dev, PTR_ERR(davinci_wdt->clk),
  176. "failed to get clock node\n");
  177. ret = clk_prepare_enable(davinci_wdt->clk);
  178. if (ret) {
  179. dev_err(dev, "failed to prepare clock\n");
  180. return ret;
  181. }
  182. ret = devm_add_action_or_reset(dev, davinci_clk_disable_unprepare,
  183. davinci_wdt->clk);
  184. if (ret)
  185. return ret;
  186. platform_set_drvdata(pdev, davinci_wdt);
  187. wdd = &davinci_wdt->wdd;
  188. wdd->info = &davinci_wdt_info;
  189. wdd->ops = &davinci_wdt_ops;
  190. wdd->min_timeout = 1;
  191. wdd->max_timeout = MAX_HEARTBEAT;
  192. wdd->timeout = DEFAULT_HEARTBEAT;
  193. wdd->parent = dev;
  194. watchdog_init_timeout(wdd, heartbeat, dev);
  195. dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
  196. watchdog_set_drvdata(wdd, davinci_wdt);
  197. watchdog_set_nowayout(wdd, 1);
  198. watchdog_set_restart_priority(wdd, 128);
  199. davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
  200. if (IS_ERR(davinci_wdt->base))
  201. return PTR_ERR(davinci_wdt->base);
  202. return devm_watchdog_register_device(dev, wdd);
  203. }
  204. static const struct of_device_id davinci_wdt_of_match[] = {
  205. { .compatible = "ti,davinci-wdt", },
  206. {},
  207. };
  208. MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
  209. static struct platform_driver platform_wdt_driver = {
  210. .driver = {
  211. .name = "davinci-wdt",
  212. .of_match_table = davinci_wdt_of_match,
  213. },
  214. .probe = davinci_wdt_probe,
  215. };
  216. module_platform_driver(platform_wdt_driver);
  217. MODULE_AUTHOR("Texas Instruments");
  218. MODULE_DESCRIPTION("DaVinci Watchdog Driver");
  219. module_param(heartbeat, int, 0);
  220. MODULE_PARM_DESC(heartbeat,
  221. "Watchdog heartbeat period in seconds from 1 to "
  222. __MODULE_STRING(MAX_HEARTBEAT) ", default "
  223. __MODULE_STRING(DEFAULT_HEARTBEAT));
  224. MODULE_LICENSE("GPL");
  225. MODULE_ALIAS("platform:davinci-wdt");