coh901327_wdt.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * coh901327_wdt.c
  4. *
  5. * Copyright (C) 2008-2009 ST-Ericsson AB
  6. * Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
  7. * Author: Linus Walleij <linus.walleij@stericsson.com>
  8. */
  9. #include <linux/moduleparam.h>
  10. #include <linux/mod_devicetable.h>
  11. #include <linux/types.h>
  12. #include <linux/watchdog.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/pm.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <linux/bitops.h>
  18. #include <linux/clk.h>
  19. #include <linux/delay.h>
  20. #include <linux/err.h>
  21. #define DRV_NAME "WDOG COH 901 327"
  22. /*
  23. * COH 901 327 register definitions
  24. */
  25. /* WDOG_FEED Register 32bit (-/W) */
  26. #define U300_WDOG_FR 0x00
  27. #define U300_WDOG_FR_FEED_RESTART_TIMER 0xFEEDU
  28. /* WDOG_TIMEOUT Register 32bit (R/W) */
  29. #define U300_WDOG_TR 0x04
  30. #define U300_WDOG_TR_TIMEOUT_MASK 0x7FFFU
  31. /* WDOG_DISABLE1 Register 32bit (-/W) */
  32. #define U300_WDOG_D1R 0x08
  33. #define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER 0x2BADU
  34. /* WDOG_DISABLE2 Register 32bit (R/W) */
  35. #define U300_WDOG_D2R 0x0C
  36. #define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER 0xCAFEU
  37. #define U300_WDOG_D2R_DISABLE_STATUS_DISABLED 0xDABEU
  38. #define U300_WDOG_D2R_DISABLE_STATUS_ENABLED 0x0000U
  39. /* WDOG_STATUS Register 32bit (R/W) */
  40. #define U300_WDOG_SR 0x10
  41. #define U300_WDOG_SR_STATUS_TIMED_OUT 0xCFE8U
  42. #define U300_WDOG_SR_STATUS_NORMAL 0x0000U
  43. #define U300_WDOG_SR_RESET_STATUS_RESET 0xE8B4U
  44. /* WDOG_COUNT Register 32bit (R/-) */
  45. #define U300_WDOG_CR 0x14
  46. #define U300_WDOG_CR_VALID_IND 0x8000U
  47. #define U300_WDOG_CR_VALID_STABLE 0x0000U
  48. #define U300_WDOG_CR_COUNT_VALUE_MASK 0x7FFFU
  49. /* WDOG_JTAGOVR Register 32bit (R/W) */
  50. #define U300_WDOG_JOR 0x18
  51. #define U300_WDOG_JOR_JTAG_MODE_IND 0x0002U
  52. #define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE 0x0001U
  53. /* WDOG_RESTART Register 32bit (-/W) */
  54. #define U300_WDOG_RR 0x1C
  55. #define U300_WDOG_RR_RESTART_VALUE_RESUME 0xACEDU
  56. /* WDOG_IRQ_EVENT Register 32bit (R/W) */
  57. #define U300_WDOG_IER 0x20
  58. #define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND 0x0001U
  59. #define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE 0x0001U
  60. /* WDOG_IRQ_MASK Register 32bit (R/W) */
  61. #define U300_WDOG_IMR 0x24
  62. #define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE 0x0001U
  63. /* WDOG_IRQ_FORCE Register 32bit (R/W) */
  64. #define U300_WDOG_IFR 0x28
  65. #define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE 0x0001U
  66. /* Default timeout in seconds = 1 minute */
  67. #define U300_WDOG_DEFAULT_TIMEOUT 60
  68. static unsigned int margin;
  69. static int irq;
  70. static void __iomem *virtbase;
  71. static struct device *parent;
  72. static struct clk *clk;
  73. /*
  74. * Enabling and disabling functions.
  75. */
  76. static void coh901327_enable(u16 timeout)
  77. {
  78. u16 val;
  79. unsigned long freq;
  80. unsigned long delay_ns;
  81. /* Restart timer if it is disabled */
  82. val = readw(virtbase + U300_WDOG_D2R);
  83. if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
  84. writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
  85. virtbase + U300_WDOG_RR);
  86. /* Acknowledge any pending interrupt so it doesn't just fire off */
  87. writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
  88. virtbase + U300_WDOG_IER);
  89. /*
  90. * The interrupt is cleared in the 32 kHz clock domain.
  91. * Wait 3 32 kHz cycles for it to take effect
  92. */
  93. freq = clk_get_rate(clk);
  94. delay_ns = DIV_ROUND_UP(1000000000, freq); /* Freq to ns and round up */
  95. delay_ns = 3 * delay_ns; /* Wait 3 cycles */
  96. ndelay(delay_ns);
  97. /* Enable the watchdog interrupt */
  98. writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
  99. /* Activate the watchdog timer */
  100. writew(timeout, virtbase + U300_WDOG_TR);
  101. /* Start the watchdog timer */
  102. writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
  103. /*
  104. * Extra read so that this change propagate in the watchdog.
  105. */
  106. (void) readw(virtbase + U300_WDOG_CR);
  107. val = readw(virtbase + U300_WDOG_D2R);
  108. if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
  109. dev_err(parent,
  110. "%s(): watchdog not enabled! D2R value %04x\n",
  111. __func__, val);
  112. }
  113. static void coh901327_disable(void)
  114. {
  115. u16 val;
  116. /* Disable the watchdog interrupt if it is active */
  117. writew(0x0000U, virtbase + U300_WDOG_IMR);
  118. /* If the watchdog is currently enabled, attempt to disable it */
  119. val = readw(virtbase + U300_WDOG_D2R);
  120. if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
  121. writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
  122. virtbase + U300_WDOG_D1R);
  123. writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
  124. virtbase + U300_WDOG_D2R);
  125. /* Write this twice (else problems occur) */
  126. writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
  127. virtbase + U300_WDOG_D2R);
  128. }
  129. val = readw(virtbase + U300_WDOG_D2R);
  130. if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
  131. dev_err(parent,
  132. "%s(): watchdog not disabled! D2R value %04x\n",
  133. __func__, val);
  134. }
  135. static int coh901327_start(struct watchdog_device *wdt_dev)
  136. {
  137. coh901327_enable(wdt_dev->timeout * 100);
  138. return 0;
  139. }
  140. static int coh901327_stop(struct watchdog_device *wdt_dev)
  141. {
  142. coh901327_disable();
  143. return 0;
  144. }
  145. static int coh901327_ping(struct watchdog_device *wdd)
  146. {
  147. /* Feed the watchdog */
  148. writew(U300_WDOG_FR_FEED_RESTART_TIMER,
  149. virtbase + U300_WDOG_FR);
  150. return 0;
  151. }
  152. static int coh901327_settimeout(struct watchdog_device *wdt_dev,
  153. unsigned int time)
  154. {
  155. wdt_dev->timeout = time;
  156. /* Set new timeout value */
  157. writew(time * 100, virtbase + U300_WDOG_TR);
  158. /* Feed the dog */
  159. writew(U300_WDOG_FR_FEED_RESTART_TIMER,
  160. virtbase + U300_WDOG_FR);
  161. return 0;
  162. }
  163. static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
  164. {
  165. u16 val;
  166. /* Read repeatedly until the value is stable! */
  167. val = readw(virtbase + U300_WDOG_CR);
  168. while (val & U300_WDOG_CR_VALID_IND)
  169. val = readw(virtbase + U300_WDOG_CR);
  170. val &= U300_WDOG_CR_COUNT_VALUE_MASK;
  171. if (val != 0)
  172. val /= 100;
  173. return val;
  174. }
  175. /*
  176. * This interrupt occurs 10 ms before the watchdog WILL bark.
  177. */
  178. static irqreturn_t coh901327_interrupt(int irq, void *data)
  179. {
  180. u16 val;
  181. /*
  182. * Ack IRQ? If this occurs we're FUBAR anyway, so
  183. * just acknowledge, disable the interrupt and await the imminent end.
  184. * If you at some point need a host of callbacks to be called
  185. * when the system is about to watchdog-reset, add them here!
  186. *
  187. * NOTE: on future versions of this IP-block, it will be possible
  188. * to prevent a watchdog reset by feeding the watchdog at this
  189. * point.
  190. */
  191. val = readw(virtbase + U300_WDOG_IER);
  192. if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
  193. writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
  194. virtbase + U300_WDOG_IER);
  195. writew(0x0000U, virtbase + U300_WDOG_IMR);
  196. dev_crit(parent, "watchdog is barking!\n");
  197. return IRQ_HANDLED;
  198. }
  199. static const struct watchdog_info coh901327_ident = {
  200. .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  201. .identity = DRV_NAME,
  202. };
  203. static const struct watchdog_ops coh901327_ops = {
  204. .owner = THIS_MODULE,
  205. .start = coh901327_start,
  206. .stop = coh901327_stop,
  207. .ping = coh901327_ping,
  208. .set_timeout = coh901327_settimeout,
  209. .get_timeleft = coh901327_gettimeleft,
  210. };
  211. static struct watchdog_device coh901327_wdt = {
  212. .info = &coh901327_ident,
  213. .ops = &coh901327_ops,
  214. /*
  215. * Max timeout is 327 since the 10ms
  216. * timeout register is max
  217. * 0x7FFF = 327670ms ~= 327s.
  218. */
  219. .min_timeout = 1,
  220. .max_timeout = 327,
  221. .timeout = U300_WDOG_DEFAULT_TIMEOUT,
  222. };
  223. static int __init coh901327_probe(struct platform_device *pdev)
  224. {
  225. struct device *dev = &pdev->dev;
  226. int ret;
  227. u16 val;
  228. parent = dev;
  229. virtbase = devm_platform_ioremap_resource(pdev, 0);
  230. if (IS_ERR(virtbase))
  231. return PTR_ERR(virtbase);
  232. clk = clk_get(dev, NULL);
  233. if (IS_ERR(clk)) {
  234. ret = PTR_ERR(clk);
  235. dev_err(dev, "could not get clock\n");
  236. return ret;
  237. }
  238. ret = clk_prepare_enable(clk);
  239. if (ret) {
  240. dev_err(dev, "could not prepare and enable clock\n");
  241. goto out_no_clk_enable;
  242. }
  243. val = readw(virtbase + U300_WDOG_SR);
  244. switch (val) {
  245. case U300_WDOG_SR_STATUS_TIMED_OUT:
  246. dev_info(dev, "watchdog timed out since last chip reset!\n");
  247. coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
  248. /* Status will be cleared below */
  249. break;
  250. case U300_WDOG_SR_STATUS_NORMAL:
  251. dev_info(dev, "in normal status, no timeouts have occurred.\n");
  252. break;
  253. default:
  254. dev_info(dev, "contains an illegal status code (%08x)\n", val);
  255. break;
  256. }
  257. val = readw(virtbase + U300_WDOG_D2R);
  258. switch (val) {
  259. case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
  260. dev_info(dev, "currently disabled.\n");
  261. break;
  262. case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
  263. dev_info(dev, "currently enabled! (disabling it now)\n");
  264. coh901327_disable();
  265. break;
  266. default:
  267. dev_err(dev, "contains an illegal enable/disable code (%08x)\n",
  268. val);
  269. break;
  270. }
  271. /* Reset the watchdog */
  272. writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
  273. irq = platform_get_irq(pdev, 0);
  274. if (request_irq(irq, coh901327_interrupt, 0,
  275. DRV_NAME " Bark", pdev)) {
  276. ret = -EIO;
  277. goto out_no_irq;
  278. }
  279. watchdog_init_timeout(&coh901327_wdt, margin, dev);
  280. coh901327_wdt.parent = dev;
  281. ret = watchdog_register_device(&coh901327_wdt);
  282. if (ret)
  283. goto out_no_wdog;
  284. dev_info(dev, "initialized. (timeout=%d sec)\n",
  285. coh901327_wdt.timeout);
  286. return 0;
  287. out_no_wdog:
  288. free_irq(irq, pdev);
  289. out_no_irq:
  290. clk_disable_unprepare(clk);
  291. out_no_clk_enable:
  292. clk_put(clk);
  293. return ret;
  294. }
  295. #ifdef CONFIG_PM
  296. static u16 wdogenablestore;
  297. static u16 irqmaskstore;
  298. static int coh901327_suspend(struct platform_device *pdev, pm_message_t state)
  299. {
  300. irqmaskstore = readw(virtbase + U300_WDOG_IMR) & 0x0001U;
  301. wdogenablestore = readw(virtbase + U300_WDOG_D2R);
  302. /* If watchdog is on, disable it here and now */
  303. if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
  304. coh901327_disable();
  305. return 0;
  306. }
  307. static int coh901327_resume(struct platform_device *pdev)
  308. {
  309. /* Restore the watchdog interrupt */
  310. writew(irqmaskstore, virtbase + U300_WDOG_IMR);
  311. if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED) {
  312. /* Restart the watchdog timer */
  313. writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
  314. virtbase + U300_WDOG_RR);
  315. writew(U300_WDOG_FR_FEED_RESTART_TIMER,
  316. virtbase + U300_WDOG_FR);
  317. }
  318. return 0;
  319. }
  320. #else
  321. #define coh901327_suspend NULL
  322. #define coh901327_resume NULL
  323. #endif
  324. /*
  325. * Mistreating the watchdog is the only way to perform a software reset of the
  326. * system on EMP platforms. So we implement this and export a symbol for it.
  327. */
  328. void coh901327_watchdog_reset(void)
  329. {
  330. /* Enable even if on JTAG too */
  331. writew(U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE,
  332. virtbase + U300_WDOG_JOR);
  333. /*
  334. * Timeout = 5s, we have to wait for the watchdog reset to
  335. * actually take place: the watchdog will be reloaded with the
  336. * default value immediately, so we HAVE to reboot and get back
  337. * into the kernel in 30s, or the device will reboot again!
  338. * The boot loader will typically deactivate the watchdog, so we
  339. * need time enough for the boot loader to get to the point of
  340. * deactivating the watchdog before it is shut down by it.
  341. *
  342. * NOTE: on future versions of the watchdog, this restriction is
  343. * gone: the watchdog will be reloaded with a default value (1 min)
  344. * instead of last value, and you can conveniently set the watchdog
  345. * timeout to 10ms (value = 1) without any problems.
  346. */
  347. coh901327_enable(500);
  348. /* Return and await doom */
  349. }
  350. static const struct of_device_id coh901327_dt_match[] = {
  351. { .compatible = "stericsson,coh901327" },
  352. {},
  353. };
  354. static struct platform_driver coh901327_driver = {
  355. .driver = {
  356. .name = "coh901327_wdog",
  357. .of_match_table = coh901327_dt_match,
  358. .suppress_bind_attrs = true,
  359. },
  360. .suspend = coh901327_suspend,
  361. .resume = coh901327_resume,
  362. };
  363. builtin_platform_driver_probe(coh901327_driver, coh901327_probe);
  364. /* not really modular, but ... */
  365. module_param(margin, uint, 0);
  366. MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");