bcm2835_wdt.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Watchdog driver for Broadcom BCM2835
  4. *
  5. * "bcm2708_wdog" driver written by Luke Diamand that was obtained from
  6. * branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used
  7. * as a hardware reference for the Broadcom BCM2835 watchdog timer.
  8. *
  9. * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk>
  10. *
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/types.h>
  14. #include <linux/mfd/bcm2835-pm.h>
  15. #include <linux/module.h>
  16. #include <linux/io.h>
  17. #include <linux/watchdog.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_platform.h>
  21. #define PM_RSTC 0x1c
  22. #define PM_RSTS 0x20
  23. #define PM_WDOG 0x24
  24. #define PM_PASSWORD 0x5a000000
  25. #define PM_WDOG_TIME_SET 0x000fffff
  26. #define PM_RSTC_WRCFG_CLR 0xffffffcf
  27. #define PM_RSTS_HADWRH_SET 0x00000040
  28. #define PM_RSTC_WRCFG_SET 0x00000030
  29. #define PM_RSTC_WRCFG_FULL_RESET 0x00000020
  30. #define PM_RSTC_RESET 0x00000102
  31. /*
  32. * The Raspberry Pi firmware uses the RSTS register to know which partition
  33. * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10.
  34. * Partition 63 is a special partition used by the firmware to indicate halt.
  35. */
  36. #define PM_RSTS_RASPBERRYPI_HALT 0x555
  37. #define SECS_TO_WDOG_TICKS(x) ((x) << 16)
  38. #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
  39. struct bcm2835_wdt {
  40. void __iomem *base;
  41. spinlock_t lock;
  42. };
  43. static struct bcm2835_wdt *bcm2835_power_off_wdt;
  44. static unsigned int heartbeat;
  45. static bool nowayout = WATCHDOG_NOWAYOUT;
  46. static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt)
  47. {
  48. uint32_t cur;
  49. cur = readl(wdt->base + PM_RSTC);
  50. return !!(cur & PM_RSTC_WRCFG_FULL_RESET);
  51. }
  52. static int bcm2835_wdt_start(struct watchdog_device *wdog)
  53. {
  54. struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  55. uint32_t cur;
  56. unsigned long flags;
  57. spin_lock_irqsave(&wdt->lock, flags);
  58. writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) &
  59. PM_WDOG_TIME_SET), wdt->base + PM_WDOG);
  60. cur = readl_relaxed(wdt->base + PM_RSTC);
  61. writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
  62. PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC);
  63. spin_unlock_irqrestore(&wdt->lock, flags);
  64. return 0;
  65. }
  66. static int bcm2835_wdt_stop(struct watchdog_device *wdog)
  67. {
  68. struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  69. writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC);
  70. return 0;
  71. }
  72. static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog)
  73. {
  74. struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  75. uint32_t ret = readl_relaxed(wdt->base + PM_WDOG);
  76. return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
  77. }
  78. static void __bcm2835_restart(struct bcm2835_wdt *wdt)
  79. {
  80. u32 val;
  81. /* use a timeout of 10 ticks (~150us) */
  82. writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
  83. val = readl_relaxed(wdt->base + PM_RSTC);
  84. val &= PM_RSTC_WRCFG_CLR;
  85. val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
  86. writel_relaxed(val, wdt->base + PM_RSTC);
  87. /* No sleeping, possibly atomic. */
  88. mdelay(1);
  89. }
  90. static int bcm2835_restart(struct watchdog_device *wdog,
  91. unsigned long action, void *data)
  92. {
  93. struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  94. __bcm2835_restart(wdt);
  95. return 0;
  96. }
  97. static const struct watchdog_ops bcm2835_wdt_ops = {
  98. .owner = THIS_MODULE,
  99. .start = bcm2835_wdt_start,
  100. .stop = bcm2835_wdt_stop,
  101. .get_timeleft = bcm2835_wdt_get_timeleft,
  102. .restart = bcm2835_restart,
  103. };
  104. static const struct watchdog_info bcm2835_wdt_info = {
  105. .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
  106. WDIOF_KEEPALIVEPING,
  107. .identity = "Broadcom BCM2835 Watchdog timer",
  108. };
  109. static struct watchdog_device bcm2835_wdt_wdd = {
  110. .info = &bcm2835_wdt_info,
  111. .ops = &bcm2835_wdt_ops,
  112. .min_timeout = 1,
  113. .max_timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
  114. .timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
  115. };
  116. /*
  117. * We can't really power off, but if we do the normal reset scheme, and
  118. * indicate to bootcode.bin not to reboot, then most of the chip will be
  119. * powered off.
  120. */
  121. static void bcm2835_power_off(void)
  122. {
  123. struct bcm2835_wdt *wdt = bcm2835_power_off_wdt;
  124. u32 val;
  125. /*
  126. * We set the watchdog hard reset bit here to distinguish this reset
  127. * from the normal (full) reset. bootcode.bin will not reboot after a
  128. * hard reset.
  129. */
  130. val = readl_relaxed(wdt->base + PM_RSTS);
  131. val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT;
  132. writel_relaxed(val, wdt->base + PM_RSTS);
  133. /* Continue with normal reset mechanism */
  134. __bcm2835_restart(wdt);
  135. }
  136. static int bcm2835_wdt_probe(struct platform_device *pdev)
  137. {
  138. struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
  139. struct device *dev = &pdev->dev;
  140. struct bcm2835_wdt *wdt;
  141. int err;
  142. wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL);
  143. if (!wdt)
  144. return -ENOMEM;
  145. spin_lock_init(&wdt->lock);
  146. wdt->base = pm->base;
  147. watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt);
  148. watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev);
  149. watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout);
  150. bcm2835_wdt_wdd.parent = dev;
  151. if (bcm2835_wdt_is_running(wdt)) {
  152. /*
  153. * The currently active timeout value (set by the
  154. * bootloader) may be different from the module
  155. * heartbeat parameter or the value in device
  156. * tree. But we just need to set WDOG_HW_RUNNING,
  157. * because then the framework will "immediately" ping
  158. * the device, updating the timeout.
  159. */
  160. set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status);
  161. }
  162. watchdog_set_restart_priority(&bcm2835_wdt_wdd, 128);
  163. watchdog_stop_on_reboot(&bcm2835_wdt_wdd);
  164. err = devm_watchdog_register_device(dev, &bcm2835_wdt_wdd);
  165. if (err)
  166. return err;
  167. if (pm_power_off == NULL) {
  168. pm_power_off = bcm2835_power_off;
  169. bcm2835_power_off_wdt = wdt;
  170. }
  171. dev_info(dev, "Broadcom BCM2835 watchdog timer");
  172. return 0;
  173. }
  174. static int bcm2835_wdt_remove(struct platform_device *pdev)
  175. {
  176. if (pm_power_off == bcm2835_power_off)
  177. pm_power_off = NULL;
  178. return 0;
  179. }
  180. static struct platform_driver bcm2835_wdt_driver = {
  181. .probe = bcm2835_wdt_probe,
  182. .remove = bcm2835_wdt_remove,
  183. .driver = {
  184. .name = "bcm2835-wdt",
  185. },
  186. };
  187. module_platform_driver(bcm2835_wdt_driver);
  188. module_param(heartbeat, uint, 0);
  189. MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
  190. module_param(nowayout, bool, 0);
  191. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  192. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  193. MODULE_ALIAS("platform:bcm2835-wdt");
  194. MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
  195. MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer");
  196. MODULE_LICENSE("GPL");