ath79_wdt.c 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer.
  4. *
  5. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  6. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  7. *
  8. * This driver was based on: drivers/watchdog/ixp4xx_wdt.c
  9. * Author: Deepak Saxena <dsaxena@plexity.net>
  10. * Copyright 2004 (c) MontaVista, Software, Inc.
  11. *
  12. * which again was based on sa1100 driver,
  13. * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
  14. */
  15. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <linux/fs.h>
  20. #include <linux/io.h>
  21. #include <linux/kernel.h>
  22. #include <linux/miscdevice.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/types.h>
  27. #include <linux/watchdog.h>
  28. #include <linux/clk.h>
  29. #include <linux/err.h>
  30. #include <linux/of.h>
  31. #include <linux/of_platform.h>
  32. #include <linux/uaccess.h>
  33. #define DRIVER_NAME "ath79-wdt"
  34. #define WDT_TIMEOUT 15 /* seconds */
  35. #define WDOG_REG_CTRL 0x00
  36. #define WDOG_REG_TIMER 0x04
  37. #define WDOG_CTRL_LAST_RESET BIT(31)
  38. #define WDOG_CTRL_ACTION_MASK 3
  39. #define WDOG_CTRL_ACTION_NONE 0 /* no action */
  40. #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
  41. #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
  42. #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
  43. static bool nowayout = WATCHDOG_NOWAYOUT;
  44. module_param(nowayout, bool, 0);
  45. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  46. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  47. static int timeout = WDT_TIMEOUT;
  48. module_param(timeout, int, 0);
  49. MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds "
  50. "(default=" __MODULE_STRING(WDT_TIMEOUT) "s)");
  51. static unsigned long wdt_flags;
  52. #define WDT_FLAGS_BUSY 0
  53. #define WDT_FLAGS_EXPECT_CLOSE 1
  54. static struct clk *wdt_clk;
  55. static unsigned long wdt_freq;
  56. static int boot_status;
  57. static int max_timeout;
  58. static void __iomem *wdt_base;
  59. static inline void ath79_wdt_wr(unsigned reg, u32 val)
  60. {
  61. iowrite32(val, wdt_base + reg);
  62. }
  63. static inline u32 ath79_wdt_rr(unsigned reg)
  64. {
  65. return ioread32(wdt_base + reg);
  66. }
  67. static inline void ath79_wdt_keepalive(void)
  68. {
  69. ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
  70. /* flush write */
  71. ath79_wdt_rr(WDOG_REG_TIMER);
  72. }
  73. static inline void ath79_wdt_enable(void)
  74. {
  75. ath79_wdt_keepalive();
  76. /*
  77. * Updating the TIMER register requires a few microseconds
  78. * on the AR934x SoCs at least. Use a small delay to ensure
  79. * that the TIMER register is updated within the hardware
  80. * before enabling the watchdog.
  81. */
  82. udelay(2);
  83. ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
  84. /* flush write */
  85. ath79_wdt_rr(WDOG_REG_CTRL);
  86. }
  87. static inline void ath79_wdt_disable(void)
  88. {
  89. ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
  90. /* flush write */
  91. ath79_wdt_rr(WDOG_REG_CTRL);
  92. }
  93. static int ath79_wdt_set_timeout(int val)
  94. {
  95. if (val < 1 || val > max_timeout)
  96. return -EINVAL;
  97. timeout = val;
  98. ath79_wdt_keepalive();
  99. return 0;
  100. }
  101. static int ath79_wdt_open(struct inode *inode, struct file *file)
  102. {
  103. if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags))
  104. return -EBUSY;
  105. clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
  106. ath79_wdt_enable();
  107. return stream_open(inode, file);
  108. }
  109. static int ath79_wdt_release(struct inode *inode, struct file *file)
  110. {
  111. if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags))
  112. ath79_wdt_disable();
  113. else {
  114. pr_crit("device closed unexpectedly, watchdog timer will not stop!\n");
  115. ath79_wdt_keepalive();
  116. }
  117. clear_bit(WDT_FLAGS_BUSY, &wdt_flags);
  118. clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
  119. return 0;
  120. }
  121. static ssize_t ath79_wdt_write(struct file *file, const char *data,
  122. size_t len, loff_t *ppos)
  123. {
  124. if (len) {
  125. if (!nowayout) {
  126. size_t i;
  127. clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
  128. for (i = 0; i != len; i++) {
  129. char c;
  130. if (get_user(c, data + i))
  131. return -EFAULT;
  132. if (c == 'V')
  133. set_bit(WDT_FLAGS_EXPECT_CLOSE,
  134. &wdt_flags);
  135. }
  136. }
  137. ath79_wdt_keepalive();
  138. }
  139. return len;
  140. }
  141. static const struct watchdog_info ath79_wdt_info = {
  142. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  143. WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
  144. .firmware_version = 0,
  145. .identity = "ATH79 watchdog",
  146. };
  147. static long ath79_wdt_ioctl(struct file *file, unsigned int cmd,
  148. unsigned long arg)
  149. {
  150. void __user *argp = (void __user *)arg;
  151. int __user *p = argp;
  152. int err;
  153. int t;
  154. switch (cmd) {
  155. case WDIOC_GETSUPPORT:
  156. err = copy_to_user(argp, &ath79_wdt_info,
  157. sizeof(ath79_wdt_info)) ? -EFAULT : 0;
  158. break;
  159. case WDIOC_GETSTATUS:
  160. err = put_user(0, p);
  161. break;
  162. case WDIOC_GETBOOTSTATUS:
  163. err = put_user(boot_status, p);
  164. break;
  165. case WDIOC_KEEPALIVE:
  166. ath79_wdt_keepalive();
  167. err = 0;
  168. break;
  169. case WDIOC_SETTIMEOUT:
  170. err = get_user(t, p);
  171. if (err)
  172. break;
  173. err = ath79_wdt_set_timeout(t);
  174. if (err)
  175. break;
  176. fallthrough;
  177. case WDIOC_GETTIMEOUT:
  178. err = put_user(timeout, p);
  179. break;
  180. default:
  181. err = -ENOTTY;
  182. break;
  183. }
  184. return err;
  185. }
  186. static const struct file_operations ath79_wdt_fops = {
  187. .owner = THIS_MODULE,
  188. .llseek = no_llseek,
  189. .write = ath79_wdt_write,
  190. .unlocked_ioctl = ath79_wdt_ioctl,
  191. .compat_ioctl = compat_ptr_ioctl,
  192. .open = ath79_wdt_open,
  193. .release = ath79_wdt_release,
  194. };
  195. static struct miscdevice ath79_wdt_miscdev = {
  196. .minor = WATCHDOG_MINOR,
  197. .name = "watchdog",
  198. .fops = &ath79_wdt_fops,
  199. };
  200. static int ath79_wdt_probe(struct platform_device *pdev)
  201. {
  202. u32 ctrl;
  203. int err;
  204. if (wdt_base)
  205. return -EBUSY;
  206. wdt_base = devm_platform_ioremap_resource(pdev, 0);
  207. if (IS_ERR(wdt_base))
  208. return PTR_ERR(wdt_base);
  209. wdt_clk = devm_clk_get(&pdev->dev, "wdt");
  210. if (IS_ERR(wdt_clk))
  211. return PTR_ERR(wdt_clk);
  212. err = clk_prepare_enable(wdt_clk);
  213. if (err)
  214. return err;
  215. wdt_freq = clk_get_rate(wdt_clk);
  216. if (!wdt_freq) {
  217. err = -EINVAL;
  218. goto err_clk_disable;
  219. }
  220. max_timeout = (0xfffffffful / wdt_freq);
  221. if (timeout < 1 || timeout > max_timeout) {
  222. timeout = max_timeout;
  223. dev_info(&pdev->dev,
  224. "timeout value must be 0 < timeout < %d, using %d\n",
  225. max_timeout, timeout);
  226. }
  227. ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
  228. boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;
  229. err = misc_register(&ath79_wdt_miscdev);
  230. if (err) {
  231. dev_err(&pdev->dev,
  232. "unable to register misc device, err=%d\n", err);
  233. goto err_clk_disable;
  234. }
  235. return 0;
  236. err_clk_disable:
  237. clk_disable_unprepare(wdt_clk);
  238. return err;
  239. }
  240. static int ath79_wdt_remove(struct platform_device *pdev)
  241. {
  242. misc_deregister(&ath79_wdt_miscdev);
  243. clk_disable_unprepare(wdt_clk);
  244. return 0;
  245. }
  246. static void ath79_wdt_shutdown(struct platform_device *pdev)
  247. {
  248. ath79_wdt_disable();
  249. }
  250. #ifdef CONFIG_OF
  251. static const struct of_device_id ath79_wdt_match[] = {
  252. { .compatible = "qca,ar7130-wdt" },
  253. {},
  254. };
  255. MODULE_DEVICE_TABLE(of, ath79_wdt_match);
  256. #endif
  257. static struct platform_driver ath79_wdt_driver = {
  258. .probe = ath79_wdt_probe,
  259. .remove = ath79_wdt_remove,
  260. .shutdown = ath79_wdt_shutdown,
  261. .driver = {
  262. .name = DRIVER_NAME,
  263. .of_match_table = of_match_ptr(ath79_wdt_match),
  264. },
  265. };
  266. module_platform_driver(ath79_wdt_driver);
  267. MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X hardware watchdog driver");
  268. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
  269. MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org");
  270. MODULE_LICENSE("GPL v2");
  271. MODULE_ALIAS("platform:" DRIVER_NAME);