at91sam9_wdt.h 2.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * drivers/watchdog/at91sam9_wdt.h
  4. *
  5. * Copyright (C) 2007 Andrew Victor
  6. * Copyright (C) 2007 Atmel Corporation.
  7. * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
  8. *
  9. * Watchdog Timer (WDT) - System peripherals regsters.
  10. * Based on AT91SAM9261 datasheet revision D.
  11. * Based on SAM9X60 datasheet.
  12. *
  13. */
  14. #ifndef AT91_WDT_H
  15. #define AT91_WDT_H
  16. #include <linux/bits.h>
  17. #define AT91_WDT_CR 0x00 /* Watchdog Control Register */
  18. #define AT91_WDT_WDRSTT BIT(0) /* Restart */
  19. #define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */
  20. #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
  21. #define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */
  22. #define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV)
  23. #define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */
  24. #define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */
  25. #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */
  26. #define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */
  27. #define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */
  28. #define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */
  29. #define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */
  30. #define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */
  31. #define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD)
  32. #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */
  33. #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */
  34. #define AT91_WDT_SR 0x08 /* Watchdog Status Register */
  35. #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */
  36. #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */
  37. /* Watchdog Timer Value Register */
  38. #define AT91_SAM9X60_VR 0x08
  39. /* Watchdog Window Level Register */
  40. #define AT91_SAM9X60_WLR 0x0c
  41. /* Watchdog Period Value */
  42. #define AT91_SAM9X60_COUNTER (0xfffUL << 0)
  43. #define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER)
  44. /* Interrupt Enable Register */
  45. #define AT91_SAM9X60_IER 0x14
  46. /* Period Interrupt Enable */
  47. #define AT91_SAM9X60_PERINT BIT(0)
  48. /* Interrupt Disable Register */
  49. #define AT91_SAM9X60_IDR 0x18
  50. /* Interrupt Status Register */
  51. #define AT91_SAM9X60_ISR 0x1c
  52. #endif