tmiofb.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Frame Buffer Device for Toshiba Mobile IO(TMIO) controller
  4. *
  5. * Copyright(C) 2005-2006 Chris Humbert
  6. * Copyright(C) 2005 Dirk Opfer
  7. * Copytight(C) 2007,2008 Dmitry Baryshkov
  8. *
  9. * Based on:
  10. * drivers/video/w100fb.c
  11. * code written by Sharp/Lineo for 2.4 kernels
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/fb.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/delay.h>
  19. /* Why should fb driver call console functions? because console_lock() */
  20. #include <linux/console.h>
  21. #include <linux/mfd/core.h>
  22. #include <linux/mfd/tmio.h>
  23. #include <linux/uaccess.h>
  24. /*
  25. * accelerator commands
  26. */
  27. #define TMIOFB_ACC_CSADR(x) (0x00000000 | ((x) & 0x001ffffe))
  28. #define TMIOFB_ACC_CHPIX(x) (0x01000000 | ((x) & 0x000003ff))
  29. #define TMIOFB_ACC_CVPIX(x) (0x02000000 | ((x) & 0x000003ff))
  30. #define TMIOFB_ACC_PSADR(x) (0x03000000 | ((x) & 0x00fffffe))
  31. #define TMIOFB_ACC_PHPIX(x) (0x04000000 | ((x) & 0x000003ff))
  32. #define TMIOFB_ACC_PVPIX(x) (0x05000000 | ((x) & 0x000003ff))
  33. #define TMIOFB_ACC_PHOFS(x) (0x06000000 | ((x) & 0x000003ff))
  34. #define TMIOFB_ACC_PVOFS(x) (0x07000000 | ((x) & 0x000003ff))
  35. #define TMIOFB_ACC_POADR(x) (0x08000000 | ((x) & 0x00fffffe))
  36. #define TMIOFB_ACC_RSTR(x) (0x09000000 | ((x) & 0x000000ff))
  37. #define TMIOFB_ACC_TCLOR(x) (0x0A000000 | ((x) & 0x0000ffff))
  38. #define TMIOFB_ACC_FILL(x) (0x0B000000 | ((x) & 0x0000ffff))
  39. #define TMIOFB_ACC_DSADR(x) (0x0C000000 | ((x) & 0x00fffffe))
  40. #define TMIOFB_ACC_SSADR(x) (0x0D000000 | ((x) & 0x00fffffe))
  41. #define TMIOFB_ACC_DHPIX(x) (0x0E000000 | ((x) & 0x000003ff))
  42. #define TMIOFB_ACC_DVPIX(x) (0x0F000000 | ((x) & 0x000003ff))
  43. #define TMIOFB_ACC_SHPIX(x) (0x10000000 | ((x) & 0x000003ff))
  44. #define TMIOFB_ACC_SVPIX(x) (0x11000000 | ((x) & 0x000003ff))
  45. #define TMIOFB_ACC_LBINI(x) (0x12000000 | ((x) & 0x0000ffff))
  46. #define TMIOFB_ACC_LBK2(x) (0x13000000 | ((x) & 0x0000ffff))
  47. #define TMIOFB_ACC_SHBINI(x) (0x14000000 | ((x) & 0x0000ffff))
  48. #define TMIOFB_ACC_SHBK2(x) (0x15000000 | ((x) & 0x0000ffff))
  49. #define TMIOFB_ACC_SVBINI(x) (0x16000000 | ((x) & 0x0000ffff))
  50. #define TMIOFB_ACC_SVBK2(x) (0x17000000 | ((x) & 0x0000ffff))
  51. #define TMIOFB_ACC_CMGO 0x20000000
  52. #define TMIOFB_ACC_CMGO_CEND 0x00000001
  53. #define TMIOFB_ACC_CMGO_INT 0x00000002
  54. #define TMIOFB_ACC_CMGO_CMOD 0x00000010
  55. #define TMIOFB_ACC_CMGO_CDVRV 0x00000020
  56. #define TMIOFB_ACC_CMGO_CDHRV 0x00000040
  57. #define TMIOFB_ACC_CMGO_RUND 0x00008000
  58. #define TMIOFB_ACC_SCGO 0x21000000
  59. #define TMIOFB_ACC_SCGO_CEND 0x00000001
  60. #define TMIOFB_ACC_SCGO_INT 0x00000002
  61. #define TMIOFB_ACC_SCGO_ROP3 0x00000004
  62. #define TMIOFB_ACC_SCGO_TRNS 0x00000008
  63. #define TMIOFB_ACC_SCGO_DVRV 0x00000010
  64. #define TMIOFB_ACC_SCGO_DHRV 0x00000020
  65. #define TMIOFB_ACC_SCGO_SVRV 0x00000040
  66. #define TMIOFB_ACC_SCGO_SHRV 0x00000080
  67. #define TMIOFB_ACC_SCGO_DSTXY 0x00008000
  68. #define TMIOFB_ACC_SBGO 0x22000000
  69. #define TMIOFB_ACC_SBGO_CEND 0x00000001
  70. #define TMIOFB_ACC_SBGO_INT 0x00000002
  71. #define TMIOFB_ACC_SBGO_DVRV 0x00000010
  72. #define TMIOFB_ACC_SBGO_DHRV 0x00000020
  73. #define TMIOFB_ACC_SBGO_SVRV 0x00000040
  74. #define TMIOFB_ACC_SBGO_SHRV 0x00000080
  75. #define TMIOFB_ACC_SBGO_SBMD 0x00000100
  76. #define TMIOFB_ACC_FLGO 0x23000000
  77. #define TMIOFB_ACC_FLGO_CEND 0x00000001
  78. #define TMIOFB_ACC_FLGO_INT 0x00000002
  79. #define TMIOFB_ACC_FLGO_ROP3 0x00000004
  80. #define TMIOFB_ACC_LDGO 0x24000000
  81. #define TMIOFB_ACC_LDGO_CEND 0x00000001
  82. #define TMIOFB_ACC_LDGO_INT 0x00000002
  83. #define TMIOFB_ACC_LDGO_ROP3 0x00000004
  84. #define TMIOFB_ACC_LDGO_ENDPX 0x00000008
  85. #define TMIOFB_ACC_LDGO_LVRV 0x00000010
  86. #define TMIOFB_ACC_LDGO_LHRV 0x00000020
  87. #define TMIOFB_ACC_LDGO_LDMOD 0x00000040
  88. /* a FIFO is always allocated, even if acceleration is not used */
  89. #define TMIOFB_FIFO_SIZE 512
  90. /*
  91. * LCD Host Controller Configuration Register
  92. *
  93. * This iomem area supports only 16-bit IO.
  94. */
  95. #define CCR_CMD 0x04 /* Command */
  96. #define CCR_REVID 0x08 /* Revision ID */
  97. #define CCR_BASEL 0x10 /* LCD Control Reg Base Addr Low */
  98. #define CCR_BASEH 0x12 /* LCD Control Reg Base Addr High */
  99. #define CCR_UGCC 0x40 /* Unified Gated Clock Control */
  100. #define CCR_GCC 0x42 /* Gated Clock Control */
  101. #define CCR_USC 0x50 /* Unified Software Clear */
  102. #define CCR_VRAMRTC 0x60 /* VRAM Timing Control */
  103. /* 0x61 VRAM Refresh Control */
  104. #define CCR_VRAMSAC 0x62 /* VRAM Access Control */
  105. /* 0x63 VRAM Status */
  106. #define CCR_VRAMBC 0x64 /* VRAM Block Control */
  107. /*
  108. * LCD Control Register
  109. *
  110. * This iomem area supports only 16-bit IO.
  111. */
  112. #define LCR_UIS 0x000 /* Unified Interrupt Status */
  113. #define LCR_VHPN 0x008 /* VRAM Horizontal Pixel Number */
  114. #define LCR_CFSAL 0x00a /* Command FIFO Start Address Low */
  115. #define LCR_CFSAH 0x00c /* Command FIFO Start Address High */
  116. #define LCR_CFS 0x00e /* Command FIFO Size */
  117. #define LCR_CFWS 0x010 /* Command FIFO Writeable Size */
  118. #define LCR_BBIE 0x012 /* BitBLT Interrupt Enable */
  119. #define LCR_BBISC 0x014 /* BitBLT Interrupt Status and Clear */
  120. #define LCR_CCS 0x016 /* Command Count Status */
  121. #define LCR_BBES 0x018 /* BitBLT Execution Status */
  122. #define LCR_CMDL 0x01c /* Command Low */
  123. #define LCR_CMDH 0x01e /* Command High */
  124. #define LCR_CFC 0x022 /* Command FIFO Clear */
  125. #define LCR_CCIFC 0x024 /* CMOS Camera IF Control */
  126. #define LCR_HWT 0x026 /* Hardware Test */
  127. #define LCR_LCDCCRC 0x100 /* LCDC Clock and Reset Control */
  128. #define LCR_LCDCC 0x102 /* LCDC Control */
  129. #define LCR_LCDCOPC 0x104 /* LCDC Output Pin Control */
  130. #define LCR_LCDIS 0x108 /* LCD Interrupt Status */
  131. #define LCR_LCDIM 0x10a /* LCD Interrupt Mask */
  132. #define LCR_LCDIE 0x10c /* LCD Interrupt Enable */
  133. #define LCR_GDSAL 0x122 /* Graphics Display Start Address Low */
  134. #define LCR_GDSAH 0x124 /* Graphics Display Start Address High */
  135. #define LCR_VHPCL 0x12a /* VRAM Horizontal Pixel Count Low */
  136. #define LCR_VHPCH 0x12c /* VRAM Horizontal Pixel Count High */
  137. #define LCR_GM 0x12e /* Graphic Mode(VRAM access enable) */
  138. #define LCR_HT 0x140 /* Horizontal Total */
  139. #define LCR_HDS 0x142 /* Horizontal Display Start */
  140. #define LCR_HSS 0x144 /* H-Sync Start */
  141. #define LCR_HSE 0x146 /* H-Sync End */
  142. #define LCR_HNP 0x14c /* Horizontal Number of Pixels */
  143. #define LCR_VT 0x150 /* Vertical Total */
  144. #define LCR_VDS 0x152 /* Vertical Display Start */
  145. #define LCR_VSS 0x154 /* V-Sync Start */
  146. #define LCR_VSE 0x156 /* V-Sync End */
  147. #define LCR_CDLN 0x160 /* Current Display Line Number */
  148. #define LCR_ILN 0x162 /* Interrupt Line Number */
  149. #define LCR_SP 0x164 /* Sync Polarity */
  150. #define LCR_MISC 0x166 /* MISC(RGB565 mode) */
  151. #define LCR_VIHSS 0x16a /* Video Interface H-Sync Start */
  152. #define LCR_VIVS 0x16c /* Video Interface Vertical Start */
  153. #define LCR_VIVE 0x16e /* Video Interface Vertical End */
  154. #define LCR_VIVSS 0x170 /* Video Interface V-Sync Start */
  155. #define LCR_VCCIS 0x17e /* Video / CMOS Camera Interface Select */
  156. #define LCR_VIDWSAL 0x180 /* VI Data Write Start Address Low */
  157. #define LCR_VIDWSAH 0x182 /* VI Data Write Start Address High */
  158. #define LCR_VIDRSAL 0x184 /* VI Data Read Start Address Low */
  159. #define LCR_VIDRSAH 0x186 /* VI Data Read Start Address High */
  160. #define LCR_VIPDDST 0x188 /* VI Picture Data Display Start Timing */
  161. #define LCR_VIPDDET 0x186 /* VI Picture Data Display End Timing */
  162. #define LCR_VIE 0x18c /* Video Interface Enable */
  163. #define LCR_VCS 0x18e /* Video/Camera Select */
  164. #define LCR_VPHWC 0x194 /* Video Picture Horizontal Wait Count */
  165. #define LCR_VPHS 0x196 /* Video Picture Horizontal Size */
  166. #define LCR_VPVWC 0x198 /* Video Picture Vertical Wait Count */
  167. #define LCR_VPVS 0x19a /* Video Picture Vertical Size */
  168. #define LCR_PLHPIX 0x1a0 /* PLHPIX */
  169. #define LCR_XS 0x1a2 /* XStart */
  170. #define LCR_XCKHW 0x1a4 /* XCK High Width */
  171. #define LCR_STHS 0x1a8 /* STH Start */
  172. #define LCR_VT2 0x1aa /* Vertical Total */
  173. #define LCR_YCKSW 0x1ac /* YCK Start Wait */
  174. #define LCR_YSTS 0x1ae /* YST Start */
  175. #define LCR_PPOLS 0x1b0 /* #PPOL Start */
  176. #define LCR_PRECW 0x1b2 /* PREC Width */
  177. #define LCR_VCLKHW 0x1b4 /* VCLK High Width */
  178. #define LCR_OC 0x1b6 /* Output Control */
  179. static char *mode_option;
  180. struct tmiofb_par {
  181. u32 pseudo_palette[16];
  182. #ifdef CONFIG_FB_TMIO_ACCELL
  183. wait_queue_head_t wait_acc;
  184. bool use_polling;
  185. #endif
  186. void __iomem *ccr;
  187. void __iomem *lcr;
  188. };
  189. /*--------------------------------------------------------------------------*/
  190. /*
  191. * reasons for an interrupt:
  192. * uis bbisc lcdis
  193. * 0100 0001 accelerator command completed
  194. * 2000 0001 vsync start
  195. * 2000 0002 display start
  196. * 2000 0004 line number match(0x1ff mask???)
  197. */
  198. static irqreturn_t tmiofb_irq(int irq, void *__info)
  199. {
  200. struct fb_info *info = __info;
  201. struct tmiofb_par *par = info->par;
  202. unsigned int bbisc = tmio_ioread16(par->lcr + LCR_BBISC);
  203. tmio_iowrite16(bbisc, par->lcr + LCR_BBISC);
  204. #ifdef CONFIG_FB_TMIO_ACCELL
  205. /*
  206. * We were in polling mode and now we got correct irq.
  207. * Switch back to IRQ-based sync of command FIFO
  208. */
  209. if (unlikely(par->use_polling && irq != -1)) {
  210. printk(KERN_INFO "tmiofb: switching to waitq\n");
  211. par->use_polling = false;
  212. }
  213. if (bbisc & 1)
  214. wake_up(&par->wait_acc);
  215. #endif
  216. return IRQ_HANDLED;
  217. }
  218. /*--------------------------------------------------------------------------*/
  219. /*
  220. * Turns off the LCD controller and LCD host controller.
  221. */
  222. static int tmiofb_hw_stop(struct platform_device *dev)
  223. {
  224. struct tmio_fb_data *data = dev_get_platdata(&dev->dev);
  225. struct fb_info *info = platform_get_drvdata(dev);
  226. struct tmiofb_par *par = info->par;
  227. tmio_iowrite16(0, par->ccr + CCR_UGCC);
  228. tmio_iowrite16(0, par->lcr + LCR_GM);
  229. data->lcd_set_power(dev, 0);
  230. tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);
  231. return 0;
  232. }
  233. /*
  234. * Initializes the LCD host controller.
  235. */
  236. static int tmiofb_hw_init(struct platform_device *dev)
  237. {
  238. const struct mfd_cell *cell = mfd_get_cell(dev);
  239. struct fb_info *info = platform_get_drvdata(dev);
  240. struct tmiofb_par *par = info->par;
  241. const struct resource *nlcr = &cell->resources[0];
  242. const struct resource *vram = &cell->resources[2];
  243. unsigned long base;
  244. if (nlcr == NULL || vram == NULL)
  245. return -EINVAL;
  246. base = nlcr->start;
  247. tmio_iowrite16(0x003a, par->ccr + CCR_UGCC);
  248. tmio_iowrite16(0x003a, par->ccr + CCR_GCC);
  249. tmio_iowrite16(0x3f00, par->ccr + CCR_USC);
  250. msleep(2); /* wait for device to settle */
  251. tmio_iowrite16(0x0000, par->ccr + CCR_USC);
  252. tmio_iowrite16(base >> 16, par->ccr + CCR_BASEH);
  253. tmio_iowrite16(base, par->ccr + CCR_BASEL);
  254. tmio_iowrite16(0x0002, par->ccr + CCR_CMD); /* base address enable */
  255. tmio_iowrite16(0x40a8, par->ccr + CCR_VRAMRTC); /* VRAMRC, VRAMTC */
  256. tmio_iowrite16(0x0018, par->ccr + CCR_VRAMSAC); /* VRAMSTS, VRAMAC */
  257. tmio_iowrite16(0x0002, par->ccr + CCR_VRAMBC);
  258. msleep(2); /* wait for device to settle */
  259. tmio_iowrite16(0x000b, par->ccr + CCR_VRAMBC);
  260. base = vram->start + info->screen_size;
  261. tmio_iowrite16(base >> 16, par->lcr + LCR_CFSAH);
  262. tmio_iowrite16(base, par->lcr + LCR_CFSAL);
  263. tmio_iowrite16(TMIOFB_FIFO_SIZE - 1, par->lcr + LCR_CFS);
  264. tmio_iowrite16(1, par->lcr + LCR_CFC);
  265. tmio_iowrite16(1, par->lcr + LCR_BBIE);
  266. tmio_iowrite16(0, par->lcr + LCR_CFWS);
  267. return 0;
  268. }
  269. /*
  270. * Sets the LCD controller's output resolution and pixel clock
  271. */
  272. static void tmiofb_hw_mode(struct platform_device *dev)
  273. {
  274. struct tmio_fb_data *data = dev_get_platdata(&dev->dev);
  275. struct fb_info *info = platform_get_drvdata(dev);
  276. struct fb_videomode *mode = info->mode;
  277. struct tmiofb_par *par = info->par;
  278. unsigned int i;
  279. tmio_iowrite16(0, par->lcr + LCR_GM);
  280. data->lcd_set_power(dev, 0);
  281. tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);
  282. data->lcd_mode(dev, mode);
  283. data->lcd_set_power(dev, 1);
  284. tmio_iowrite16(info->fix.line_length, par->lcr + LCR_VHPN);
  285. tmio_iowrite16(0, par->lcr + LCR_GDSAH);
  286. tmio_iowrite16(0, par->lcr + LCR_GDSAL);
  287. tmio_iowrite16(info->fix.line_length >> 16, par->lcr + LCR_VHPCH);
  288. tmio_iowrite16(info->fix.line_length, par->lcr + LCR_VHPCL);
  289. tmio_iowrite16(i = 0, par->lcr + LCR_HSS);
  290. tmio_iowrite16(i += mode->hsync_len, par->lcr + LCR_HSE);
  291. tmio_iowrite16(i += mode->left_margin, par->lcr + LCR_HDS);
  292. tmio_iowrite16(i += mode->xres + mode->right_margin, par->lcr + LCR_HT);
  293. tmio_iowrite16(mode->xres, par->lcr + LCR_HNP);
  294. tmio_iowrite16(i = 0, par->lcr + LCR_VSS);
  295. tmio_iowrite16(i += mode->vsync_len, par->lcr + LCR_VSE);
  296. tmio_iowrite16(i += mode->upper_margin, par->lcr + LCR_VDS);
  297. tmio_iowrite16(i += mode->yres, par->lcr + LCR_ILN);
  298. tmio_iowrite16(i += mode->lower_margin, par->lcr + LCR_VT);
  299. tmio_iowrite16(3, par->lcr + LCR_MISC); /* RGB565 mode */
  300. tmio_iowrite16(1, par->lcr + LCR_GM); /* VRAM enable */
  301. tmio_iowrite16(0x4007, par->lcr + LCR_LCDCC);
  302. tmio_iowrite16(3, par->lcr + LCR_SP); /* sync polarity */
  303. tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);
  304. msleep(5); /* wait for device to settle */
  305. tmio_iowrite16(0x0014, par->lcr + LCR_LCDCCRC); /* STOP_CKP */
  306. msleep(5); /* wait for device to settle */
  307. tmio_iowrite16(0x0015, par->lcr + LCR_LCDCCRC); /* STOP_CKP|SOFT_RESET*/
  308. tmio_iowrite16(0xfffa, par->lcr + LCR_VCS);
  309. }
  310. /*--------------------------------------------------------------------------*/
  311. #ifdef CONFIG_FB_TMIO_ACCELL
  312. static int __must_check
  313. tmiofb_acc_wait(struct fb_info *info, unsigned int ccs)
  314. {
  315. struct tmiofb_par *par = info->par;
  316. /*
  317. * This code can be called with interrupts disabled.
  318. * So instead of relaying on irq to trigger the event,
  319. * poll the state till the necessary command is executed.
  320. */
  321. if (irqs_disabled() || par->use_polling) {
  322. int i = 0;
  323. while (tmio_ioread16(par->lcr + LCR_CCS) > ccs) {
  324. udelay(1);
  325. i++;
  326. if (i > 10000) {
  327. pr_err("tmiofb: timeout waiting for %d\n",
  328. ccs);
  329. return -ETIMEDOUT;
  330. }
  331. tmiofb_irq(-1, info);
  332. }
  333. } else {
  334. if (!wait_event_interruptible_timeout(par->wait_acc,
  335. tmio_ioread16(par->lcr + LCR_CCS) <= ccs,
  336. 1000)) {
  337. pr_err("tmiofb: timeout waiting for %d\n", ccs);
  338. return -ETIMEDOUT;
  339. }
  340. }
  341. return 0;
  342. }
  343. /*
  344. * Writes an accelerator command to the accelerator's FIFO.
  345. */
  346. static int
  347. tmiofb_acc_write(struct fb_info *info, const u32 *cmd, unsigned int count)
  348. {
  349. struct tmiofb_par *par = info->par;
  350. int ret;
  351. ret = tmiofb_acc_wait(info, TMIOFB_FIFO_SIZE - count);
  352. if (ret)
  353. return ret;
  354. for (; count; count--, cmd++) {
  355. tmio_iowrite16(*cmd >> 16, par->lcr + LCR_CMDH);
  356. tmio_iowrite16(*cmd, par->lcr + LCR_CMDL);
  357. }
  358. return ret;
  359. }
  360. /*
  361. * Wait for the accelerator to finish its operations before writing
  362. * to the framebuffer for consistent display output.
  363. */
  364. static int tmiofb_sync(struct fb_info *fbi)
  365. {
  366. struct tmiofb_par *par = fbi->par;
  367. int ret;
  368. int i = 0;
  369. ret = tmiofb_acc_wait(fbi, 0);
  370. while (tmio_ioread16(par->lcr + LCR_BBES) & 2) { /* blit active */
  371. udelay(1);
  372. i++ ;
  373. if (i > 10000) {
  374. printk(KERN_ERR "timeout waiting for blit to end!\n");
  375. return -ETIMEDOUT;
  376. }
  377. }
  378. return ret;
  379. }
  380. static void
  381. tmiofb_fillrect(struct fb_info *fbi, const struct fb_fillrect *rect)
  382. {
  383. const u32 cmd[] = {
  384. TMIOFB_ACC_DSADR((rect->dy * fbi->mode->xres + rect->dx) * 2),
  385. TMIOFB_ACC_DHPIX(rect->width - 1),
  386. TMIOFB_ACC_DVPIX(rect->height - 1),
  387. TMIOFB_ACC_FILL(rect->color),
  388. TMIOFB_ACC_FLGO,
  389. };
  390. if (fbi->state != FBINFO_STATE_RUNNING ||
  391. fbi->flags & FBINFO_HWACCEL_DISABLED) {
  392. cfb_fillrect(fbi, rect);
  393. return;
  394. }
  395. tmiofb_acc_write(fbi, cmd, ARRAY_SIZE(cmd));
  396. }
  397. static void
  398. tmiofb_copyarea(struct fb_info *fbi, const struct fb_copyarea *area)
  399. {
  400. const u32 cmd[] = {
  401. TMIOFB_ACC_DSADR((area->dy * fbi->mode->xres + area->dx) * 2),
  402. TMIOFB_ACC_DHPIX(area->width - 1),
  403. TMIOFB_ACC_DVPIX(area->height - 1),
  404. TMIOFB_ACC_SSADR((area->sy * fbi->mode->xres + area->sx) * 2),
  405. TMIOFB_ACC_SCGO,
  406. };
  407. if (fbi->state != FBINFO_STATE_RUNNING ||
  408. fbi->flags & FBINFO_HWACCEL_DISABLED) {
  409. cfb_copyarea(fbi, area);
  410. return;
  411. }
  412. tmiofb_acc_write(fbi, cmd, ARRAY_SIZE(cmd));
  413. }
  414. #endif
  415. static void tmiofb_clearscreen(struct fb_info *info)
  416. {
  417. const struct fb_fillrect rect = {
  418. .dx = 0,
  419. .dy = 0,
  420. .width = info->mode->xres,
  421. .height = info->mode->yres,
  422. .color = 0,
  423. .rop = ROP_COPY,
  424. };
  425. info->fbops->fb_fillrect(info, &rect);
  426. }
  427. static int tmiofb_vblank(struct fb_info *fbi, struct fb_vblank *vblank)
  428. {
  429. struct tmiofb_par *par = fbi->par;
  430. struct fb_videomode *mode = fbi->mode;
  431. unsigned int vcount = tmio_ioread16(par->lcr + LCR_CDLN);
  432. unsigned int vds = mode->vsync_len + mode->upper_margin;
  433. vblank->vcount = vcount;
  434. vblank->flags = FB_VBLANK_HAVE_VBLANK | FB_VBLANK_HAVE_VCOUNT
  435. | FB_VBLANK_HAVE_VSYNC;
  436. if (vcount < mode->vsync_len)
  437. vblank->flags |= FB_VBLANK_VSYNCING;
  438. if (vcount < vds || vcount > vds + mode->yres)
  439. vblank->flags |= FB_VBLANK_VBLANKING;
  440. return 0;
  441. }
  442. static int tmiofb_ioctl(struct fb_info *fbi,
  443. unsigned int cmd, unsigned long arg)
  444. {
  445. switch (cmd) {
  446. case FBIOGET_VBLANK: {
  447. struct fb_vblank vblank = {0};
  448. void __user *argp = (void __user *) arg;
  449. tmiofb_vblank(fbi, &vblank);
  450. if (copy_to_user(argp, &vblank, sizeof vblank))
  451. return -EFAULT;
  452. return 0;
  453. }
  454. #ifdef CONFIG_FB_TMIO_ACCELL
  455. case FBIO_TMIO_ACC_SYNC:
  456. tmiofb_sync(fbi);
  457. return 0;
  458. case FBIO_TMIO_ACC_WRITE: {
  459. u32 __user *argp = (void __user *) arg;
  460. u32 len;
  461. u32 acc[16];
  462. if (get_user(len, argp))
  463. return -EFAULT;
  464. if (len > ARRAY_SIZE(acc))
  465. return -EINVAL;
  466. if (copy_from_user(acc, argp + 1, sizeof(u32) * len))
  467. return -EFAULT;
  468. return tmiofb_acc_write(fbi, acc, len);
  469. }
  470. #endif
  471. }
  472. return -ENOTTY;
  473. }
  474. /*--------------------------------------------------------------------------*/
  475. /* Select the smallest mode that allows the desired resolution to be
  476. * displayed. If desired, the x and y parameters can be rounded up to
  477. * match the selected mode.
  478. */
  479. static struct fb_videomode *
  480. tmiofb_find_mode(struct fb_info *info, struct fb_var_screeninfo *var)
  481. {
  482. struct tmio_fb_data *data = dev_get_platdata(info->device);
  483. struct fb_videomode *best = NULL;
  484. int i;
  485. for (i = 0; i < data->num_modes; i++) {
  486. struct fb_videomode *mode = data->modes + i;
  487. if (mode->xres >= var->xres && mode->yres >= var->yres
  488. && (!best || (mode->xres < best->xres
  489. && mode->yres < best->yres)))
  490. best = mode;
  491. }
  492. return best;
  493. }
  494. static int tmiofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  495. {
  496. struct fb_videomode *mode;
  497. struct tmio_fb_data *data = dev_get_platdata(info->device);
  498. mode = tmiofb_find_mode(info, var);
  499. if (!mode || var->bits_per_pixel > 16)
  500. return -EINVAL;
  501. fb_videomode_to_var(var, mode);
  502. var->xres_virtual = mode->xres;
  503. var->yres_virtual = info->screen_size / (mode->xres * 2);
  504. if (var->yres_virtual < var->yres)
  505. return -EINVAL;
  506. var->xoffset = 0;
  507. var->yoffset = 0;
  508. var->bits_per_pixel = 16;
  509. var->grayscale = 0;
  510. var->red.offset = 11;
  511. var->red.length = 5;
  512. var->green.offset = 5;
  513. var->green.length = 6;
  514. var->blue.offset = 0;
  515. var->blue.length = 5;
  516. var->transp.offset = 0;
  517. var->transp.length = 0;
  518. var->nonstd = 0;
  519. var->height = data->height; /* mm */
  520. var->width = data->width; /* mm */
  521. var->rotate = 0;
  522. return 0;
  523. }
  524. static int tmiofb_set_par(struct fb_info *info)
  525. {
  526. struct fb_var_screeninfo *var = &info->var;
  527. struct fb_videomode *mode;
  528. mode = tmiofb_find_mode(info, var);
  529. if (!mode)
  530. return -EINVAL;
  531. info->mode = mode;
  532. info->fix.line_length = info->mode->xres *
  533. var->bits_per_pixel / 8;
  534. tmiofb_hw_mode(to_platform_device(info->device));
  535. tmiofb_clearscreen(info);
  536. return 0;
  537. }
  538. static int tmiofb_setcolreg(unsigned regno, unsigned red, unsigned green,
  539. unsigned blue, unsigned transp,
  540. struct fb_info *info)
  541. {
  542. struct tmiofb_par *par = info->par;
  543. if (regno < ARRAY_SIZE(par->pseudo_palette)) {
  544. par->pseudo_palette[regno] =
  545. ((red & 0xf800)) |
  546. ((green & 0xfc00) >> 5) |
  547. ((blue & 0xf800) >> 11);
  548. return 0;
  549. }
  550. return -EINVAL;
  551. }
  552. static int tmiofb_blank(int blank, struct fb_info *info)
  553. {
  554. /*
  555. * everything is done in lcd/bl drivers.
  556. * this is purely to make sysfs happy and work.
  557. */
  558. return 0;
  559. }
  560. static const struct fb_ops tmiofb_ops = {
  561. .owner = THIS_MODULE,
  562. .fb_ioctl = tmiofb_ioctl,
  563. .fb_check_var = tmiofb_check_var,
  564. .fb_set_par = tmiofb_set_par,
  565. .fb_setcolreg = tmiofb_setcolreg,
  566. .fb_blank = tmiofb_blank,
  567. .fb_imageblit = cfb_imageblit,
  568. #ifdef CONFIG_FB_TMIO_ACCELL
  569. .fb_sync = tmiofb_sync,
  570. .fb_fillrect = tmiofb_fillrect,
  571. .fb_copyarea = tmiofb_copyarea,
  572. #else
  573. .fb_fillrect = cfb_fillrect,
  574. .fb_copyarea = cfb_copyarea,
  575. #endif
  576. };
  577. /*--------------------------------------------------------------------------*/
  578. static int tmiofb_probe(struct platform_device *dev)
  579. {
  580. const struct mfd_cell *cell = mfd_get_cell(dev);
  581. struct tmio_fb_data *data = dev_get_platdata(&dev->dev);
  582. struct resource *ccr = platform_get_resource(dev, IORESOURCE_MEM, 1);
  583. struct resource *lcr = platform_get_resource(dev, IORESOURCE_MEM, 0);
  584. struct resource *vram = platform_get_resource(dev, IORESOURCE_MEM, 2);
  585. int irq = platform_get_irq(dev, 0);
  586. struct fb_info *info;
  587. struct tmiofb_par *par;
  588. int retval;
  589. /*
  590. * This is the only way ATM to disable the fb
  591. */
  592. if (data == NULL) {
  593. dev_err(&dev->dev, "NULL platform data!\n");
  594. return -EINVAL;
  595. }
  596. if (ccr == NULL || lcr == NULL || vram == NULL || irq < 0) {
  597. dev_err(&dev->dev, "missing resources\n");
  598. return -EINVAL;
  599. }
  600. info = framebuffer_alloc(sizeof(struct tmiofb_par), &dev->dev);
  601. if (!info)
  602. return -ENOMEM;
  603. par = info->par;
  604. #ifdef CONFIG_FB_TMIO_ACCELL
  605. init_waitqueue_head(&par->wait_acc);
  606. par->use_polling = true;
  607. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA
  608. | FBINFO_HWACCEL_FILLRECT;
  609. #else
  610. info->flags = FBINFO_DEFAULT;
  611. #endif
  612. info->fbops = &tmiofb_ops;
  613. strcpy(info->fix.id, "tmio-fb");
  614. info->fix.smem_start = vram->start;
  615. info->fix.smem_len = resource_size(vram);
  616. info->fix.type = FB_TYPE_PACKED_PIXELS;
  617. info->fix.visual = FB_VISUAL_TRUECOLOR;
  618. info->fix.mmio_start = lcr->start;
  619. info->fix.mmio_len = resource_size(lcr);
  620. info->fix.accel = FB_ACCEL_NONE;
  621. info->screen_size = info->fix.smem_len - (4 * TMIOFB_FIFO_SIZE);
  622. info->pseudo_palette = par->pseudo_palette;
  623. par->ccr = ioremap(ccr->start, resource_size(ccr));
  624. if (!par->ccr) {
  625. retval = -ENOMEM;
  626. goto err_ioremap_ccr;
  627. }
  628. par->lcr = ioremap(info->fix.mmio_start, info->fix.mmio_len);
  629. if (!par->lcr) {
  630. retval = -ENOMEM;
  631. goto err_ioremap_lcr;
  632. }
  633. info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
  634. if (!info->screen_base) {
  635. retval = -ENOMEM;
  636. goto err_ioremap_vram;
  637. }
  638. retval = request_irq(irq, &tmiofb_irq, 0,
  639. dev_name(&dev->dev), info);
  640. if (retval)
  641. goto err_request_irq;
  642. platform_set_drvdata(dev, info);
  643. retval = fb_find_mode(&info->var, info, mode_option,
  644. data->modes, data->num_modes,
  645. data->modes, 16);
  646. if (!retval) {
  647. retval = -EINVAL;
  648. goto err_find_mode;
  649. }
  650. if (cell->enable) {
  651. retval = cell->enable(dev);
  652. if (retval)
  653. goto err_enable;
  654. }
  655. retval = tmiofb_hw_init(dev);
  656. if (retval)
  657. goto err_hw_init;
  658. fb_videomode_to_modelist(data->modes, data->num_modes,
  659. &info->modelist);
  660. retval = register_framebuffer(info);
  661. if (retval < 0)
  662. goto err_register_framebuffer;
  663. fb_info(info, "%s frame buffer device\n", info->fix.id);
  664. return 0;
  665. err_register_framebuffer:
  666. /*err_set_par:*/
  667. tmiofb_hw_stop(dev);
  668. err_hw_init:
  669. if (cell->disable)
  670. cell->disable(dev);
  671. err_enable:
  672. err_find_mode:
  673. free_irq(irq, info);
  674. err_request_irq:
  675. iounmap(info->screen_base);
  676. err_ioremap_vram:
  677. iounmap(par->lcr);
  678. err_ioremap_lcr:
  679. iounmap(par->ccr);
  680. err_ioremap_ccr:
  681. framebuffer_release(info);
  682. return retval;
  683. }
  684. static int tmiofb_remove(struct platform_device *dev)
  685. {
  686. const struct mfd_cell *cell = mfd_get_cell(dev);
  687. struct fb_info *info = platform_get_drvdata(dev);
  688. int irq = platform_get_irq(dev, 0);
  689. struct tmiofb_par *par;
  690. if (info) {
  691. par = info->par;
  692. unregister_framebuffer(info);
  693. tmiofb_hw_stop(dev);
  694. if (cell->disable)
  695. cell->disable(dev);
  696. free_irq(irq, info);
  697. iounmap(info->screen_base);
  698. iounmap(par->lcr);
  699. iounmap(par->ccr);
  700. framebuffer_release(info);
  701. }
  702. return 0;
  703. }
  704. #ifdef DEBUG
  705. static void tmiofb_dump_regs(struct platform_device *dev)
  706. {
  707. struct fb_info *info = platform_get_drvdata(dev);
  708. struct tmiofb_par *par = info->par;
  709. printk(KERN_DEBUG "lhccr:\n");
  710. #define CCR_PR(n) printk(KERN_DEBUG "\t" #n " = \t%04x\n",\
  711. tmio_ioread16(par->ccr + CCR_ ## n));
  712. CCR_PR(CMD);
  713. CCR_PR(REVID);
  714. CCR_PR(BASEL);
  715. CCR_PR(BASEH);
  716. CCR_PR(UGCC);
  717. CCR_PR(GCC);
  718. CCR_PR(USC);
  719. CCR_PR(VRAMRTC);
  720. CCR_PR(VRAMSAC);
  721. CCR_PR(VRAMBC);
  722. #undef CCR_PR
  723. printk(KERN_DEBUG "lcr: \n");
  724. #define LCR_PR(n) printk(KERN_DEBUG "\t" #n " = \t%04x\n",\
  725. tmio_ioread16(par->lcr + LCR_ ## n));
  726. LCR_PR(UIS);
  727. LCR_PR(VHPN);
  728. LCR_PR(CFSAL);
  729. LCR_PR(CFSAH);
  730. LCR_PR(CFS);
  731. LCR_PR(CFWS);
  732. LCR_PR(BBIE);
  733. LCR_PR(BBISC);
  734. LCR_PR(CCS);
  735. LCR_PR(BBES);
  736. LCR_PR(CMDL);
  737. LCR_PR(CMDH);
  738. LCR_PR(CFC);
  739. LCR_PR(CCIFC);
  740. LCR_PR(HWT);
  741. LCR_PR(LCDCCRC);
  742. LCR_PR(LCDCC);
  743. LCR_PR(LCDCOPC);
  744. LCR_PR(LCDIS);
  745. LCR_PR(LCDIM);
  746. LCR_PR(LCDIE);
  747. LCR_PR(GDSAL);
  748. LCR_PR(GDSAH);
  749. LCR_PR(VHPCL);
  750. LCR_PR(VHPCH);
  751. LCR_PR(GM);
  752. LCR_PR(HT);
  753. LCR_PR(HDS);
  754. LCR_PR(HSS);
  755. LCR_PR(HSE);
  756. LCR_PR(HNP);
  757. LCR_PR(VT);
  758. LCR_PR(VDS);
  759. LCR_PR(VSS);
  760. LCR_PR(VSE);
  761. LCR_PR(CDLN);
  762. LCR_PR(ILN);
  763. LCR_PR(SP);
  764. LCR_PR(MISC);
  765. LCR_PR(VIHSS);
  766. LCR_PR(VIVS);
  767. LCR_PR(VIVE);
  768. LCR_PR(VIVSS);
  769. LCR_PR(VCCIS);
  770. LCR_PR(VIDWSAL);
  771. LCR_PR(VIDWSAH);
  772. LCR_PR(VIDRSAL);
  773. LCR_PR(VIDRSAH);
  774. LCR_PR(VIPDDST);
  775. LCR_PR(VIPDDET);
  776. LCR_PR(VIE);
  777. LCR_PR(VCS);
  778. LCR_PR(VPHWC);
  779. LCR_PR(VPHS);
  780. LCR_PR(VPVWC);
  781. LCR_PR(VPVS);
  782. LCR_PR(PLHPIX);
  783. LCR_PR(XS);
  784. LCR_PR(XCKHW);
  785. LCR_PR(STHS);
  786. LCR_PR(VT2);
  787. LCR_PR(YCKSW);
  788. LCR_PR(YSTS);
  789. LCR_PR(PPOLS);
  790. LCR_PR(PRECW);
  791. LCR_PR(VCLKHW);
  792. LCR_PR(OC);
  793. #undef LCR_PR
  794. }
  795. #endif
  796. #ifdef CONFIG_PM
  797. static int tmiofb_suspend(struct platform_device *dev, pm_message_t state)
  798. {
  799. struct fb_info *info = platform_get_drvdata(dev);
  800. #ifdef CONFIG_FB_TMIO_ACCELL
  801. struct tmiofb_par *par = info->par;
  802. #endif
  803. const struct mfd_cell *cell = mfd_get_cell(dev);
  804. int retval = 0;
  805. console_lock();
  806. fb_set_suspend(info, 1);
  807. if (info->fbops->fb_sync)
  808. info->fbops->fb_sync(info);
  809. #ifdef CONFIG_FB_TMIO_ACCELL
  810. /*
  811. * The fb should be usable even if interrupts are disabled (and they are
  812. * during suspend/resume). Switch temporary to forced polling.
  813. */
  814. printk(KERN_INFO "tmiofb: switching to polling\n");
  815. par->use_polling = true;
  816. #endif
  817. tmiofb_hw_stop(dev);
  818. if (cell->suspend)
  819. retval = cell->suspend(dev);
  820. console_unlock();
  821. return retval;
  822. }
  823. static int tmiofb_resume(struct platform_device *dev)
  824. {
  825. struct fb_info *info = platform_get_drvdata(dev);
  826. const struct mfd_cell *cell = mfd_get_cell(dev);
  827. int retval = 0;
  828. console_lock();
  829. if (cell->resume) {
  830. retval = cell->resume(dev);
  831. if (retval)
  832. goto out;
  833. }
  834. tmiofb_irq(-1, info);
  835. tmiofb_hw_init(dev);
  836. tmiofb_hw_mode(dev);
  837. fb_set_suspend(info, 0);
  838. out:
  839. console_unlock();
  840. return retval;
  841. }
  842. #else
  843. #define tmiofb_suspend NULL
  844. #define tmiofb_resume NULL
  845. #endif
  846. static struct platform_driver tmiofb_driver = {
  847. .driver.name = "tmio-fb",
  848. .driver.owner = THIS_MODULE,
  849. .probe = tmiofb_probe,
  850. .remove = tmiofb_remove,
  851. .suspend = tmiofb_suspend,
  852. .resume = tmiofb_resume,
  853. };
  854. /*--------------------------------------------------------------------------*/
  855. #ifndef MODULE
  856. static void __init tmiofb_setup(char *options)
  857. {
  858. char *this_opt;
  859. if (!options || !*options)
  860. return;
  861. while ((this_opt = strsep(&options, ",")) != NULL) {
  862. if (!*this_opt)
  863. continue;
  864. /*
  865. * FIXME
  866. */
  867. }
  868. }
  869. #endif
  870. static int __init tmiofb_init(void)
  871. {
  872. #ifndef MODULE
  873. char *option = NULL;
  874. if (fb_get_options("tmiofb", &option))
  875. return -ENODEV;
  876. tmiofb_setup(option);
  877. #endif
  878. return platform_driver_register(&tmiofb_driver);
  879. }
  880. static void __exit tmiofb_cleanup(void)
  881. {
  882. platform_driver_unregister(&tmiofb_driver);
  883. }
  884. module_init(tmiofb_init);
  885. module_exit(tmiofb_cleanup);
  886. MODULE_DESCRIPTION("TMIO framebuffer driver");
  887. MODULE_AUTHOR("Chris Humbert, Dirk Opfer, Dmitry Baryshkov");
  888. MODULE_LICENSE("GPL");