smscufx.c 53 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * smscufx.c -- Framebuffer driver for SMSC UFX USB controller
  4. *
  5. * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net>
  6. * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
  7. * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
  8. * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
  9. *
  10. * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen,
  11. * and others.
  12. *
  13. * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev
  14. * available from http://git.plugable.com
  15. *
  16. * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven,
  17. * usb-skeleton by GregKH.
  18. */
  19. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/usb.h>
  24. #include <linux/uaccess.h>
  25. #include <linux/mm.h>
  26. #include <linux/fb.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/slab.h>
  29. #include <linux/delay.h>
  30. #include "edid.h"
  31. #define check_warn(status, fmt, args...) \
  32. ({ if (status < 0) pr_warn(fmt, ##args); })
  33. #define check_warn_return(status, fmt, args...) \
  34. ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
  35. #define check_warn_goto_error(status, fmt, args...) \
  36. ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
  37. #define all_bits_set(x, bits) (((x) & (bits)) == (bits))
  38. #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
  39. #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
  40. /*
  41. * TODO: Propose standard fb.h ioctl for reporting damage,
  42. * using _IOWR() and one of the existing area structs from fb.h
  43. * Consider these ioctls deprecated, but they're still used by the
  44. * DisplayLink X server as yet - need both to be modified in tandem
  45. * when new ioctl(s) are ready.
  46. */
  47. #define UFX_IOCTL_RETURN_EDID (0xAD)
  48. #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
  49. /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
  50. #define BULK_SIZE (512)
  51. #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
  52. #define WRITES_IN_FLIGHT (4)
  53. #define GET_URB_TIMEOUT (HZ)
  54. #define FREE_URB_TIMEOUT (HZ*2)
  55. #define BPP 2
  56. #define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */
  57. #define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */
  58. struct dloarea {
  59. int x, y;
  60. int w, h;
  61. };
  62. struct urb_node {
  63. struct list_head entry;
  64. struct ufx_data *dev;
  65. struct delayed_work release_urb_work;
  66. struct urb *urb;
  67. };
  68. struct urb_list {
  69. struct list_head list;
  70. spinlock_t lock;
  71. struct semaphore limit_sem;
  72. int available;
  73. int count;
  74. size_t size;
  75. };
  76. struct ufx_data {
  77. struct usb_device *udev;
  78. struct device *gdev; /* &udev->dev */
  79. struct fb_info *info;
  80. struct urb_list urbs;
  81. struct kref kref;
  82. int fb_count;
  83. bool virtualized; /* true when physical usb device not present */
  84. struct delayed_work free_framebuffer_work;
  85. atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
  86. atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
  87. u8 *edid; /* null until we read edid from hw or get from sysfs */
  88. size_t edid_size;
  89. u32 pseudo_palette[256];
  90. };
  91. static struct fb_fix_screeninfo ufx_fix = {
  92. .id = "smscufx",
  93. .type = FB_TYPE_PACKED_PIXELS,
  94. .visual = FB_VISUAL_TRUECOLOR,
  95. .xpanstep = 0,
  96. .ypanstep = 0,
  97. .ywrapstep = 0,
  98. .accel = FB_ACCEL_NONE,
  99. };
  100. static const u32 smscufx_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST |
  101. FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT |
  102. FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR;
  103. static const struct usb_device_id id_table[] = {
  104. {USB_DEVICE(0x0424, 0x9d00),},
  105. {USB_DEVICE(0x0424, 0x9d01),},
  106. {},
  107. };
  108. MODULE_DEVICE_TABLE(usb, id_table);
  109. /* module options */
  110. static bool console; /* Optionally allow fbcon to consume first framebuffer */
  111. static bool fb_defio = true; /* Optionally enable fb_defio mmap support */
  112. /* ufx keeps a list of urbs for efficient bulk transfers */
  113. static void ufx_urb_completion(struct urb *urb);
  114. static struct urb *ufx_get_urb(struct ufx_data *dev);
  115. static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len);
  116. static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size);
  117. static void ufx_free_urb_list(struct ufx_data *dev);
  118. /* reads a control register */
  119. static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data)
  120. {
  121. u32 *buf = kmalloc(4, GFP_KERNEL);
  122. int ret;
  123. BUG_ON(!dev);
  124. if (!buf)
  125. return -ENOMEM;
  126. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  127. USB_VENDOR_REQUEST_READ_REGISTER,
  128. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  129. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  130. le32_to_cpus(buf);
  131. *data = *buf;
  132. kfree(buf);
  133. if (unlikely(ret < 0))
  134. pr_warn("Failed to read register index 0x%08x\n", index);
  135. return ret;
  136. }
  137. /* writes a control register */
  138. static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data)
  139. {
  140. u32 *buf = kmalloc(4, GFP_KERNEL);
  141. int ret;
  142. BUG_ON(!dev);
  143. if (!buf)
  144. return -ENOMEM;
  145. *buf = data;
  146. cpu_to_le32s(buf);
  147. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  148. USB_VENDOR_REQUEST_WRITE_REGISTER,
  149. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  150. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  151. kfree(buf);
  152. if (unlikely(ret < 0))
  153. pr_warn("Failed to write register index 0x%08x with value "
  154. "0x%08x\n", index, data);
  155. return ret;
  156. }
  157. static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index,
  158. u32 bits_to_clear, u32 bits_to_set)
  159. {
  160. u32 data;
  161. int status = ufx_reg_read(dev, index, &data);
  162. check_warn_return(status, "ufx_reg_clear_and_set_bits error reading "
  163. "0x%x", index);
  164. data &= (~bits_to_clear);
  165. data |= bits_to_set;
  166. status = ufx_reg_write(dev, index, data);
  167. check_warn_return(status, "ufx_reg_clear_and_set_bits error writing "
  168. "0x%x", index);
  169. return 0;
  170. }
  171. static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits)
  172. {
  173. return ufx_reg_clear_and_set_bits(dev, index, 0, bits);
  174. }
  175. static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits)
  176. {
  177. return ufx_reg_clear_and_set_bits(dev, index, bits, 0);
  178. }
  179. static int ufx_lite_reset(struct ufx_data *dev)
  180. {
  181. int status;
  182. u32 value;
  183. status = ufx_reg_write(dev, 0x3008, 0x00000001);
  184. check_warn_return(status, "ufx_lite_reset error writing 0x3008");
  185. status = ufx_reg_read(dev, 0x3008, &value);
  186. check_warn_return(status, "ufx_lite_reset error reading 0x3008");
  187. return (value == 0) ? 0 : -EIO;
  188. }
  189. /* If display is unblanked, then blank it */
  190. static int ufx_blank(struct ufx_data *dev, bool wait)
  191. {
  192. u32 dc_ctrl, dc_sts;
  193. int i;
  194. int status = ufx_reg_read(dev, 0x2004, &dc_sts);
  195. check_warn_return(status, "ufx_blank error reading 0x2004");
  196. status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
  197. check_warn_return(status, "ufx_blank error reading 0x2000");
  198. /* return success if display is already blanked */
  199. if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100))
  200. return 0;
  201. /* request the DC to blank the display */
  202. dc_ctrl |= 0x00000100;
  203. status = ufx_reg_write(dev, 0x2000, dc_ctrl);
  204. check_warn_return(status, "ufx_blank error writing 0x2000");
  205. /* return success immediately if we don't have to wait */
  206. if (!wait)
  207. return 0;
  208. for (i = 0; i < 250; i++) {
  209. status = ufx_reg_read(dev, 0x2004, &dc_sts);
  210. check_warn_return(status, "ufx_blank error reading 0x2004");
  211. if (dc_sts & 0x00000100)
  212. return 0;
  213. }
  214. /* timed out waiting for display to blank */
  215. return -EIO;
  216. }
  217. /* If display is blanked, then unblank it */
  218. static int ufx_unblank(struct ufx_data *dev, bool wait)
  219. {
  220. u32 dc_ctrl, dc_sts;
  221. int i;
  222. int status = ufx_reg_read(dev, 0x2004, &dc_sts);
  223. check_warn_return(status, "ufx_unblank error reading 0x2004");
  224. status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
  225. check_warn_return(status, "ufx_unblank error reading 0x2000");
  226. /* return success if display is already unblanked */
  227. if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0))
  228. return 0;
  229. /* request the DC to unblank the display */
  230. dc_ctrl &= ~0x00000100;
  231. status = ufx_reg_write(dev, 0x2000, dc_ctrl);
  232. check_warn_return(status, "ufx_unblank error writing 0x2000");
  233. /* return success immediately if we don't have to wait */
  234. if (!wait)
  235. return 0;
  236. for (i = 0; i < 250; i++) {
  237. status = ufx_reg_read(dev, 0x2004, &dc_sts);
  238. check_warn_return(status, "ufx_unblank error reading 0x2004");
  239. if ((dc_sts & 0x00000100) == 0)
  240. return 0;
  241. }
  242. /* timed out waiting for display to unblank */
  243. return -EIO;
  244. }
  245. /* If display is enabled, then disable it */
  246. static int ufx_disable(struct ufx_data *dev, bool wait)
  247. {
  248. u32 dc_ctrl, dc_sts;
  249. int i;
  250. int status = ufx_reg_read(dev, 0x2004, &dc_sts);
  251. check_warn_return(status, "ufx_disable error reading 0x2004");
  252. status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
  253. check_warn_return(status, "ufx_disable error reading 0x2000");
  254. /* return success if display is already disabled */
  255. if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0))
  256. return 0;
  257. /* request the DC to disable the display */
  258. dc_ctrl &= ~(0x00000001);
  259. status = ufx_reg_write(dev, 0x2000, dc_ctrl);
  260. check_warn_return(status, "ufx_disable error writing 0x2000");
  261. /* return success immediately if we don't have to wait */
  262. if (!wait)
  263. return 0;
  264. for (i = 0; i < 250; i++) {
  265. status = ufx_reg_read(dev, 0x2004, &dc_sts);
  266. check_warn_return(status, "ufx_disable error reading 0x2004");
  267. if ((dc_sts & 0x00000001) == 0)
  268. return 0;
  269. }
  270. /* timed out waiting for display to disable */
  271. return -EIO;
  272. }
  273. /* If display is disabled, then enable it */
  274. static int ufx_enable(struct ufx_data *dev, bool wait)
  275. {
  276. u32 dc_ctrl, dc_sts;
  277. int i;
  278. int status = ufx_reg_read(dev, 0x2004, &dc_sts);
  279. check_warn_return(status, "ufx_enable error reading 0x2004");
  280. status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
  281. check_warn_return(status, "ufx_enable error reading 0x2000");
  282. /* return success if display is already enabled */
  283. if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001))
  284. return 0;
  285. /* request the DC to enable the display */
  286. dc_ctrl |= 0x00000001;
  287. status = ufx_reg_write(dev, 0x2000, dc_ctrl);
  288. check_warn_return(status, "ufx_enable error writing 0x2000");
  289. /* return success immediately if we don't have to wait */
  290. if (!wait)
  291. return 0;
  292. for (i = 0; i < 250; i++) {
  293. status = ufx_reg_read(dev, 0x2004, &dc_sts);
  294. check_warn_return(status, "ufx_enable error reading 0x2004");
  295. if (dc_sts & 0x00000001)
  296. return 0;
  297. }
  298. /* timed out waiting for display to enable */
  299. return -EIO;
  300. }
  301. static int ufx_config_sys_clk(struct ufx_data *dev)
  302. {
  303. int status = ufx_reg_write(dev, 0x700C, 0x8000000F);
  304. check_warn_return(status, "error writing 0x700C");
  305. status = ufx_reg_write(dev, 0x7014, 0x0010024F);
  306. check_warn_return(status, "error writing 0x7014");
  307. status = ufx_reg_write(dev, 0x7010, 0x00000000);
  308. check_warn_return(status, "error writing 0x7010");
  309. status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A);
  310. check_warn_return(status, "error clearing PLL1 bypass in 0x700C");
  311. msleep(1);
  312. status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000);
  313. check_warn_return(status, "error clearing output gate in 0x700C");
  314. return 0;
  315. }
  316. static int ufx_config_ddr2(struct ufx_data *dev)
  317. {
  318. int status, i = 0;
  319. u32 tmp;
  320. status = ufx_reg_write(dev, 0x0004, 0x001F0F77);
  321. check_warn_return(status, "error writing 0x0004");
  322. status = ufx_reg_write(dev, 0x0008, 0xFFF00000);
  323. check_warn_return(status, "error writing 0x0008");
  324. status = ufx_reg_write(dev, 0x000C, 0x0FFF2222);
  325. check_warn_return(status, "error writing 0x000C");
  326. status = ufx_reg_write(dev, 0x0010, 0x00030814);
  327. check_warn_return(status, "error writing 0x0010");
  328. status = ufx_reg_write(dev, 0x0014, 0x00500019);
  329. check_warn_return(status, "error writing 0x0014");
  330. status = ufx_reg_write(dev, 0x0018, 0x020D0F15);
  331. check_warn_return(status, "error writing 0x0018");
  332. status = ufx_reg_write(dev, 0x001C, 0x02532305);
  333. check_warn_return(status, "error writing 0x001C");
  334. status = ufx_reg_write(dev, 0x0020, 0x0B030905);
  335. check_warn_return(status, "error writing 0x0020");
  336. status = ufx_reg_write(dev, 0x0024, 0x00000827);
  337. check_warn_return(status, "error writing 0x0024");
  338. status = ufx_reg_write(dev, 0x0028, 0x00000000);
  339. check_warn_return(status, "error writing 0x0028");
  340. status = ufx_reg_write(dev, 0x002C, 0x00000042);
  341. check_warn_return(status, "error writing 0x002C");
  342. status = ufx_reg_write(dev, 0x0030, 0x09520000);
  343. check_warn_return(status, "error writing 0x0030");
  344. status = ufx_reg_write(dev, 0x0034, 0x02223314);
  345. check_warn_return(status, "error writing 0x0034");
  346. status = ufx_reg_write(dev, 0x0038, 0x00430043);
  347. check_warn_return(status, "error writing 0x0038");
  348. status = ufx_reg_write(dev, 0x003C, 0xF00F000F);
  349. check_warn_return(status, "error writing 0x003C");
  350. status = ufx_reg_write(dev, 0x0040, 0xF380F00F);
  351. check_warn_return(status, "error writing 0x0040");
  352. status = ufx_reg_write(dev, 0x0044, 0xF00F0496);
  353. check_warn_return(status, "error writing 0x0044");
  354. status = ufx_reg_write(dev, 0x0048, 0x03080406);
  355. check_warn_return(status, "error writing 0x0048");
  356. status = ufx_reg_write(dev, 0x004C, 0x00001000);
  357. check_warn_return(status, "error writing 0x004C");
  358. status = ufx_reg_write(dev, 0x005C, 0x00000007);
  359. check_warn_return(status, "error writing 0x005C");
  360. status = ufx_reg_write(dev, 0x0100, 0x54F00012);
  361. check_warn_return(status, "error writing 0x0100");
  362. status = ufx_reg_write(dev, 0x0104, 0x00004012);
  363. check_warn_return(status, "error writing 0x0104");
  364. status = ufx_reg_write(dev, 0x0118, 0x40404040);
  365. check_warn_return(status, "error writing 0x0118");
  366. status = ufx_reg_write(dev, 0x0000, 0x00000001);
  367. check_warn_return(status, "error writing 0x0000");
  368. while (i++ < 500) {
  369. status = ufx_reg_read(dev, 0x0000, &tmp);
  370. check_warn_return(status, "error reading 0x0000");
  371. if (all_bits_set(tmp, 0xC0000000))
  372. return 0;
  373. }
  374. pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp);
  375. return -ETIMEDOUT;
  376. }
  377. struct pll_values {
  378. u32 div_r0;
  379. u32 div_f0;
  380. u32 div_q0;
  381. u32 range0;
  382. u32 div_r1;
  383. u32 div_f1;
  384. u32 div_q1;
  385. u32 range1;
  386. };
  387. static u32 ufx_calc_range(u32 ref_freq)
  388. {
  389. if (ref_freq >= 88000000)
  390. return 7;
  391. if (ref_freq >= 54000000)
  392. return 6;
  393. if (ref_freq >= 34000000)
  394. return 5;
  395. if (ref_freq >= 21000000)
  396. return 4;
  397. if (ref_freq >= 13000000)
  398. return 3;
  399. if (ref_freq >= 8000000)
  400. return 2;
  401. return 1;
  402. }
  403. /* calculates PLL divider settings for a desired target frequency */
  404. static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll)
  405. {
  406. const u32 ref_clk = 25000000;
  407. u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1;
  408. u32 min_error = clk_pixel_pll;
  409. for (div_r0 = 1; div_r0 <= 32; div_r0++) {
  410. u32 ref_freq0 = ref_clk / div_r0;
  411. if (ref_freq0 < 5000000)
  412. break;
  413. if (ref_freq0 > 200000000)
  414. continue;
  415. for (div_f0 = 1; div_f0 <= 256; div_f0++) {
  416. u32 vco_freq0 = ref_freq0 * div_f0;
  417. if (vco_freq0 < 350000000)
  418. continue;
  419. if (vco_freq0 > 700000000)
  420. break;
  421. for (div_q0 = 0; div_q0 < 7; div_q0++) {
  422. u32 pllout_freq0 = vco_freq0 / (1 << div_q0);
  423. if (pllout_freq0 < 5000000)
  424. break;
  425. if (pllout_freq0 > 200000000)
  426. continue;
  427. for (div_r1 = 1; div_r1 <= 32; div_r1++) {
  428. u32 ref_freq1 = pllout_freq0 / div_r1;
  429. if (ref_freq1 < 5000000)
  430. break;
  431. for (div_f1 = 1; div_f1 <= 256; div_f1++) {
  432. u32 vco_freq1 = ref_freq1 * div_f1;
  433. if (vco_freq1 < 350000000)
  434. continue;
  435. if (vco_freq1 > 700000000)
  436. break;
  437. for (div_q1 = 0; div_q1 < 7; div_q1++) {
  438. u32 pllout_freq1 = vco_freq1 / (1 << div_q1);
  439. int error = abs(pllout_freq1 - clk_pixel_pll);
  440. if (pllout_freq1 < 5000000)
  441. break;
  442. if (pllout_freq1 > 700000000)
  443. continue;
  444. if (error < min_error) {
  445. min_error = error;
  446. /* final returned value is equal to calculated value - 1
  447. * because a value of 0 = divide by 1 */
  448. asic_pll->div_r0 = div_r0 - 1;
  449. asic_pll->div_f0 = div_f0 - 1;
  450. asic_pll->div_q0 = div_q0;
  451. asic_pll->div_r1 = div_r1 - 1;
  452. asic_pll->div_f1 = div_f1 - 1;
  453. asic_pll->div_q1 = div_q1;
  454. asic_pll->range0 = ufx_calc_range(ref_freq0);
  455. asic_pll->range1 = ufx_calc_range(ref_freq1);
  456. if (min_error == 0)
  457. return;
  458. }
  459. }
  460. }
  461. }
  462. }
  463. }
  464. }
  465. }
  466. /* sets analog bit PLL configuration values */
  467. static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock)
  468. {
  469. struct pll_values asic_pll = {0};
  470. u32 value, clk_pixel, clk_pixel_pll;
  471. int status;
  472. /* convert pixclock (in ps) to frequency (in Hz) */
  473. clk_pixel = PICOS2KHZ(pixclock) * 1000;
  474. pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel);
  475. /* clk_pixel = 1/2 clk_pixel_pll */
  476. clk_pixel_pll = clk_pixel * 2;
  477. ufx_calc_pll_values(clk_pixel_pll, &asic_pll);
  478. /* Keep BYPASS and RESET signals asserted until configured */
  479. status = ufx_reg_write(dev, 0x7000, 0x8000000F);
  480. check_warn_return(status, "error writing 0x7000");
  481. value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) |
  482. (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20));
  483. status = ufx_reg_write(dev, 0x7008, value);
  484. check_warn_return(status, "error writing 0x7008");
  485. value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) |
  486. (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20));
  487. status = ufx_reg_write(dev, 0x7004, value);
  488. check_warn_return(status, "error writing 0x7004");
  489. status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005);
  490. check_warn_return(status,
  491. "error clearing PLL0 bypass bits in 0x7000");
  492. msleep(1);
  493. status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A);
  494. check_warn_return(status,
  495. "error clearing PLL1 bypass bits in 0x7000");
  496. msleep(1);
  497. status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000);
  498. check_warn_return(status, "error clearing gate bits in 0x7000");
  499. return 0;
  500. }
  501. static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var)
  502. {
  503. u32 temp;
  504. u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end;
  505. u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end;
  506. int status = ufx_reg_write(dev, 0x8028, 0);
  507. check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad");
  508. status = ufx_reg_write(dev, 0x8024, 0);
  509. check_warn_return(status, "ufx_set_vid_mode error disabling VDAC");
  510. /* shut everything down before changing timing */
  511. status = ufx_blank(dev, true);
  512. check_warn_return(status, "ufx_set_vid_mode error blanking display");
  513. status = ufx_disable(dev, true);
  514. check_warn_return(status, "ufx_set_vid_mode error disabling display");
  515. status = ufx_config_pix_clk(dev, var->pixclock);
  516. check_warn_return(status, "ufx_set_vid_mode error configuring pixclock");
  517. status = ufx_reg_write(dev, 0x2000, 0x00000104);
  518. check_warn_return(status, "ufx_set_vid_mode error writing 0x2000");
  519. /* set horizontal timings */
  520. h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
  521. h_active = var->xres;
  522. h_blank_start = var->xres + var->right_margin;
  523. h_blank_end = var->xres + var->right_margin + var->hsync_len;
  524. h_sync_start = var->xres + var->right_margin;
  525. h_sync_end = var->xres + var->right_margin + var->hsync_len;
  526. temp = ((h_total - 1) << 16) | (h_active - 1);
  527. status = ufx_reg_write(dev, 0x2008, temp);
  528. check_warn_return(status, "ufx_set_vid_mode error writing 0x2008");
  529. temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1);
  530. status = ufx_reg_write(dev, 0x200C, temp);
  531. check_warn_return(status, "ufx_set_vid_mode error writing 0x200C");
  532. temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1);
  533. status = ufx_reg_write(dev, 0x2010, temp);
  534. check_warn_return(status, "ufx_set_vid_mode error writing 0x2010");
  535. /* set vertical timings */
  536. v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;
  537. v_active = var->yres;
  538. v_blank_start = var->yres + var->lower_margin;
  539. v_blank_end = var->yres + var->lower_margin + var->vsync_len;
  540. v_sync_start = var->yres + var->lower_margin;
  541. v_sync_end = var->yres + var->lower_margin + var->vsync_len;
  542. temp = ((v_total - 1) << 16) | (v_active - 1);
  543. status = ufx_reg_write(dev, 0x2014, temp);
  544. check_warn_return(status, "ufx_set_vid_mode error writing 0x2014");
  545. temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1);
  546. status = ufx_reg_write(dev, 0x2018, temp);
  547. check_warn_return(status, "ufx_set_vid_mode error writing 0x2018");
  548. temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1);
  549. status = ufx_reg_write(dev, 0x201C, temp);
  550. check_warn_return(status, "ufx_set_vid_mode error writing 0x201C");
  551. status = ufx_reg_write(dev, 0x2020, 0x00000000);
  552. check_warn_return(status, "ufx_set_vid_mode error writing 0x2020");
  553. status = ufx_reg_write(dev, 0x2024, 0x00000000);
  554. check_warn_return(status, "ufx_set_vid_mode error writing 0x2024");
  555. /* Set the frame length register (#pix * 2 bytes/pixel) */
  556. temp = var->xres * var->yres * 2;
  557. temp = (temp + 7) & (~0x7);
  558. status = ufx_reg_write(dev, 0x2028, temp);
  559. check_warn_return(status, "ufx_set_vid_mode error writing 0x2028");
  560. /* enable desired output interface & disable others */
  561. status = ufx_reg_write(dev, 0x2040, 0);
  562. check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
  563. status = ufx_reg_write(dev, 0x2044, 0);
  564. check_warn_return(status, "ufx_set_vid_mode error writing 0x2044");
  565. status = ufx_reg_write(dev, 0x2048, 0);
  566. check_warn_return(status, "ufx_set_vid_mode error writing 0x2048");
  567. /* set the sync polarities & enable bit */
  568. temp = 0x00000001;
  569. if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  570. temp |= 0x00000010;
  571. if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  572. temp |= 0x00000008;
  573. status = ufx_reg_write(dev, 0x2040, temp);
  574. check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
  575. /* start everything back up */
  576. status = ufx_enable(dev, true);
  577. check_warn_return(status, "ufx_set_vid_mode error enabling display");
  578. /* Unblank the display */
  579. status = ufx_unblank(dev, true);
  580. check_warn_return(status, "ufx_set_vid_mode error unblanking display");
  581. /* enable RGB pad */
  582. status = ufx_reg_write(dev, 0x8028, 0x00000003);
  583. check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad");
  584. /* enable VDAC */
  585. status = ufx_reg_write(dev, 0x8024, 0x00000007);
  586. check_warn_return(status, "ufx_set_vid_mode error enabling VDAC");
  587. return 0;
  588. }
  589. static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma)
  590. {
  591. unsigned long start = vma->vm_start;
  592. unsigned long size = vma->vm_end - vma->vm_start;
  593. unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
  594. unsigned long page, pos;
  595. if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
  596. return -EINVAL;
  597. if (size > info->fix.smem_len)
  598. return -EINVAL;
  599. if (offset > info->fix.smem_len - size)
  600. return -EINVAL;
  601. pos = (unsigned long)info->fix.smem_start + offset;
  602. pr_debug("mmap() framebuffer addr:%lu size:%lu\n",
  603. pos, size);
  604. while (size > 0) {
  605. page = vmalloc_to_pfn((void *)pos);
  606. if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
  607. return -EAGAIN;
  608. start += PAGE_SIZE;
  609. pos += PAGE_SIZE;
  610. if (size > PAGE_SIZE)
  611. size -= PAGE_SIZE;
  612. else
  613. size = 0;
  614. }
  615. return 0;
  616. }
  617. static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y,
  618. int width, int height)
  619. {
  620. size_t packed_line_len = ALIGN((width * 2), 4);
  621. size_t packed_rect_len = packed_line_len * height;
  622. int line;
  623. BUG_ON(!dev);
  624. BUG_ON(!dev->info);
  625. /* command word */
  626. *((u32 *)&cmd[0]) = cpu_to_le32(0x01);
  627. /* length word */
  628. *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16);
  629. cmd[4] = cpu_to_le16(x);
  630. cmd[5] = cpu_to_le16(y);
  631. cmd[6] = cpu_to_le16(width);
  632. cmd[7] = cpu_to_le16(height);
  633. /* frame base address */
  634. *((u32 *)&cmd[8]) = cpu_to_le32(0);
  635. /* color mode and horizontal resolution */
  636. cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres);
  637. /* vertical resolution */
  638. cmd[11] = cpu_to_le16(dev->info->var.yres);
  639. /* packed data */
  640. for (line = 0; line < height; line++) {
  641. const int line_offset = dev->info->fix.line_length * (y + line);
  642. const int byte_offset = line_offset + (x * BPP);
  643. memcpy(&cmd[(24 + (packed_line_len * line)) / 2],
  644. (char *)dev->info->fix.smem_start + byte_offset, width * BPP);
  645. }
  646. }
  647. static int ufx_handle_damage(struct ufx_data *dev, int x, int y,
  648. int width, int height)
  649. {
  650. size_t packed_line_len = ALIGN((width * 2), 4);
  651. int len, status, urb_lines, start_line = 0;
  652. if ((width <= 0) || (height <= 0) ||
  653. (x + width > dev->info->var.xres) ||
  654. (y + height > dev->info->var.yres))
  655. return -EINVAL;
  656. if (!atomic_read(&dev->usb_active))
  657. return 0;
  658. while (start_line < height) {
  659. struct urb *urb = ufx_get_urb(dev);
  660. if (!urb) {
  661. pr_warn("ufx_handle_damage unable to get urb");
  662. return 0;
  663. }
  664. /* assume we have enough space to transfer at least one line */
  665. BUG_ON(urb->transfer_buffer_length < (24 + (width * 2)));
  666. /* calculate the maximum number of lines we could fit in */
  667. urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len;
  668. /* but we might not need this many */
  669. urb_lines = min(urb_lines, (height - start_line));
  670. memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
  671. ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines);
  672. len = 24 + (packed_line_len * urb_lines);
  673. status = ufx_submit_urb(dev, urb, len);
  674. check_warn_return(status, "Error submitting URB");
  675. start_line += urb_lines;
  676. }
  677. return 0;
  678. }
  679. /* Path triggered by usermode clients who write to filesystem
  680. * e.g. cat filename > /dev/fb1
  681. * Not used by X Windows or text-mode console. But useful for testing.
  682. * Slow because of extra copy and we must assume all pixels dirty. */
  683. static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf,
  684. size_t count, loff_t *ppos)
  685. {
  686. ssize_t result;
  687. struct ufx_data *dev = info->par;
  688. u32 offset = (u32) *ppos;
  689. result = fb_sys_write(info, buf, count, ppos);
  690. if (result > 0) {
  691. int start = max((int)(offset / info->fix.line_length), 0);
  692. int lines = min((u32)((result / info->fix.line_length) + 1),
  693. (u32)info->var.yres);
  694. ufx_handle_damage(dev, 0, start, info->var.xres, lines);
  695. }
  696. return result;
  697. }
  698. static void ufx_ops_copyarea(struct fb_info *info,
  699. const struct fb_copyarea *area)
  700. {
  701. struct ufx_data *dev = info->par;
  702. sys_copyarea(info, area);
  703. ufx_handle_damage(dev, area->dx, area->dy,
  704. area->width, area->height);
  705. }
  706. static void ufx_ops_imageblit(struct fb_info *info,
  707. const struct fb_image *image)
  708. {
  709. struct ufx_data *dev = info->par;
  710. sys_imageblit(info, image);
  711. ufx_handle_damage(dev, image->dx, image->dy,
  712. image->width, image->height);
  713. }
  714. static void ufx_ops_fillrect(struct fb_info *info,
  715. const struct fb_fillrect *rect)
  716. {
  717. struct ufx_data *dev = info->par;
  718. sys_fillrect(info, rect);
  719. ufx_handle_damage(dev, rect->dx, rect->dy, rect->width,
  720. rect->height);
  721. }
  722. /* NOTE: fb_defio.c is holding info->fbdefio.mutex
  723. * Touching ANY framebuffer memory that triggers a page fault
  724. * in fb_defio will cause a deadlock, when it also tries to
  725. * grab the same mutex. */
  726. static void ufx_dpy_deferred_io(struct fb_info *info,
  727. struct list_head *pagelist)
  728. {
  729. struct page *cur;
  730. struct fb_deferred_io *fbdefio = info->fbdefio;
  731. struct ufx_data *dev = info->par;
  732. if (!fb_defio)
  733. return;
  734. if (!atomic_read(&dev->usb_active))
  735. return;
  736. /* walk the written page list and render each to device */
  737. list_for_each_entry(cur, &fbdefio->pagelist, lru) {
  738. /* create a rectangle of full screen width that encloses the
  739. * entire dirty framebuffer page */
  740. const int x = 0;
  741. const int width = dev->info->var.xres;
  742. const int y = (cur->index << PAGE_SHIFT) / (width * 2);
  743. int height = (PAGE_SIZE / (width * 2)) + 1;
  744. height = min(height, (int)(dev->info->var.yres - y));
  745. BUG_ON(y >= dev->info->var.yres);
  746. BUG_ON((y + height) > dev->info->var.yres);
  747. ufx_handle_damage(dev, x, y, width, height);
  748. }
  749. }
  750. static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd,
  751. unsigned long arg)
  752. {
  753. struct ufx_data *dev = info->par;
  754. struct dloarea *area = NULL;
  755. if (!atomic_read(&dev->usb_active))
  756. return 0;
  757. /* TODO: Update X server to get this from sysfs instead */
  758. if (cmd == UFX_IOCTL_RETURN_EDID) {
  759. u8 __user *edid = (u8 __user *)arg;
  760. if (copy_to_user(edid, dev->edid, dev->edid_size))
  761. return -EFAULT;
  762. return 0;
  763. }
  764. /* TODO: Help propose a standard fb.h ioctl to report mmap damage */
  765. if (cmd == UFX_IOCTL_REPORT_DAMAGE) {
  766. /* If we have a damage-aware client, turn fb_defio "off"
  767. * To avoid perf imact of unnecessary page fault handling.
  768. * Done by resetting the delay for this fb_info to a very
  769. * long period. Pages will become writable and stay that way.
  770. * Reset to normal value when all clients have closed this fb.
  771. */
  772. if (info->fbdefio)
  773. info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE;
  774. area = (struct dloarea *)arg;
  775. if (area->x < 0)
  776. area->x = 0;
  777. if (area->x > info->var.xres)
  778. area->x = info->var.xres;
  779. if (area->y < 0)
  780. area->y = 0;
  781. if (area->y > info->var.yres)
  782. area->y = info->var.yres;
  783. ufx_handle_damage(dev, area->x, area->y, area->w, area->h);
  784. }
  785. return 0;
  786. }
  787. /* taken from vesafb */
  788. static int
  789. ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green,
  790. unsigned blue, unsigned transp, struct fb_info *info)
  791. {
  792. int err = 0;
  793. if (regno >= info->cmap.len)
  794. return 1;
  795. if (regno < 16) {
  796. if (info->var.red.offset == 10) {
  797. /* 1:5:5:5 */
  798. ((u32 *) (info->pseudo_palette))[regno] =
  799. ((red & 0xf800) >> 1) |
  800. ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
  801. } else {
  802. /* 0:5:6:5 */
  803. ((u32 *) (info->pseudo_palette))[regno] =
  804. ((red & 0xf800)) |
  805. ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
  806. }
  807. }
  808. return err;
  809. }
  810. /* It's common for several clients to have framebuffer open simultaneously.
  811. * e.g. both fbcon and X. Makes things interesting.
  812. * Assumes caller is holding info->lock (for open and release at least) */
  813. static int ufx_ops_open(struct fb_info *info, int user)
  814. {
  815. struct ufx_data *dev = info->par;
  816. /* fbcon aggressively connects to first framebuffer it finds,
  817. * preventing other clients (X) from working properly. Usually
  818. * not what the user wants. Fail by default with option to enable. */
  819. if (user == 0 && !console)
  820. return -EBUSY;
  821. /* If the USB device is gone, we don't accept new opens */
  822. if (dev->virtualized)
  823. return -ENODEV;
  824. dev->fb_count++;
  825. kref_get(&dev->kref);
  826. if (fb_defio && (info->fbdefio == NULL)) {
  827. /* enable defio at last moment if not disabled by client */
  828. struct fb_deferred_io *fbdefio;
  829. fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL);
  830. if (fbdefio) {
  831. fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
  832. fbdefio->deferred_io = ufx_dpy_deferred_io;
  833. }
  834. info->fbdefio = fbdefio;
  835. fb_deferred_io_init(info);
  836. }
  837. pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d",
  838. info->node, user, info, dev->fb_count);
  839. return 0;
  840. }
  841. /*
  842. * Called when all client interfaces to start transactions have been disabled,
  843. * and all references to our device instance (ufx_data) are released.
  844. * Every transaction must have a reference, so we know are fully spun down
  845. */
  846. static void ufx_free(struct kref *kref)
  847. {
  848. struct ufx_data *dev = container_of(kref, struct ufx_data, kref);
  849. /* this function will wait for all in-flight urbs to complete */
  850. if (dev->urbs.count > 0)
  851. ufx_free_urb_list(dev);
  852. pr_debug("freeing ufx_data %p", dev);
  853. kfree(dev);
  854. }
  855. static void ufx_release_urb_work(struct work_struct *work)
  856. {
  857. struct urb_node *unode = container_of(work, struct urb_node,
  858. release_urb_work.work);
  859. up(&unode->dev->urbs.limit_sem);
  860. }
  861. static void ufx_free_framebuffer_work(struct work_struct *work)
  862. {
  863. struct ufx_data *dev = container_of(work, struct ufx_data,
  864. free_framebuffer_work.work);
  865. struct fb_info *info = dev->info;
  866. int node = info->node;
  867. unregister_framebuffer(info);
  868. if (info->cmap.len != 0)
  869. fb_dealloc_cmap(&info->cmap);
  870. if (info->monspecs.modedb)
  871. fb_destroy_modedb(info->monspecs.modedb);
  872. vfree(info->screen_base);
  873. fb_destroy_modelist(&info->modelist);
  874. dev->info = NULL;
  875. /* Assume info structure is freed after this point */
  876. framebuffer_release(info);
  877. pr_debug("fb_info for /dev/fb%d has been freed", node);
  878. /* ref taken in probe() as part of registering framebfufer */
  879. kref_put(&dev->kref, ufx_free);
  880. }
  881. /*
  882. * Assumes caller is holding info->lock mutex (for open and release at least)
  883. */
  884. static int ufx_ops_release(struct fb_info *info, int user)
  885. {
  886. struct ufx_data *dev = info->par;
  887. dev->fb_count--;
  888. /* We can't free fb_info here - fbmem will touch it when we return */
  889. if (dev->virtualized && (dev->fb_count == 0))
  890. schedule_delayed_work(&dev->free_framebuffer_work, HZ);
  891. if ((dev->fb_count == 0) && (info->fbdefio)) {
  892. fb_deferred_io_cleanup(info);
  893. kfree(info->fbdefio);
  894. info->fbdefio = NULL;
  895. }
  896. pr_debug("released /dev/fb%d user=%d count=%d",
  897. info->node, user, dev->fb_count);
  898. kref_put(&dev->kref, ufx_free);
  899. return 0;
  900. }
  901. /* Check whether a video mode is supported by the chip
  902. * We start from monitor's modes, so don't need to filter that here */
  903. static int ufx_is_valid_mode(struct fb_videomode *mode,
  904. struct fb_info *info)
  905. {
  906. if ((mode->xres * mode->yres) > (2048 * 1152)) {
  907. pr_debug("%dx%d too many pixels",
  908. mode->xres, mode->yres);
  909. return 0;
  910. }
  911. if (mode->pixclock < 5000) {
  912. pr_debug("%dx%d %dps pixel clock too fast",
  913. mode->xres, mode->yres, mode->pixclock);
  914. return 0;
  915. }
  916. pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres,
  917. mode->pixclock, (1000000 / mode->pixclock));
  918. return 1;
  919. }
  920. static void ufx_var_color_format(struct fb_var_screeninfo *var)
  921. {
  922. const struct fb_bitfield red = { 11, 5, 0 };
  923. const struct fb_bitfield green = { 5, 6, 0 };
  924. const struct fb_bitfield blue = { 0, 5, 0 };
  925. var->bits_per_pixel = 16;
  926. var->red = red;
  927. var->green = green;
  928. var->blue = blue;
  929. }
  930. static int ufx_ops_check_var(struct fb_var_screeninfo *var,
  931. struct fb_info *info)
  932. {
  933. struct fb_videomode mode;
  934. /* TODO: support dynamically changing framebuffer size */
  935. if ((var->xres * var->yres * 2) > info->fix.smem_len)
  936. return -EINVAL;
  937. /* set device-specific elements of var unrelated to mode */
  938. ufx_var_color_format(var);
  939. fb_var_to_videomode(&mode, var);
  940. if (!ufx_is_valid_mode(&mode, info))
  941. return -EINVAL;
  942. return 0;
  943. }
  944. static int ufx_ops_set_par(struct fb_info *info)
  945. {
  946. struct ufx_data *dev = info->par;
  947. int result;
  948. u16 *pix_framebuffer;
  949. int i;
  950. pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres);
  951. result = ufx_set_vid_mode(dev, &info->var);
  952. if ((result == 0) && (dev->fb_count == 0)) {
  953. /* paint greenscreen */
  954. pix_framebuffer = (u16 *) info->screen_base;
  955. for (i = 0; i < info->fix.smem_len / 2; i++)
  956. pix_framebuffer[i] = 0x37e6;
  957. ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres);
  958. }
  959. /* re-enable defio if previously disabled by damage tracking */
  960. if (info->fbdefio)
  961. info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
  962. return result;
  963. }
  964. /* In order to come back from full DPMS off, we need to set the mode again */
  965. static int ufx_ops_blank(int blank_mode, struct fb_info *info)
  966. {
  967. struct ufx_data *dev = info->par;
  968. ufx_set_vid_mode(dev, &info->var);
  969. return 0;
  970. }
  971. static const struct fb_ops ufx_ops = {
  972. .owner = THIS_MODULE,
  973. .fb_read = fb_sys_read,
  974. .fb_write = ufx_ops_write,
  975. .fb_setcolreg = ufx_ops_setcolreg,
  976. .fb_fillrect = ufx_ops_fillrect,
  977. .fb_copyarea = ufx_ops_copyarea,
  978. .fb_imageblit = ufx_ops_imageblit,
  979. .fb_mmap = ufx_ops_mmap,
  980. .fb_ioctl = ufx_ops_ioctl,
  981. .fb_open = ufx_ops_open,
  982. .fb_release = ufx_ops_release,
  983. .fb_blank = ufx_ops_blank,
  984. .fb_check_var = ufx_ops_check_var,
  985. .fb_set_par = ufx_ops_set_par,
  986. };
  987. /* Assumes &info->lock held by caller
  988. * Assumes no active clients have framebuffer open */
  989. static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info)
  990. {
  991. int old_len = info->fix.smem_len;
  992. int new_len;
  993. unsigned char *old_fb = info->screen_base;
  994. unsigned char *new_fb;
  995. pr_debug("Reallocating framebuffer. Addresses will change!");
  996. new_len = info->fix.line_length * info->var.yres;
  997. if (PAGE_ALIGN(new_len) > old_len) {
  998. /*
  999. * Alloc system memory for virtual framebuffer
  1000. */
  1001. new_fb = vmalloc(new_len);
  1002. if (!new_fb)
  1003. return -ENOMEM;
  1004. if (info->screen_base) {
  1005. memcpy(new_fb, old_fb, old_len);
  1006. vfree(info->screen_base);
  1007. }
  1008. info->screen_base = new_fb;
  1009. info->fix.smem_len = PAGE_ALIGN(new_len);
  1010. info->fix.smem_start = (unsigned long) new_fb;
  1011. info->flags = smscufx_info_flags;
  1012. }
  1013. return 0;
  1014. }
  1015. /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master,
  1016. * restart enabled, but no start byte, enable controller */
  1017. static int ufx_i2c_init(struct ufx_data *dev)
  1018. {
  1019. u32 tmp;
  1020. /* disable the controller before it can be reprogrammed */
  1021. int status = ufx_reg_write(dev, 0x106C, 0x00);
  1022. check_warn_return(status, "failed to disable I2C");
  1023. /* Setup the clock count registers
  1024. * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */
  1025. status = ufx_reg_write(dev, 0x1018, 12);
  1026. check_warn_return(status, "error writing 0x1018");
  1027. /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */
  1028. status = ufx_reg_write(dev, 0x1014, 6);
  1029. check_warn_return(status, "error writing 0x1014");
  1030. status = ufx_reg_read(dev, 0x1000, &tmp);
  1031. check_warn_return(status, "error reading 0x1000");
  1032. /* set speed to std mode */
  1033. tmp &= ~(0x06);
  1034. tmp |= 0x02;
  1035. /* 7-bit (not 10-bit) addressing */
  1036. tmp &= ~(0x10);
  1037. /* enable restart conditions and master mode */
  1038. tmp |= 0x21;
  1039. status = ufx_reg_write(dev, 0x1000, tmp);
  1040. check_warn_return(status, "error writing 0x1000");
  1041. /* Set normal tx using target address 0 */
  1042. status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000);
  1043. check_warn_return(status, "error setting TX mode bits in 0x1004");
  1044. /* Enable the controller */
  1045. status = ufx_reg_write(dev, 0x106C, 0x01);
  1046. check_warn_return(status, "failed to enable I2C");
  1047. return 0;
  1048. }
  1049. /* sets the I2C port mux and target address */
  1050. static int ufx_i2c_configure(struct ufx_data *dev)
  1051. {
  1052. int status = ufx_reg_write(dev, 0x106C, 0x00);
  1053. check_warn_return(status, "failed to disable I2C");
  1054. status = ufx_reg_write(dev, 0x3010, 0x00000000);
  1055. check_warn_return(status, "failed to write 0x3010");
  1056. /* A0h is std for any EDID, right shifted by one */
  1057. status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1));
  1058. check_warn_return(status, "failed to set TAR bits in 0x1004");
  1059. status = ufx_reg_write(dev, 0x106C, 0x01);
  1060. check_warn_return(status, "failed to enable I2C");
  1061. return 0;
  1062. }
  1063. /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no
  1064. * monitor is connected, there is no error except for timeout */
  1065. static int ufx_i2c_wait_busy(struct ufx_data *dev)
  1066. {
  1067. u32 tmp;
  1068. int i, status;
  1069. for (i = 0; i < 15; i++) {
  1070. status = ufx_reg_read(dev, 0x1100, &tmp);
  1071. check_warn_return(status, "0x1100 read failed");
  1072. /* if BUSY is clear, check for error */
  1073. if ((tmp & 0x80000000) == 0) {
  1074. if (tmp & 0x20000000) {
  1075. pr_warn("I2C read failed, 0x1100=0x%08x", tmp);
  1076. return -EIO;
  1077. }
  1078. return 0;
  1079. }
  1080. /* perform the first 10 retries without delay */
  1081. if (i >= 10)
  1082. msleep(10);
  1083. }
  1084. pr_warn("I2C access timed out, resetting I2C hardware");
  1085. status = ufx_reg_write(dev, 0x1100, 0x40000000);
  1086. check_warn_return(status, "0x1100 write failed");
  1087. return -ETIMEDOUT;
  1088. }
  1089. /* reads a 128-byte EDID block from the currently selected port and TAR */
  1090. static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len)
  1091. {
  1092. int i, j, status;
  1093. u32 *edid_u32 = (u32 *)edid;
  1094. BUG_ON(edid_len != EDID_LENGTH);
  1095. status = ufx_i2c_configure(dev);
  1096. if (status < 0) {
  1097. pr_err("ufx_i2c_configure failed");
  1098. return status;
  1099. }
  1100. memset(edid, 0xff, EDID_LENGTH);
  1101. /* Read the 128-byte EDID as 2 bursts of 64 bytes */
  1102. for (i = 0; i < 2; i++) {
  1103. u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8);
  1104. status = ufx_reg_write(dev, 0x1100, temp);
  1105. check_warn_return(status, "Failed to write 0x1100");
  1106. temp |= 0x80000000;
  1107. status = ufx_reg_write(dev, 0x1100, temp);
  1108. check_warn_return(status, "Failed to write 0x1100");
  1109. status = ufx_i2c_wait_busy(dev);
  1110. check_warn_return(status, "Timeout waiting for I2C BUSY to clear");
  1111. for (j = 0; j < 16; j++) {
  1112. u32 data_reg_addr = 0x1110 + (j * 4);
  1113. status = ufx_reg_read(dev, data_reg_addr, edid_u32++);
  1114. check_warn_return(status, "Error reading i2c data");
  1115. }
  1116. }
  1117. /* all FF's in the first 16 bytes indicates nothing is connected */
  1118. for (i = 0; i < 16; i++) {
  1119. if (edid[i] != 0xFF) {
  1120. pr_debug("edid data read successfully");
  1121. return EDID_LENGTH;
  1122. }
  1123. }
  1124. pr_warn("edid data contains all 0xff");
  1125. return -ETIMEDOUT;
  1126. }
  1127. /* 1) use sw default
  1128. * 2) Parse into various fb_info structs
  1129. * 3) Allocate virtual framebuffer memory to back highest res mode
  1130. *
  1131. * Parses EDID into three places used by various parts of fbdev:
  1132. * fb_var_screeninfo contains the timing of the monitor's preferred mode
  1133. * fb_info.monspecs is full parsed EDID info, including monspecs.modedb
  1134. * fb_info.modelist is a linked list of all monitor & VESA modes which work
  1135. *
  1136. * If EDID is not readable/valid, then modelist is all VESA modes,
  1137. * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode
  1138. * Returns 0 if successful */
  1139. static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info,
  1140. char *default_edid, size_t default_edid_size)
  1141. {
  1142. const struct fb_videomode *default_vmode = NULL;
  1143. u8 *edid;
  1144. int i, result = 0, tries = 3;
  1145. if (info->dev) /* only use mutex if info has been registered */
  1146. mutex_lock(&info->lock);
  1147. edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
  1148. if (!edid) {
  1149. result = -ENOMEM;
  1150. goto error;
  1151. }
  1152. fb_destroy_modelist(&info->modelist);
  1153. memset(&info->monspecs, 0, sizeof(info->monspecs));
  1154. /* Try to (re)read EDID from hardware first
  1155. * EDID data may return, but not parse as valid
  1156. * Try again a few times, in case of e.g. analog cable noise */
  1157. while (tries--) {
  1158. i = ufx_read_edid(dev, edid, EDID_LENGTH);
  1159. if (i >= EDID_LENGTH)
  1160. fb_edid_to_monspecs(edid, &info->monspecs);
  1161. if (info->monspecs.modedb_len > 0) {
  1162. dev->edid = edid;
  1163. dev->edid_size = i;
  1164. break;
  1165. }
  1166. }
  1167. /* If that fails, use a previously returned EDID if available */
  1168. if (info->monspecs.modedb_len == 0) {
  1169. pr_err("Unable to get valid EDID from device/display\n");
  1170. if (dev->edid) {
  1171. fb_edid_to_monspecs(dev->edid, &info->monspecs);
  1172. if (info->monspecs.modedb_len > 0)
  1173. pr_err("Using previously queried EDID\n");
  1174. }
  1175. }
  1176. /* If that fails, use the default EDID we were handed */
  1177. if (info->monspecs.modedb_len == 0) {
  1178. if (default_edid_size >= EDID_LENGTH) {
  1179. fb_edid_to_monspecs(default_edid, &info->monspecs);
  1180. if (info->monspecs.modedb_len > 0) {
  1181. memcpy(edid, default_edid, default_edid_size);
  1182. dev->edid = edid;
  1183. dev->edid_size = default_edid_size;
  1184. pr_err("Using default/backup EDID\n");
  1185. }
  1186. }
  1187. }
  1188. /* If we've got modes, let's pick a best default mode */
  1189. if (info->monspecs.modedb_len > 0) {
  1190. for (i = 0; i < info->monspecs.modedb_len; i++) {
  1191. if (ufx_is_valid_mode(&info->monspecs.modedb[i], info))
  1192. fb_add_videomode(&info->monspecs.modedb[i],
  1193. &info->modelist);
  1194. else /* if we've removed top/best mode */
  1195. info->monspecs.misc &= ~FB_MISC_1ST_DETAIL;
  1196. }
  1197. default_vmode = fb_find_best_display(&info->monspecs,
  1198. &info->modelist);
  1199. }
  1200. /* If everything else has failed, fall back to safe default mode */
  1201. if (default_vmode == NULL) {
  1202. struct fb_videomode fb_vmode = {0};
  1203. /* Add the standard VESA modes to our modelist
  1204. * Since we don't have EDID, there may be modes that
  1205. * overspec monitor and/or are incorrect aspect ratio, etc.
  1206. * But at least the user has a chance to choose
  1207. */
  1208. for (i = 0; i < VESA_MODEDB_SIZE; i++) {
  1209. if (ufx_is_valid_mode((struct fb_videomode *)
  1210. &vesa_modes[i], info))
  1211. fb_add_videomode(&vesa_modes[i],
  1212. &info->modelist);
  1213. }
  1214. /* default to resolution safe for projectors
  1215. * (since they are most common case without EDID)
  1216. */
  1217. fb_vmode.xres = 800;
  1218. fb_vmode.yres = 600;
  1219. fb_vmode.refresh = 60;
  1220. default_vmode = fb_find_nearest_mode(&fb_vmode,
  1221. &info->modelist);
  1222. }
  1223. /* If we have good mode and no active clients */
  1224. if ((default_vmode != NULL) && (dev->fb_count == 0)) {
  1225. fb_videomode_to_var(&info->var, default_vmode);
  1226. ufx_var_color_format(&info->var);
  1227. /* with mode size info, we can now alloc our framebuffer */
  1228. memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix));
  1229. info->fix.line_length = info->var.xres *
  1230. (info->var.bits_per_pixel / 8);
  1231. result = ufx_realloc_framebuffer(dev, info);
  1232. } else
  1233. result = -EINVAL;
  1234. error:
  1235. if (edid && (dev->edid != edid))
  1236. kfree(edid);
  1237. if (info->dev)
  1238. mutex_unlock(&info->lock);
  1239. return result;
  1240. }
  1241. static int ufx_usb_probe(struct usb_interface *interface,
  1242. const struct usb_device_id *id)
  1243. {
  1244. struct usb_device *usbdev;
  1245. struct ufx_data *dev;
  1246. struct fb_info *info;
  1247. int retval;
  1248. u32 id_rev, fpga_rev;
  1249. /* usb initialization */
  1250. usbdev = interface_to_usbdev(interface);
  1251. BUG_ON(!usbdev);
  1252. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  1253. if (dev == NULL) {
  1254. dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n");
  1255. return -ENOMEM;
  1256. }
  1257. /* we need to wait for both usb and fbdev to spin down on disconnect */
  1258. kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */
  1259. kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */
  1260. dev->udev = usbdev;
  1261. dev->gdev = &usbdev->dev; /* our generic struct device * */
  1262. usb_set_intfdata(interface, dev);
  1263. dev_dbg(dev->gdev, "%s %s - serial #%s\n",
  1264. usbdev->manufacturer, usbdev->product, usbdev->serial);
  1265. dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n",
  1266. le16_to_cpu(usbdev->descriptor.idVendor),
  1267. le16_to_cpu(usbdev->descriptor.idProduct),
  1268. le16_to_cpu(usbdev->descriptor.bcdDevice), dev);
  1269. dev_dbg(dev->gdev, "console enable=%d\n", console);
  1270. dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio);
  1271. if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) {
  1272. dev_err(dev->gdev, "ufx_alloc_urb_list failed\n");
  1273. goto e_nomem;
  1274. }
  1275. /* We don't register a new USB class. Our client interface is fbdev */
  1276. /* allocates framebuffer driver structure, not framebuffer memory */
  1277. info = framebuffer_alloc(0, &usbdev->dev);
  1278. if (!info)
  1279. goto e_nomem;
  1280. dev->info = info;
  1281. info->par = dev;
  1282. info->pseudo_palette = dev->pseudo_palette;
  1283. info->fbops = &ufx_ops;
  1284. INIT_LIST_HEAD(&info->modelist);
  1285. retval = fb_alloc_cmap(&info->cmap, 256, 0);
  1286. if (retval < 0) {
  1287. dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval);
  1288. goto destroy_modedb;
  1289. }
  1290. INIT_DELAYED_WORK(&dev->free_framebuffer_work,
  1291. ufx_free_framebuffer_work);
  1292. retval = ufx_reg_read(dev, 0x3000, &id_rev);
  1293. check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval);
  1294. dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev);
  1295. retval = ufx_reg_read(dev, 0x3004, &fpga_rev);
  1296. check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval);
  1297. dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev);
  1298. dev_dbg(dev->gdev, "resetting device");
  1299. retval = ufx_lite_reset(dev);
  1300. check_warn_goto_error(retval, "error %d resetting device", retval);
  1301. dev_dbg(dev->gdev, "configuring system clock");
  1302. retval = ufx_config_sys_clk(dev);
  1303. check_warn_goto_error(retval, "error %d configuring system clock", retval);
  1304. dev_dbg(dev->gdev, "configuring DDR2 controller");
  1305. retval = ufx_config_ddr2(dev);
  1306. check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval);
  1307. dev_dbg(dev->gdev, "configuring I2C controller");
  1308. retval = ufx_i2c_init(dev);
  1309. check_warn_goto_error(retval, "error %d initialising I2C controller", retval);
  1310. dev_dbg(dev->gdev, "selecting display mode");
  1311. retval = ufx_setup_modes(dev, info, NULL, 0);
  1312. check_warn_goto_error(retval, "unable to find common mode for display and adapter");
  1313. retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001);
  1314. check_warn_goto_error(retval, "error %d enabling graphics engine", retval);
  1315. /* ready to begin using device */
  1316. atomic_set(&dev->usb_active, 1);
  1317. dev_dbg(dev->gdev, "checking var");
  1318. retval = ufx_ops_check_var(&info->var, info);
  1319. check_warn_goto_error(retval, "error %d ufx_ops_check_var", retval);
  1320. dev_dbg(dev->gdev, "setting par");
  1321. retval = ufx_ops_set_par(info);
  1322. check_warn_goto_error(retval, "error %d ufx_ops_set_par", retval);
  1323. dev_dbg(dev->gdev, "registering framebuffer");
  1324. retval = register_framebuffer(info);
  1325. check_warn_goto_error(retval, "error %d register_framebuffer", retval);
  1326. dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution."
  1327. " Using %dK framebuffer memory\n", info->node,
  1328. info->var.xres, info->var.yres, info->fix.smem_len >> 10);
  1329. return 0;
  1330. error:
  1331. fb_dealloc_cmap(&info->cmap);
  1332. destroy_modedb:
  1333. fb_destroy_modedb(info->monspecs.modedb);
  1334. vfree(info->screen_base);
  1335. fb_destroy_modelist(&info->modelist);
  1336. framebuffer_release(info);
  1337. put_ref:
  1338. kref_put(&dev->kref, ufx_free); /* ref for framebuffer */
  1339. kref_put(&dev->kref, ufx_free); /* last ref from kref_init */
  1340. return retval;
  1341. e_nomem:
  1342. retval = -ENOMEM;
  1343. goto put_ref;
  1344. }
  1345. static void ufx_usb_disconnect(struct usb_interface *interface)
  1346. {
  1347. struct ufx_data *dev;
  1348. dev = usb_get_intfdata(interface);
  1349. pr_debug("USB disconnect starting\n");
  1350. /* we virtualize until all fb clients release. Then we free */
  1351. dev->virtualized = true;
  1352. /* When non-active we'll update virtual framebuffer, but no new urbs */
  1353. atomic_set(&dev->usb_active, 0);
  1354. usb_set_intfdata(interface, NULL);
  1355. /* if clients still have us open, will be freed on last close */
  1356. if (dev->fb_count == 0)
  1357. schedule_delayed_work(&dev->free_framebuffer_work, 0);
  1358. /* release reference taken by kref_init in probe() */
  1359. kref_put(&dev->kref, ufx_free);
  1360. /* consider ufx_data freed */
  1361. }
  1362. static struct usb_driver ufx_driver = {
  1363. .name = "smscufx",
  1364. .probe = ufx_usb_probe,
  1365. .disconnect = ufx_usb_disconnect,
  1366. .id_table = id_table,
  1367. };
  1368. module_usb_driver(ufx_driver);
  1369. static void ufx_urb_completion(struct urb *urb)
  1370. {
  1371. struct urb_node *unode = urb->context;
  1372. struct ufx_data *dev = unode->dev;
  1373. unsigned long flags;
  1374. /* sync/async unlink faults aren't errors */
  1375. if (urb->status) {
  1376. if (!(urb->status == -ENOENT ||
  1377. urb->status == -ECONNRESET ||
  1378. urb->status == -ESHUTDOWN)) {
  1379. pr_err("%s - nonzero write bulk status received: %d\n",
  1380. __func__, urb->status);
  1381. atomic_set(&dev->lost_pixels, 1);
  1382. }
  1383. }
  1384. urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */
  1385. spin_lock_irqsave(&dev->urbs.lock, flags);
  1386. list_add_tail(&unode->entry, &dev->urbs.list);
  1387. dev->urbs.available++;
  1388. spin_unlock_irqrestore(&dev->urbs.lock, flags);
  1389. /* When using fb_defio, we deadlock if up() is called
  1390. * while another is waiting. So queue to another process */
  1391. if (fb_defio)
  1392. schedule_delayed_work(&unode->release_urb_work, 0);
  1393. else
  1394. up(&dev->urbs.limit_sem);
  1395. }
  1396. static void ufx_free_urb_list(struct ufx_data *dev)
  1397. {
  1398. int count = dev->urbs.count;
  1399. struct list_head *node;
  1400. struct urb_node *unode;
  1401. struct urb *urb;
  1402. int ret;
  1403. unsigned long flags;
  1404. pr_debug("Waiting for completes and freeing all render urbs\n");
  1405. /* keep waiting and freeing, until we've got 'em all */
  1406. while (count--) {
  1407. /* Getting interrupted means a leak, but ok at shutdown*/
  1408. ret = down_interruptible(&dev->urbs.limit_sem);
  1409. if (ret)
  1410. break;
  1411. spin_lock_irqsave(&dev->urbs.lock, flags);
  1412. node = dev->urbs.list.next; /* have reserved one with sem */
  1413. list_del_init(node);
  1414. spin_unlock_irqrestore(&dev->urbs.lock, flags);
  1415. unode = list_entry(node, struct urb_node, entry);
  1416. urb = unode->urb;
  1417. /* Free each separately allocated piece */
  1418. usb_free_coherent(urb->dev, dev->urbs.size,
  1419. urb->transfer_buffer, urb->transfer_dma);
  1420. usb_free_urb(urb);
  1421. kfree(node);
  1422. }
  1423. }
  1424. static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size)
  1425. {
  1426. int i = 0;
  1427. struct urb *urb;
  1428. struct urb_node *unode;
  1429. char *buf;
  1430. spin_lock_init(&dev->urbs.lock);
  1431. dev->urbs.size = size;
  1432. INIT_LIST_HEAD(&dev->urbs.list);
  1433. while (i < count) {
  1434. unode = kzalloc(sizeof(*unode), GFP_KERNEL);
  1435. if (!unode)
  1436. break;
  1437. unode->dev = dev;
  1438. INIT_DELAYED_WORK(&unode->release_urb_work,
  1439. ufx_release_urb_work);
  1440. urb = usb_alloc_urb(0, GFP_KERNEL);
  1441. if (!urb) {
  1442. kfree(unode);
  1443. break;
  1444. }
  1445. unode->urb = urb;
  1446. buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL,
  1447. &urb->transfer_dma);
  1448. if (!buf) {
  1449. kfree(unode);
  1450. usb_free_urb(urb);
  1451. break;
  1452. }
  1453. /* urb->transfer_buffer_length set to actual before submit */
  1454. usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1),
  1455. buf, size, ufx_urb_completion, unode);
  1456. urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
  1457. list_add_tail(&unode->entry, &dev->urbs.list);
  1458. i++;
  1459. }
  1460. sema_init(&dev->urbs.limit_sem, i);
  1461. dev->urbs.count = i;
  1462. dev->urbs.available = i;
  1463. pr_debug("allocated %d %d byte urbs\n", i, (int) size);
  1464. return i;
  1465. }
  1466. static struct urb *ufx_get_urb(struct ufx_data *dev)
  1467. {
  1468. int ret = 0;
  1469. struct list_head *entry;
  1470. struct urb_node *unode;
  1471. struct urb *urb = NULL;
  1472. unsigned long flags;
  1473. /* Wait for an in-flight buffer to complete and get re-queued */
  1474. ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT);
  1475. if (ret) {
  1476. atomic_set(&dev->lost_pixels, 1);
  1477. pr_warn("wait for urb interrupted: %x available: %d\n",
  1478. ret, dev->urbs.available);
  1479. goto error;
  1480. }
  1481. spin_lock_irqsave(&dev->urbs.lock, flags);
  1482. BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */
  1483. entry = dev->urbs.list.next;
  1484. list_del_init(entry);
  1485. dev->urbs.available--;
  1486. spin_unlock_irqrestore(&dev->urbs.lock, flags);
  1487. unode = list_entry(entry, struct urb_node, entry);
  1488. urb = unode->urb;
  1489. error:
  1490. return urb;
  1491. }
  1492. static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len)
  1493. {
  1494. int ret;
  1495. BUG_ON(len > dev->urbs.size);
  1496. urb->transfer_buffer_length = len; /* set to actual payload len */
  1497. ret = usb_submit_urb(urb, GFP_KERNEL);
  1498. if (ret) {
  1499. ufx_urb_completion(urb); /* because no one else will */
  1500. atomic_set(&dev->lost_pixels, 1);
  1501. pr_err("usb_submit_urb error %x\n", ret);
  1502. }
  1503. return ret;
  1504. }
  1505. module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
  1506. MODULE_PARM_DESC(console, "Allow fbcon to be used on this display");
  1507. module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
  1508. MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support");
  1509. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1510. MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver");
  1511. MODULE_LICENSE("GPL");