s3fb.c 44 KB

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  1. /*
  2. * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
  3. *
  4. * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive for
  8. * more details.
  9. *
  10. * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
  11. * which is based on the code of neofb.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/string.h>
  17. #include <linux/mm.h>
  18. #include <linux/tty.h>
  19. #include <linux/delay.h>
  20. #include <linux/fb.h>
  21. #include <linux/svga.h>
  22. #include <linux/init.h>
  23. #include <linux/pci.h>
  24. #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
  25. #include <video/vga.h>
  26. #include <linux/i2c.h>
  27. #include <linux/i2c-algo-bit.h>
  28. struct s3fb_info {
  29. int chip, rev, mclk_freq;
  30. int wc_cookie;
  31. struct vgastate state;
  32. struct mutex open_lock;
  33. unsigned int ref_count;
  34. u32 pseudo_palette[16];
  35. #ifdef CONFIG_FB_S3_DDC
  36. u8 __iomem *mmio;
  37. bool ddc_registered;
  38. struct i2c_adapter ddc_adapter;
  39. struct i2c_algo_bit_data ddc_algo;
  40. #endif
  41. };
  42. /* ------------------------------------------------------------------------- */
  43. static const struct svga_fb_format s3fb_formats[] = {
  44. { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  45. FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  46. { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
  47. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  48. { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
  49. FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  50. { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  51. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
  52. {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
  53. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
  54. {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
  55. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
  56. {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  57. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
  58. {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  59. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
  60. SVGA_FORMAT_END
  61. };
  62. static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
  63. 35000, 240000, 14318};
  64. static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
  65. 230000, 460000, 14318};
  66. static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
  67. static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
  68. "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
  69. "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
  70. "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
  71. "S3 Virge/GX2", "S3 Virge/GX2+", "",
  72. "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
  73. "S3 Trio3D", "S3 Virge/MX"};
  74. #define CHIP_UNKNOWN 0x00
  75. #define CHIP_732_TRIO32 0x01
  76. #define CHIP_764_TRIO64 0x02
  77. #define CHIP_765_TRIO64VP 0x03
  78. #define CHIP_767_TRIO64UVP 0x04
  79. #define CHIP_775_TRIO64V2_DX 0x05
  80. #define CHIP_785_TRIO64V2_GX 0x06
  81. #define CHIP_551_PLATO_PX 0x07
  82. #define CHIP_M65_AURORA64VP 0x08
  83. #define CHIP_325_VIRGE 0x09
  84. #define CHIP_988_VIRGE_VX 0x0A
  85. #define CHIP_375_VIRGE_DX 0x0B
  86. #define CHIP_385_VIRGE_GX 0x0C
  87. #define CHIP_357_VIRGE_GX2 0x0D
  88. #define CHIP_359_VIRGE_GX2P 0x0E
  89. #define CHIP_360_TRIO3D_1X 0x10
  90. #define CHIP_362_TRIO3D_2X 0x11
  91. #define CHIP_368_TRIO3D_2X 0x12
  92. #define CHIP_365_TRIO3D 0x13
  93. #define CHIP_260_VIRGE_MX 0x14
  94. #define CHIP_XXX_TRIO 0x80
  95. #define CHIP_XXX_TRIO64V2_DXGX 0x81
  96. #define CHIP_XXX_VIRGE_DXGX 0x82
  97. #define CHIP_36X_TRIO3D_1X_2X 0x83
  98. #define CHIP_UNDECIDED_FLAG 0x80
  99. #define CHIP_MASK 0xFF
  100. #define MMIO_OFFSET 0x1000000
  101. #define MMIO_SIZE 0x10000
  102. /* CRT timing register sets */
  103. static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
  104. static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
  105. static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
  106. static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
  107. static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
  108. static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
  109. static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
  110. static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
  111. static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
  112. static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
  113. static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
  114. static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
  115. static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
  116. static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
  117. static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
  118. static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
  119. static const struct svga_timing_regs s3_timing_regs = {
  120. s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
  121. s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
  122. s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
  123. s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
  124. };
  125. /* ------------------------------------------------------------------------- */
  126. /* Module parameters */
  127. static char *mode_option;
  128. static int mtrr = 1;
  129. static int fasttext = 1;
  130. MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
  131. MODULE_LICENSE("GPL");
  132. MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
  133. module_param(mode_option, charp, 0444);
  134. MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
  135. module_param_named(mode, mode_option, charp, 0444);
  136. MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
  137. module_param(mtrr, int, 0444);
  138. MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
  139. module_param(fasttext, int, 0644);
  140. MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
  141. /* ------------------------------------------------------------------------- */
  142. #ifdef CONFIG_FB_S3_DDC
  143. #define DDC_REG 0xaa /* Trio 3D/1X/2X */
  144. #define DDC_MMIO_REG 0xff20 /* all other chips */
  145. #define DDC_SCL_OUT (1 << 0)
  146. #define DDC_SDA_OUT (1 << 1)
  147. #define DDC_SCL_IN (1 << 2)
  148. #define DDC_SDA_IN (1 << 3)
  149. #define DDC_DRIVE_EN (1 << 4)
  150. static bool s3fb_ddc_needs_mmio(int chip)
  151. {
  152. return !(chip == CHIP_360_TRIO3D_1X ||
  153. chip == CHIP_362_TRIO3D_2X ||
  154. chip == CHIP_368_TRIO3D_2X);
  155. }
  156. static u8 s3fb_ddc_read(struct s3fb_info *par)
  157. {
  158. if (s3fb_ddc_needs_mmio(par->chip))
  159. return readb(par->mmio + DDC_MMIO_REG);
  160. else
  161. return vga_rcrt(par->state.vgabase, DDC_REG);
  162. }
  163. static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
  164. {
  165. if (s3fb_ddc_needs_mmio(par->chip))
  166. writeb(val, par->mmio + DDC_MMIO_REG);
  167. else
  168. vga_wcrt(par->state.vgabase, DDC_REG, val);
  169. }
  170. static void s3fb_ddc_setscl(void *data, int val)
  171. {
  172. struct s3fb_info *par = data;
  173. unsigned char reg;
  174. reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
  175. if (val)
  176. reg |= DDC_SCL_OUT;
  177. else
  178. reg &= ~DDC_SCL_OUT;
  179. s3fb_ddc_write(par, reg);
  180. }
  181. static void s3fb_ddc_setsda(void *data, int val)
  182. {
  183. struct s3fb_info *par = data;
  184. unsigned char reg;
  185. reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
  186. if (val)
  187. reg |= DDC_SDA_OUT;
  188. else
  189. reg &= ~DDC_SDA_OUT;
  190. s3fb_ddc_write(par, reg);
  191. }
  192. static int s3fb_ddc_getscl(void *data)
  193. {
  194. struct s3fb_info *par = data;
  195. return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
  196. }
  197. static int s3fb_ddc_getsda(void *data)
  198. {
  199. struct s3fb_info *par = data;
  200. return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
  201. }
  202. static int s3fb_setup_ddc_bus(struct fb_info *info)
  203. {
  204. struct s3fb_info *par = info->par;
  205. strlcpy(par->ddc_adapter.name, info->fix.id,
  206. sizeof(par->ddc_adapter.name));
  207. par->ddc_adapter.owner = THIS_MODULE;
  208. par->ddc_adapter.class = I2C_CLASS_DDC;
  209. par->ddc_adapter.algo_data = &par->ddc_algo;
  210. par->ddc_adapter.dev.parent = info->device;
  211. par->ddc_algo.setsda = s3fb_ddc_setsda;
  212. par->ddc_algo.setscl = s3fb_ddc_setscl;
  213. par->ddc_algo.getsda = s3fb_ddc_getsda;
  214. par->ddc_algo.getscl = s3fb_ddc_getscl;
  215. par->ddc_algo.udelay = 10;
  216. par->ddc_algo.timeout = 20;
  217. par->ddc_algo.data = par;
  218. i2c_set_adapdata(&par->ddc_adapter, par);
  219. /*
  220. * some Virge cards have external MUX to switch chip I2C bus between
  221. * DDC and extension pins - switch it do DDC
  222. */
  223. /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
  224. if (par->chip == CHIP_357_VIRGE_GX2 ||
  225. par->chip == CHIP_359_VIRGE_GX2P ||
  226. par->chip == CHIP_260_VIRGE_MX)
  227. svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
  228. else
  229. svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
  230. /* some Virge need this or the DDC is ignored */
  231. svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
  232. return i2c_bit_add_bus(&par->ddc_adapter);
  233. }
  234. #endif /* CONFIG_FB_S3_DDC */
  235. /* ------------------------------------------------------------------------- */
  236. /* Set font in S3 fast text mode */
  237. static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
  238. {
  239. const u8 *font = map->data;
  240. u8 __iomem *fb = (u8 __iomem *) info->screen_base;
  241. int i, c;
  242. if ((map->width != 8) || (map->height != 16) ||
  243. (map->depth != 1) || (map->length != 256)) {
  244. fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
  245. map->width, map->height, map->depth, map->length);
  246. return;
  247. }
  248. fb += 2;
  249. for (i = 0; i < map->height; i++) {
  250. for (c = 0; c < map->length; c++) {
  251. fb_writeb(font[c * map->height + i], fb + c * 4);
  252. }
  253. fb += 1024;
  254. }
  255. }
  256. static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
  257. {
  258. struct s3fb_info *par = info->par;
  259. svga_tilecursor(par->state.vgabase, info, cursor);
  260. }
  261. static struct fb_tile_ops s3fb_tile_ops = {
  262. .fb_settile = svga_settile,
  263. .fb_tilecopy = svga_tilecopy,
  264. .fb_tilefill = svga_tilefill,
  265. .fb_tileblit = svga_tileblit,
  266. .fb_tilecursor = s3fb_tilecursor,
  267. .fb_get_tilemax = svga_get_tilemax,
  268. };
  269. static struct fb_tile_ops s3fb_fast_tile_ops = {
  270. .fb_settile = s3fb_settile_fast,
  271. .fb_tilecopy = svga_tilecopy,
  272. .fb_tilefill = svga_tilefill,
  273. .fb_tileblit = svga_tileblit,
  274. .fb_tilecursor = s3fb_tilecursor,
  275. .fb_get_tilemax = svga_get_tilemax,
  276. };
  277. /* ------------------------------------------------------------------------- */
  278. /* image data is MSB-first, fb structure is MSB-first too */
  279. static inline u32 expand_color(u32 c)
  280. {
  281. return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
  282. }
  283. /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
  284. static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
  285. {
  286. u32 fg = expand_color(image->fg_color);
  287. u32 bg = expand_color(image->bg_color);
  288. const u8 *src1, *src;
  289. u8 __iomem *dst1;
  290. u32 __iomem *dst;
  291. u32 val;
  292. int x, y;
  293. src1 = image->data;
  294. dst1 = info->screen_base + (image->dy * info->fix.line_length)
  295. + ((image->dx / 8) * 4);
  296. for (y = 0; y < image->height; y++) {
  297. src = src1;
  298. dst = (u32 __iomem *) dst1;
  299. for (x = 0; x < image->width; x += 8) {
  300. val = *(src++) * 0x01010101;
  301. val = (val & fg) | (~val & bg);
  302. fb_writel(val, dst++);
  303. }
  304. src1 += image->width / 8;
  305. dst1 += info->fix.line_length;
  306. }
  307. }
  308. /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
  309. static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  310. {
  311. u32 fg = expand_color(rect->color);
  312. u8 __iomem *dst1;
  313. u32 __iomem *dst;
  314. int x, y;
  315. dst1 = info->screen_base + (rect->dy * info->fix.line_length)
  316. + ((rect->dx / 8) * 4);
  317. for (y = 0; y < rect->height; y++) {
  318. dst = (u32 __iomem *) dst1;
  319. for (x = 0; x < rect->width; x += 8) {
  320. fb_writel(fg, dst++);
  321. }
  322. dst1 += info->fix.line_length;
  323. }
  324. }
  325. /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
  326. static inline u32 expand_pixel(u32 c)
  327. {
  328. return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
  329. ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
  330. }
  331. /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
  332. static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
  333. {
  334. u32 fg = image->fg_color * 0x11111111;
  335. u32 bg = image->bg_color * 0x11111111;
  336. const u8 *src1, *src;
  337. u8 __iomem *dst1;
  338. u32 __iomem *dst;
  339. u32 val;
  340. int x, y;
  341. src1 = image->data;
  342. dst1 = info->screen_base + (image->dy * info->fix.line_length)
  343. + ((image->dx / 8) * 4);
  344. for (y = 0; y < image->height; y++) {
  345. src = src1;
  346. dst = (u32 __iomem *) dst1;
  347. for (x = 0; x < image->width; x += 8) {
  348. val = expand_pixel(*(src++));
  349. val = (val & fg) | (~val & bg);
  350. fb_writel(val, dst++);
  351. }
  352. src1 += image->width / 8;
  353. dst1 += info->fix.line_length;
  354. }
  355. }
  356. static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
  357. {
  358. if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
  359. && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
  360. if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
  361. s3fb_iplan_imageblit(info, image);
  362. else
  363. s3fb_cfb4_imageblit(info, image);
  364. } else
  365. cfb_imageblit(info, image);
  366. }
  367. static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  368. {
  369. if ((info->var.bits_per_pixel == 4)
  370. && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
  371. && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
  372. s3fb_iplan_fillrect(info, rect);
  373. else
  374. cfb_fillrect(info, rect);
  375. }
  376. /* ------------------------------------------------------------------------- */
  377. static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
  378. {
  379. struct s3fb_info *par = info->par;
  380. u16 m, n, r;
  381. u8 regval;
  382. int rv;
  383. rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
  384. 1000000000 / pixclock, &m, &n, &r, info->node);
  385. if (rv < 0) {
  386. fb_err(info, "cannot set requested pixclock, keeping old value\n");
  387. return;
  388. }
  389. /* Set VGA misc register */
  390. regval = vga_r(par->state.vgabase, VGA_MIS_R);
  391. vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
  392. /* Set S3 clock registers */
  393. if (par->chip == CHIP_357_VIRGE_GX2 ||
  394. par->chip == CHIP_359_VIRGE_GX2P ||
  395. par->chip == CHIP_360_TRIO3D_1X ||
  396. par->chip == CHIP_362_TRIO3D_2X ||
  397. par->chip == CHIP_368_TRIO3D_2X ||
  398. par->chip == CHIP_260_VIRGE_MX) {
  399. vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
  400. vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
  401. } else
  402. vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
  403. vga_wseq(par->state.vgabase, 0x13, m - 2);
  404. udelay(1000);
  405. /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
  406. regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
  407. vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
  408. vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
  409. vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
  410. }
  411. /* Open framebuffer */
  412. static int s3fb_open(struct fb_info *info, int user)
  413. {
  414. struct s3fb_info *par = info->par;
  415. mutex_lock(&(par->open_lock));
  416. if (par->ref_count == 0) {
  417. void __iomem *vgabase = par->state.vgabase;
  418. memset(&(par->state), 0, sizeof(struct vgastate));
  419. par->state.vgabase = vgabase;
  420. par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
  421. par->state.num_crtc = 0x70;
  422. par->state.num_seq = 0x20;
  423. save_vga(&(par->state));
  424. }
  425. par->ref_count++;
  426. mutex_unlock(&(par->open_lock));
  427. return 0;
  428. }
  429. /* Close framebuffer */
  430. static int s3fb_release(struct fb_info *info, int user)
  431. {
  432. struct s3fb_info *par = info->par;
  433. mutex_lock(&(par->open_lock));
  434. if (par->ref_count == 0) {
  435. mutex_unlock(&(par->open_lock));
  436. return -EINVAL;
  437. }
  438. if (par->ref_count == 1)
  439. restore_vga(&(par->state));
  440. par->ref_count--;
  441. mutex_unlock(&(par->open_lock));
  442. return 0;
  443. }
  444. /* Validate passed in var */
  445. static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  446. {
  447. struct s3fb_info *par = info->par;
  448. int rv, mem, step;
  449. u16 m, n, r;
  450. /* Find appropriate format */
  451. rv = svga_match_format (s3fb_formats, var, NULL);
  452. /* 32bpp mode is not supported on VIRGE VX,
  453. 24bpp is not supported on others */
  454. if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
  455. rv = -EINVAL;
  456. if (rv < 0) {
  457. fb_err(info, "unsupported mode requested\n");
  458. return rv;
  459. }
  460. /* Do not allow to have real resoulution larger than virtual */
  461. if (var->xres > var->xres_virtual)
  462. var->xres_virtual = var->xres;
  463. if (var->yres > var->yres_virtual)
  464. var->yres_virtual = var->yres;
  465. /* Round up xres_virtual to have proper alignment of lines */
  466. step = s3fb_formats[rv].xresstep - 1;
  467. var->xres_virtual = (var->xres_virtual+step) & ~step;
  468. /* Check whether have enough memory */
  469. mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
  470. if (mem > info->screen_size) {
  471. fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n",
  472. mem >> 10, (unsigned int) (info->screen_size >> 10));
  473. return -EINVAL;
  474. }
  475. rv = svga_check_timings (&s3_timing_regs, var, info->node);
  476. if (rv < 0) {
  477. fb_err(info, "invalid timings requested\n");
  478. return rv;
  479. }
  480. rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
  481. info->node);
  482. if (rv < 0) {
  483. fb_err(info, "invalid pixclock value requested\n");
  484. return rv;
  485. }
  486. return 0;
  487. }
  488. /* Set video mode from par */
  489. static int s3fb_set_par(struct fb_info *info)
  490. {
  491. struct s3fb_info *par = info->par;
  492. u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
  493. u32 bpp = info->var.bits_per_pixel;
  494. u32 htotal, hsstart;
  495. if (bpp != 0) {
  496. info->fix.ypanstep = 1;
  497. info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
  498. info->flags &= ~FBINFO_MISC_TILEBLITTING;
  499. info->tileops = NULL;
  500. /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
  501. info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
  502. info->pixmap.blit_y = ~(u32)0;
  503. offset_value = (info->var.xres_virtual * bpp) / 64;
  504. screen_size = info->var.yres_virtual * info->fix.line_length;
  505. } else {
  506. info->fix.ypanstep = 16;
  507. info->fix.line_length = 0;
  508. info->flags |= FBINFO_MISC_TILEBLITTING;
  509. info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
  510. /* supports 8x16 tiles only */
  511. info->pixmap.blit_x = 1 << (8 - 1);
  512. info->pixmap.blit_y = 1 << (16 - 1);
  513. offset_value = info->var.xres_virtual / 16;
  514. screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
  515. }
  516. info->var.xoffset = 0;
  517. info->var.yoffset = 0;
  518. info->var.activate = FB_ACTIVATE_NOW;
  519. /* Unlock registers */
  520. vga_wcrt(par->state.vgabase, 0x38, 0x48);
  521. vga_wcrt(par->state.vgabase, 0x39, 0xA5);
  522. vga_wseq(par->state.vgabase, 0x08, 0x06);
  523. svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
  524. /* Blank screen and turn off sync */
  525. svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
  526. svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
  527. /* Set default values */
  528. svga_set_default_gfx_regs(par->state.vgabase);
  529. svga_set_default_atc_regs(par->state.vgabase);
  530. svga_set_default_seq_regs(par->state.vgabase);
  531. svga_set_default_crt_regs(par->state.vgabase);
  532. svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
  533. svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
  534. /* S3 specific initialization */
  535. svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
  536. svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
  537. /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
  538. /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
  539. svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
  540. svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
  541. svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
  542. /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
  543. /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
  544. /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
  545. /* Set the offset register */
  546. fb_dbg(info, "offset register : %d\n", offset_value);
  547. svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
  548. if (par->chip != CHIP_357_VIRGE_GX2 &&
  549. par->chip != CHIP_359_VIRGE_GX2P &&
  550. par->chip != CHIP_360_TRIO3D_1X &&
  551. par->chip != CHIP_362_TRIO3D_2X &&
  552. par->chip != CHIP_368_TRIO3D_2X &&
  553. par->chip != CHIP_260_VIRGE_MX) {
  554. vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
  555. vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
  556. vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
  557. vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
  558. }
  559. vga_wcrt(par->state.vgabase, 0x3A, 0x35);
  560. svga_wattr(par->state.vgabase, 0x33, 0x00);
  561. if (info->var.vmode & FB_VMODE_DOUBLE)
  562. svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
  563. else
  564. svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
  565. if (info->var.vmode & FB_VMODE_INTERLACED)
  566. svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
  567. else
  568. svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
  569. /* Disable hardware graphics cursor */
  570. svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
  571. /* Disable Streams engine */
  572. svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
  573. mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
  574. /* S3 virge DX hack */
  575. if (par->chip == CHIP_375_VIRGE_DX) {
  576. vga_wcrt(par->state.vgabase, 0x86, 0x80);
  577. vga_wcrt(par->state.vgabase, 0x90, 0x00);
  578. }
  579. /* S3 virge VX hack */
  580. if (par->chip == CHIP_988_VIRGE_VX) {
  581. vga_wcrt(par->state.vgabase, 0x50, 0x00);
  582. vga_wcrt(par->state.vgabase, 0x67, 0x50);
  583. msleep(10); /* screen remains blank sometimes without this */
  584. vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
  585. vga_wcrt(par->state.vgabase, 0x66, 0x90);
  586. }
  587. if (par->chip == CHIP_357_VIRGE_GX2 ||
  588. par->chip == CHIP_359_VIRGE_GX2P ||
  589. par->chip == CHIP_360_TRIO3D_1X ||
  590. par->chip == CHIP_362_TRIO3D_2X ||
  591. par->chip == CHIP_368_TRIO3D_2X ||
  592. par->chip == CHIP_365_TRIO3D ||
  593. par->chip == CHIP_375_VIRGE_DX ||
  594. par->chip == CHIP_385_VIRGE_GX ||
  595. par->chip == CHIP_260_VIRGE_MX) {
  596. dbytes = info->var.xres * ((bpp+7)/8);
  597. vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
  598. vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
  599. vga_wcrt(par->state.vgabase, 0x66, 0x81);
  600. }
  601. if (par->chip == CHIP_357_VIRGE_GX2 ||
  602. par->chip == CHIP_359_VIRGE_GX2P ||
  603. par->chip == CHIP_360_TRIO3D_1X ||
  604. par->chip == CHIP_362_TRIO3D_2X ||
  605. par->chip == CHIP_368_TRIO3D_2X ||
  606. par->chip == CHIP_260_VIRGE_MX)
  607. vga_wcrt(par->state.vgabase, 0x34, 0x00);
  608. else /* enable Data Transfer Position Control (DTPC) */
  609. vga_wcrt(par->state.vgabase, 0x34, 0x10);
  610. svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
  611. multiplex = 0;
  612. hmul = 1;
  613. /* Set mode-specific register values */
  614. switch (mode) {
  615. case 0:
  616. fb_dbg(info, "text mode\n");
  617. svga_set_textmode_vga_regs(par->state.vgabase);
  618. /* Set additional registers like in 8-bit mode */
  619. svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
  620. svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
  621. /* Disable enhanced mode */
  622. svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
  623. if (fasttext) {
  624. fb_dbg(info, "high speed text mode set\n");
  625. svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
  626. }
  627. break;
  628. case 1:
  629. fb_dbg(info, "4 bit pseudocolor\n");
  630. vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
  631. /* Set additional registers like in 8-bit mode */
  632. svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
  633. svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
  634. /* disable enhanced mode */
  635. svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
  636. break;
  637. case 2:
  638. fb_dbg(info, "4 bit pseudocolor, planar\n");
  639. /* Set additional registers like in 8-bit mode */
  640. svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
  641. svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
  642. /* disable enhanced mode */
  643. svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
  644. break;
  645. case 3:
  646. fb_dbg(info, "8 bit pseudocolor\n");
  647. svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
  648. if (info->var.pixclock > 20000 ||
  649. par->chip == CHIP_357_VIRGE_GX2 ||
  650. par->chip == CHIP_359_VIRGE_GX2P ||
  651. par->chip == CHIP_360_TRIO3D_1X ||
  652. par->chip == CHIP_362_TRIO3D_2X ||
  653. par->chip == CHIP_368_TRIO3D_2X ||
  654. par->chip == CHIP_260_VIRGE_MX)
  655. svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
  656. else {
  657. svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
  658. multiplex = 1;
  659. }
  660. break;
  661. case 4:
  662. fb_dbg(info, "5/5/5 truecolor\n");
  663. if (par->chip == CHIP_988_VIRGE_VX) {
  664. if (info->var.pixclock > 20000)
  665. svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
  666. else
  667. svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
  668. } else if (par->chip == CHIP_365_TRIO3D) {
  669. svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
  670. if (info->var.pixclock > 8695) {
  671. svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
  672. hmul = 2;
  673. } else {
  674. svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
  675. multiplex = 1;
  676. }
  677. } else {
  678. svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
  679. svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
  680. if (par->chip != CHIP_357_VIRGE_GX2 &&
  681. par->chip != CHIP_359_VIRGE_GX2P &&
  682. par->chip != CHIP_360_TRIO3D_1X &&
  683. par->chip != CHIP_362_TRIO3D_2X &&
  684. par->chip != CHIP_368_TRIO3D_2X &&
  685. par->chip != CHIP_260_VIRGE_MX)
  686. hmul = 2;
  687. }
  688. break;
  689. case 5:
  690. fb_dbg(info, "5/6/5 truecolor\n");
  691. if (par->chip == CHIP_988_VIRGE_VX) {
  692. if (info->var.pixclock > 20000)
  693. svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
  694. else
  695. svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
  696. } else if (par->chip == CHIP_365_TRIO3D) {
  697. svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
  698. if (info->var.pixclock > 8695) {
  699. svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
  700. hmul = 2;
  701. } else {
  702. svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
  703. multiplex = 1;
  704. }
  705. } else {
  706. svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
  707. svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
  708. if (par->chip != CHIP_357_VIRGE_GX2 &&
  709. par->chip != CHIP_359_VIRGE_GX2P &&
  710. par->chip != CHIP_360_TRIO3D_1X &&
  711. par->chip != CHIP_362_TRIO3D_2X &&
  712. par->chip != CHIP_368_TRIO3D_2X &&
  713. par->chip != CHIP_260_VIRGE_MX)
  714. hmul = 2;
  715. }
  716. break;
  717. case 6:
  718. /* VIRGE VX case */
  719. fb_dbg(info, "8/8/8 truecolor\n");
  720. svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
  721. break;
  722. case 7:
  723. fb_dbg(info, "8/8/8/8 truecolor\n");
  724. svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
  725. svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
  726. break;
  727. default:
  728. fb_err(info, "unsupported mode - bug\n");
  729. return -EINVAL;
  730. }
  731. if (par->chip != CHIP_988_VIRGE_VX) {
  732. svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
  733. svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
  734. }
  735. s3_set_pixclock(info, info->var.pixclock);
  736. svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
  737. (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
  738. (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
  739. hmul, info->node);
  740. /* Set interlaced mode start/end register */
  741. htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
  742. htotal = ((htotal * hmul) / 8) - 5;
  743. vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
  744. /* Set Data Transfer Position */
  745. hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
  746. /* + 2 is needed for Virge/VX, does no harm on other cards */
  747. value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1);
  748. svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
  749. memset_io(info->screen_base, 0x00, screen_size);
  750. /* Device and screen back on */
  751. svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
  752. svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
  753. return 0;
  754. }
  755. /* Set a colour register */
  756. static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  757. u_int transp, struct fb_info *fb)
  758. {
  759. switch (fb->var.bits_per_pixel) {
  760. case 0:
  761. case 4:
  762. if (regno >= 16)
  763. return -EINVAL;
  764. if ((fb->var.bits_per_pixel == 4) &&
  765. (fb->var.nonstd == 0)) {
  766. outb(0xF0, VGA_PEL_MSK);
  767. outb(regno*16, VGA_PEL_IW);
  768. } else {
  769. outb(0x0F, VGA_PEL_MSK);
  770. outb(regno, VGA_PEL_IW);
  771. }
  772. outb(red >> 10, VGA_PEL_D);
  773. outb(green >> 10, VGA_PEL_D);
  774. outb(blue >> 10, VGA_PEL_D);
  775. break;
  776. case 8:
  777. if (regno >= 256)
  778. return -EINVAL;
  779. outb(0xFF, VGA_PEL_MSK);
  780. outb(regno, VGA_PEL_IW);
  781. outb(red >> 10, VGA_PEL_D);
  782. outb(green >> 10, VGA_PEL_D);
  783. outb(blue >> 10, VGA_PEL_D);
  784. break;
  785. case 16:
  786. if (regno >= 16)
  787. return 0;
  788. if (fb->var.green.length == 5)
  789. ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
  790. ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
  791. else if (fb->var.green.length == 6)
  792. ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
  793. ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
  794. else return -EINVAL;
  795. break;
  796. case 24:
  797. case 32:
  798. if (regno >= 16)
  799. return 0;
  800. ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
  801. (green & 0xFF00) | ((blue & 0xFF00) >> 8);
  802. break;
  803. default:
  804. return -EINVAL;
  805. }
  806. return 0;
  807. }
  808. /* Set the display blanking state */
  809. static int s3fb_blank(int blank_mode, struct fb_info *info)
  810. {
  811. struct s3fb_info *par = info->par;
  812. switch (blank_mode) {
  813. case FB_BLANK_UNBLANK:
  814. fb_dbg(info, "unblank\n");
  815. svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
  816. svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
  817. break;
  818. case FB_BLANK_NORMAL:
  819. fb_dbg(info, "blank\n");
  820. svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
  821. svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
  822. break;
  823. case FB_BLANK_HSYNC_SUSPEND:
  824. fb_dbg(info, "hsync\n");
  825. svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
  826. svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
  827. break;
  828. case FB_BLANK_VSYNC_SUSPEND:
  829. fb_dbg(info, "vsync\n");
  830. svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
  831. svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
  832. break;
  833. case FB_BLANK_POWERDOWN:
  834. fb_dbg(info, "sync down\n");
  835. svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
  836. svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
  837. break;
  838. }
  839. return 0;
  840. }
  841. /* Pan the display */
  842. static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  843. {
  844. struct s3fb_info *par = info->par;
  845. unsigned int offset;
  846. /* Calculate the offset */
  847. if (info->var.bits_per_pixel == 0) {
  848. offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
  849. + (var->xoffset / 2);
  850. offset = offset >> 2;
  851. } else {
  852. offset = (var->yoffset * info->fix.line_length) +
  853. (var->xoffset * info->var.bits_per_pixel / 8);
  854. offset = offset >> 2;
  855. }
  856. /* Set the offset */
  857. svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
  858. return 0;
  859. }
  860. /* ------------------------------------------------------------------------- */
  861. /* Frame buffer operations */
  862. static const struct fb_ops s3fb_ops = {
  863. .owner = THIS_MODULE,
  864. .fb_open = s3fb_open,
  865. .fb_release = s3fb_release,
  866. .fb_check_var = s3fb_check_var,
  867. .fb_set_par = s3fb_set_par,
  868. .fb_setcolreg = s3fb_setcolreg,
  869. .fb_blank = s3fb_blank,
  870. .fb_pan_display = s3fb_pan_display,
  871. .fb_fillrect = s3fb_fillrect,
  872. .fb_copyarea = cfb_copyarea,
  873. .fb_imageblit = s3fb_imageblit,
  874. .fb_get_caps = svga_get_caps,
  875. };
  876. /* ------------------------------------------------------------------------- */
  877. static int s3_identification(struct s3fb_info *par)
  878. {
  879. int chip = par->chip;
  880. if (chip == CHIP_XXX_TRIO) {
  881. u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
  882. u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
  883. u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
  884. if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
  885. if (cr2e == 0x10)
  886. return CHIP_732_TRIO32;
  887. if (cr2e == 0x11) {
  888. if (! (cr2f & 0x40))
  889. return CHIP_764_TRIO64;
  890. else
  891. return CHIP_765_TRIO64VP;
  892. }
  893. }
  894. }
  895. if (chip == CHIP_XXX_TRIO64V2_DXGX) {
  896. u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
  897. if (! (cr6f & 0x01))
  898. return CHIP_775_TRIO64V2_DX;
  899. else
  900. return CHIP_785_TRIO64V2_GX;
  901. }
  902. if (chip == CHIP_XXX_VIRGE_DXGX) {
  903. u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
  904. if (! (cr6f & 0x01))
  905. return CHIP_375_VIRGE_DX;
  906. else
  907. return CHIP_385_VIRGE_GX;
  908. }
  909. if (chip == CHIP_36X_TRIO3D_1X_2X) {
  910. switch (vga_rcrt(par->state.vgabase, 0x2f)) {
  911. case 0x00:
  912. return CHIP_360_TRIO3D_1X;
  913. case 0x01:
  914. return CHIP_362_TRIO3D_2X;
  915. case 0x02:
  916. return CHIP_368_TRIO3D_2X;
  917. }
  918. }
  919. return CHIP_UNKNOWN;
  920. }
  921. /* PCI probe */
  922. static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  923. {
  924. struct pci_bus_region bus_reg;
  925. struct resource vga_res;
  926. struct fb_info *info;
  927. struct s3fb_info *par;
  928. int rc;
  929. u8 regval, cr38, cr39;
  930. bool found = false;
  931. /* Ignore secondary VGA device because there is no VGA arbitration */
  932. if (! svga_primary_device(dev)) {
  933. dev_info(&(dev->dev), "ignoring secondary device\n");
  934. return -ENODEV;
  935. }
  936. /* Allocate and fill driver data structure */
  937. info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
  938. if (!info)
  939. return -ENOMEM;
  940. par = info->par;
  941. mutex_init(&par->open_lock);
  942. info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
  943. info->fbops = &s3fb_ops;
  944. /* Prepare PCI device */
  945. rc = pci_enable_device(dev);
  946. if (rc < 0) {
  947. dev_err(info->device, "cannot enable PCI device\n");
  948. goto err_enable_device;
  949. }
  950. rc = pci_request_regions(dev, "s3fb");
  951. if (rc < 0) {
  952. dev_err(info->device, "cannot reserve framebuffer region\n");
  953. goto err_request_regions;
  954. }
  955. info->fix.smem_start = pci_resource_start(dev, 0);
  956. info->fix.smem_len = pci_resource_len(dev, 0);
  957. /* Map physical IO memory address into kernel space */
  958. info->screen_base = pci_iomap_wc(dev, 0, 0);
  959. if (! info->screen_base) {
  960. rc = -ENOMEM;
  961. dev_err(info->device, "iomap for framebuffer failed\n");
  962. goto err_iomap;
  963. }
  964. bus_reg.start = 0;
  965. bus_reg.end = 64 * 1024;
  966. vga_res.flags = IORESOURCE_IO;
  967. pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
  968. par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
  969. /* Unlock regs */
  970. cr38 = vga_rcrt(par->state.vgabase, 0x38);
  971. cr39 = vga_rcrt(par->state.vgabase, 0x39);
  972. vga_wseq(par->state.vgabase, 0x08, 0x06);
  973. vga_wcrt(par->state.vgabase, 0x38, 0x48);
  974. vga_wcrt(par->state.vgabase, 0x39, 0xA5);
  975. /* Identify chip type */
  976. par->chip = id->driver_data & CHIP_MASK;
  977. par->rev = vga_rcrt(par->state.vgabase, 0x2f);
  978. if (par->chip & CHIP_UNDECIDED_FLAG)
  979. par->chip = s3_identification(par);
  980. /* Find how many physical memory there is on card */
  981. /* 0x36 register is accessible even if other registers are locked */
  982. regval = vga_rcrt(par->state.vgabase, 0x36);
  983. if (par->chip == CHIP_360_TRIO3D_1X ||
  984. par->chip == CHIP_362_TRIO3D_2X ||
  985. par->chip == CHIP_368_TRIO3D_2X ||
  986. par->chip == CHIP_365_TRIO3D) {
  987. switch ((regval & 0xE0) >> 5) {
  988. case 0: /* 8MB -- only 4MB usable for display */
  989. case 1: /* 4MB with 32-bit bus */
  990. case 2: /* 4MB */
  991. info->screen_size = 4 << 20;
  992. break;
  993. case 4: /* 2MB on 365 Trio3D */
  994. case 6: /* 2MB */
  995. info->screen_size = 2 << 20;
  996. break;
  997. }
  998. } else if (par->chip == CHIP_357_VIRGE_GX2 ||
  999. par->chip == CHIP_359_VIRGE_GX2P ||
  1000. par->chip == CHIP_260_VIRGE_MX) {
  1001. switch ((regval & 0xC0) >> 6) {
  1002. case 1: /* 4MB */
  1003. info->screen_size = 4 << 20;
  1004. break;
  1005. case 3: /* 2MB */
  1006. info->screen_size = 2 << 20;
  1007. break;
  1008. }
  1009. } else if (par->chip == CHIP_988_VIRGE_VX) {
  1010. switch ((regval & 0x60) >> 5) {
  1011. case 0: /* 2MB */
  1012. info->screen_size = 2 << 20;
  1013. break;
  1014. case 1: /* 4MB */
  1015. info->screen_size = 4 << 20;
  1016. break;
  1017. case 2: /* 6MB */
  1018. info->screen_size = 6 << 20;
  1019. break;
  1020. case 3: /* 8MB */
  1021. info->screen_size = 8 << 20;
  1022. break;
  1023. }
  1024. /* off-screen memory */
  1025. regval = vga_rcrt(par->state.vgabase, 0x37);
  1026. switch ((regval & 0x60) >> 5) {
  1027. case 1: /* 4MB */
  1028. info->screen_size -= 4 << 20;
  1029. break;
  1030. case 2: /* 2MB */
  1031. info->screen_size -= 2 << 20;
  1032. break;
  1033. }
  1034. } else
  1035. info->screen_size = s3_memsizes[regval >> 5] << 10;
  1036. info->fix.smem_len = info->screen_size;
  1037. /* Find MCLK frequency */
  1038. regval = vga_rseq(par->state.vgabase, 0x10);
  1039. par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
  1040. par->mclk_freq = par->mclk_freq >> (regval >> 5);
  1041. /* Restore locks */
  1042. vga_wcrt(par->state.vgabase, 0x38, cr38);
  1043. vga_wcrt(par->state.vgabase, 0x39, cr39);
  1044. strcpy(info->fix.id, s3_names [par->chip]);
  1045. info->fix.mmio_start = 0;
  1046. info->fix.mmio_len = 0;
  1047. info->fix.type = FB_TYPE_PACKED_PIXELS;
  1048. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  1049. info->fix.ypanstep = 0;
  1050. info->fix.accel = FB_ACCEL_NONE;
  1051. info->pseudo_palette = (void*) (par->pseudo_palette);
  1052. info->var.bits_per_pixel = 8;
  1053. #ifdef CONFIG_FB_S3_DDC
  1054. /* Enable MMIO if needed */
  1055. if (s3fb_ddc_needs_mmio(par->chip)) {
  1056. par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
  1057. if (par->mmio)
  1058. svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
  1059. else
  1060. dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
  1061. info->fix.smem_start + MMIO_OFFSET);
  1062. }
  1063. if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
  1064. if (s3fb_setup_ddc_bus(info) == 0) {
  1065. u8 *edid = fb_ddc_read(&par->ddc_adapter);
  1066. par->ddc_registered = true;
  1067. if (edid) {
  1068. fb_edid_to_monspecs(edid, &info->monspecs);
  1069. kfree(edid);
  1070. if (!info->monspecs.modedb)
  1071. dev_err(info->device, "error getting mode database\n");
  1072. else {
  1073. const struct fb_videomode *m;
  1074. fb_videomode_to_modelist(info->monspecs.modedb,
  1075. info->monspecs.modedb_len,
  1076. &info->modelist);
  1077. m = fb_find_best_display(&info->monspecs, &info->modelist);
  1078. if (m) {
  1079. fb_videomode_to_var(&info->var, m);
  1080. /* fill all other info->var's fields */
  1081. if (s3fb_check_var(&info->var, info) == 0)
  1082. found = true;
  1083. }
  1084. }
  1085. }
  1086. }
  1087. #endif
  1088. if (!mode_option && !found)
  1089. mode_option = "640x480-8@60";
  1090. /* Prepare startup mode */
  1091. if (mode_option) {
  1092. rc = fb_find_mode(&info->var, info, mode_option,
  1093. info->monspecs.modedb, info->monspecs.modedb_len,
  1094. NULL, info->var.bits_per_pixel);
  1095. if (!rc || rc == 4) {
  1096. rc = -EINVAL;
  1097. dev_err(info->device, "mode %s not found\n", mode_option);
  1098. fb_destroy_modedb(info->monspecs.modedb);
  1099. info->monspecs.modedb = NULL;
  1100. goto err_find_mode;
  1101. }
  1102. }
  1103. fb_destroy_modedb(info->monspecs.modedb);
  1104. info->monspecs.modedb = NULL;
  1105. /* maximize virtual vertical size for fast scrolling */
  1106. info->var.yres_virtual = info->fix.smem_len * 8 /
  1107. (info->var.bits_per_pixel * info->var.xres_virtual);
  1108. if (info->var.yres_virtual < info->var.yres) {
  1109. dev_err(info->device, "virtual vertical size smaller than real\n");
  1110. rc = -EINVAL;
  1111. goto err_find_mode;
  1112. }
  1113. rc = fb_alloc_cmap(&info->cmap, 256, 0);
  1114. if (rc < 0) {
  1115. dev_err(info->device, "cannot allocate colormap\n");
  1116. goto err_alloc_cmap;
  1117. }
  1118. rc = register_framebuffer(info);
  1119. if (rc < 0) {
  1120. dev_err(info->device, "cannot register framebuffer\n");
  1121. goto err_reg_fb;
  1122. }
  1123. fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n",
  1124. info->fix.id, pci_name(dev),
  1125. info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
  1126. if (par->chip == CHIP_UNKNOWN)
  1127. fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
  1128. vga_rcrt(par->state.vgabase, 0x2d),
  1129. vga_rcrt(par->state.vgabase, 0x2e),
  1130. vga_rcrt(par->state.vgabase, 0x2f),
  1131. vga_rcrt(par->state.vgabase, 0x30));
  1132. /* Record a reference to the driver data */
  1133. pci_set_drvdata(dev, info);
  1134. if (mtrr)
  1135. par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
  1136. info->fix.smem_len);
  1137. return 0;
  1138. /* Error handling */
  1139. err_reg_fb:
  1140. fb_dealloc_cmap(&info->cmap);
  1141. err_alloc_cmap:
  1142. err_find_mode:
  1143. #ifdef CONFIG_FB_S3_DDC
  1144. if (par->ddc_registered)
  1145. i2c_del_adapter(&par->ddc_adapter);
  1146. if (par->mmio)
  1147. iounmap(par->mmio);
  1148. #endif
  1149. pci_iounmap(dev, info->screen_base);
  1150. err_iomap:
  1151. pci_release_regions(dev);
  1152. err_request_regions:
  1153. /* pci_disable_device(dev); */
  1154. err_enable_device:
  1155. framebuffer_release(info);
  1156. return rc;
  1157. }
  1158. /* PCI remove */
  1159. static void s3_pci_remove(struct pci_dev *dev)
  1160. {
  1161. struct fb_info *info = pci_get_drvdata(dev);
  1162. struct s3fb_info __maybe_unused *par;
  1163. if (info) {
  1164. par = info->par;
  1165. arch_phys_wc_del(par->wc_cookie);
  1166. unregister_framebuffer(info);
  1167. fb_dealloc_cmap(&info->cmap);
  1168. #ifdef CONFIG_FB_S3_DDC
  1169. if (par->ddc_registered)
  1170. i2c_del_adapter(&par->ddc_adapter);
  1171. if (par->mmio)
  1172. iounmap(par->mmio);
  1173. #endif
  1174. pci_iounmap(dev, info->screen_base);
  1175. pci_release_regions(dev);
  1176. /* pci_disable_device(dev); */
  1177. framebuffer_release(info);
  1178. }
  1179. }
  1180. /* PCI suspend */
  1181. static int __maybe_unused s3_pci_suspend(struct device *dev)
  1182. {
  1183. struct fb_info *info = dev_get_drvdata(dev);
  1184. struct s3fb_info *par = info->par;
  1185. dev_info(info->device, "suspend\n");
  1186. console_lock();
  1187. mutex_lock(&(par->open_lock));
  1188. if (par->ref_count == 0) {
  1189. mutex_unlock(&(par->open_lock));
  1190. console_unlock();
  1191. return 0;
  1192. }
  1193. fb_set_suspend(info, 1);
  1194. mutex_unlock(&(par->open_lock));
  1195. console_unlock();
  1196. return 0;
  1197. }
  1198. /* PCI resume */
  1199. static int __maybe_unused s3_pci_resume(struct device *dev)
  1200. {
  1201. struct fb_info *info = dev_get_drvdata(dev);
  1202. struct s3fb_info *par = info->par;
  1203. dev_info(info->device, "resume\n");
  1204. console_lock();
  1205. mutex_lock(&(par->open_lock));
  1206. if (par->ref_count == 0) {
  1207. mutex_unlock(&(par->open_lock));
  1208. console_unlock();
  1209. return 0;
  1210. }
  1211. s3fb_set_par(info);
  1212. fb_set_suspend(info, 0);
  1213. mutex_unlock(&(par->open_lock));
  1214. console_unlock();
  1215. return 0;
  1216. }
  1217. static const struct dev_pm_ops s3_pci_pm_ops = {
  1218. #ifdef CONFIG_PM_SLEEP
  1219. .suspend = s3_pci_suspend,
  1220. .resume = s3_pci_resume,
  1221. .freeze = NULL,
  1222. .thaw = s3_pci_resume,
  1223. .poweroff = s3_pci_suspend,
  1224. .restore = s3_pci_resume,
  1225. #endif
  1226. };
  1227. /* List of boards that we are trying to support */
  1228. static const struct pci_device_id s3_devices[] = {
  1229. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
  1230. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
  1231. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
  1232. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
  1233. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
  1234. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
  1235. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
  1236. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
  1237. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
  1238. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
  1239. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
  1240. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
  1241. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
  1242. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
  1243. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
  1244. {0, 0, 0, 0, 0, 0, 0}
  1245. };
  1246. MODULE_DEVICE_TABLE(pci, s3_devices);
  1247. static struct pci_driver s3fb_pci_driver = {
  1248. .name = "s3fb",
  1249. .id_table = s3_devices,
  1250. .probe = s3_pci_probe,
  1251. .remove = s3_pci_remove,
  1252. .driver.pm = &s3_pci_pm_ops,
  1253. };
  1254. /* Parse user specified options */
  1255. #ifndef MODULE
  1256. static int __init s3fb_setup(char *options)
  1257. {
  1258. char *opt;
  1259. if (!options || !*options)
  1260. return 0;
  1261. while ((opt = strsep(&options, ",")) != NULL) {
  1262. if (!*opt)
  1263. continue;
  1264. else if (!strncmp(opt, "mtrr:", 5))
  1265. mtrr = simple_strtoul(opt + 5, NULL, 0);
  1266. else if (!strncmp(opt, "fasttext:", 9))
  1267. fasttext = simple_strtoul(opt + 9, NULL, 0);
  1268. else
  1269. mode_option = opt;
  1270. }
  1271. return 0;
  1272. }
  1273. #endif
  1274. /* Cleanup */
  1275. static void __exit s3fb_cleanup(void)
  1276. {
  1277. pr_debug("s3fb: cleaning up\n");
  1278. pci_unregister_driver(&s3fb_pci_driver);
  1279. }
  1280. /* Driver Initialisation */
  1281. static int __init s3fb_init(void)
  1282. {
  1283. #ifndef MODULE
  1284. char *option = NULL;
  1285. if (fb_get_options("s3fb", &option))
  1286. return -ENODEV;
  1287. s3fb_setup(option);
  1288. #endif
  1289. pr_debug("s3fb: initializing\n");
  1290. return pci_register_driver(&s3fb_pci_driver);
  1291. }
  1292. /* ------------------------------------------------------------------------- */
  1293. /* Modularization */
  1294. module_init(s3fb_init);
  1295. module_exit(s3fb_cleanup);