s3c-fb.c 46 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* linux/drivers/video/s3c-fb.c
  3. *
  4. * Copyright 2008 Openmoko Inc.
  5. * Copyright 2008-2010 Simtec Electronics
  6. * Ben Dooks <ben@simtec.co.uk>
  7. * http://armlinux.simtec.co.uk/
  8. *
  9. * Samsung SoC Framebuffer driver
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/slab.h>
  16. #include <linux/init.h>
  17. #include <linux/clk.h>
  18. #include <linux/fb.h>
  19. #include <linux/io.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_data/video_s3c.h>
  24. #include <video/samsung_fimd.h>
  25. /* This driver will export a number of framebuffer interfaces depending
  26. * on the configuration passed in via the platform data. Each fb instance
  27. * maps to a hardware window. Currently there is no support for runtime
  28. * setting of the alpha-blending functions that each window has, so only
  29. * window 0 is actually useful.
  30. *
  31. * Window 0 is treated specially, it is used for the basis of the LCD
  32. * output timings and as the control for the output power-down state.
  33. */
  34. /* note, the previous use of <mach/regs-fb.h> to get platform specific data
  35. * has been replaced by using the platform device name to pick the correct
  36. * configuration data for the system.
  37. */
  38. #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
  39. #undef writel
  40. #define writel(v, r) do { \
  41. pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
  42. __raw_writel(v, r); \
  43. } while (0)
  44. #endif /* FB_S3C_DEBUG_REGWRITE */
  45. /* irq_flags bits */
  46. #define S3C_FB_VSYNC_IRQ_EN 0
  47. #define VSYNC_TIMEOUT_MSEC 50
  48. struct s3c_fb;
  49. #define VALID_BPP(x) (1 << ((x) - 1))
  50. #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
  51. #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
  52. #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
  53. #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
  54. #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
  55. /**
  56. * struct s3c_fb_variant - fb variant information
  57. * @is_2443: Set if S3C2443/S3C2416 style hardware.
  58. * @nr_windows: The number of windows.
  59. * @vidtcon: The base for the VIDTCONx registers
  60. * @wincon: The base for the WINxCON registers.
  61. * @winmap: The base for the WINxMAP registers.
  62. * @keycon: The abse for the WxKEYCON registers.
  63. * @buf_start: Offset of buffer start registers.
  64. * @buf_size: Offset of buffer size registers.
  65. * @buf_end: Offset of buffer end registers.
  66. * @osd: The base for the OSD registers.
  67. * @palette: Address of palette memory, or 0 if none.
  68. * @has_prtcon: Set if has PRTCON register.
  69. * @has_shadowcon: Set if has SHADOWCON register.
  70. * @has_blendcon: Set if has BLENDCON register.
  71. * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
  72. * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
  73. */
  74. struct s3c_fb_variant {
  75. unsigned int is_2443:1;
  76. unsigned short nr_windows;
  77. unsigned int vidtcon;
  78. unsigned short wincon;
  79. unsigned short winmap;
  80. unsigned short keycon;
  81. unsigned short buf_start;
  82. unsigned short buf_end;
  83. unsigned short buf_size;
  84. unsigned short osd;
  85. unsigned short osd_stride;
  86. unsigned short palette[S3C_FB_MAX_WIN];
  87. unsigned int has_prtcon:1;
  88. unsigned int has_shadowcon:1;
  89. unsigned int has_blendcon:1;
  90. unsigned int has_clksel:1;
  91. unsigned int has_fixvclk:1;
  92. };
  93. /**
  94. * struct s3c_fb_win_variant
  95. * @has_osd_c: Set if has OSD C register.
  96. * @has_osd_d: Set if has OSD D register.
  97. * @has_osd_alpha: Set if can change alpha transparency for a window.
  98. * @palette_sz: Size of palette in entries.
  99. * @palette_16bpp: Set if palette is 16bits wide.
  100. * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
  101. * register is located at the given offset from OSD_BASE.
  102. * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
  103. *
  104. * valid_bpp bit x is set if (x+1)BPP is supported.
  105. */
  106. struct s3c_fb_win_variant {
  107. unsigned int has_osd_c:1;
  108. unsigned int has_osd_d:1;
  109. unsigned int has_osd_alpha:1;
  110. unsigned int palette_16bpp:1;
  111. unsigned short osd_size_off;
  112. unsigned short palette_sz;
  113. u32 valid_bpp;
  114. };
  115. /**
  116. * struct s3c_fb_driverdata - per-device type driver data for init time.
  117. * @variant: The variant information for this driver.
  118. * @win: The window information for each window.
  119. */
  120. struct s3c_fb_driverdata {
  121. struct s3c_fb_variant variant;
  122. struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
  123. };
  124. /**
  125. * struct s3c_fb_palette - palette information
  126. * @r: Red bitfield.
  127. * @g: Green bitfield.
  128. * @b: Blue bitfield.
  129. * @a: Alpha bitfield.
  130. */
  131. struct s3c_fb_palette {
  132. struct fb_bitfield r;
  133. struct fb_bitfield g;
  134. struct fb_bitfield b;
  135. struct fb_bitfield a;
  136. };
  137. /**
  138. * struct s3c_fb_win - per window private data for each framebuffer.
  139. * @windata: The platform data supplied for the window configuration.
  140. * @parent: The hardware that this window is part of.
  141. * @fbinfo: Pointer pack to the framebuffer info for this window.
  142. * @varint: The variant information for this window.
  143. * @palette_buffer: Buffer/cache to hold palette entries.
  144. * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
  145. * @index: The window number of this window.
  146. * @palette: The bitfields for changing r/g/b into a hardware palette entry.
  147. */
  148. struct s3c_fb_win {
  149. struct s3c_fb_pd_win *windata;
  150. struct s3c_fb *parent;
  151. struct fb_info *fbinfo;
  152. struct s3c_fb_palette palette;
  153. struct s3c_fb_win_variant variant;
  154. u32 *palette_buffer;
  155. u32 pseudo_palette[16];
  156. unsigned int index;
  157. };
  158. /**
  159. * struct s3c_fb_vsync - vsync information
  160. * @wait: a queue for processes waiting for vsync
  161. * @count: vsync interrupt count
  162. */
  163. struct s3c_fb_vsync {
  164. wait_queue_head_t wait;
  165. unsigned int count;
  166. };
  167. /**
  168. * struct s3c_fb - overall hardware state of the hardware
  169. * @slock: The spinlock protection for this data structure.
  170. * @dev: The device that we bound to, for printing, etc.
  171. * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
  172. * @lcd_clk: The clk (sclk) feeding pixclk.
  173. * @regs: The mapped hardware registers.
  174. * @variant: Variant information for this hardware.
  175. * @enabled: A bitmask of enabled hardware windows.
  176. * @output_on: Flag if the physical output is enabled.
  177. * @pdata: The platform configuration data passed with the device.
  178. * @windows: The hardware windows that have been claimed.
  179. * @irq_no: IRQ line number
  180. * @irq_flags: irq flags
  181. * @vsync_info: VSYNC-related information (count, queues...)
  182. */
  183. struct s3c_fb {
  184. spinlock_t slock;
  185. struct device *dev;
  186. struct clk *bus_clk;
  187. struct clk *lcd_clk;
  188. void __iomem *regs;
  189. struct s3c_fb_variant variant;
  190. unsigned char enabled;
  191. bool output_on;
  192. struct s3c_fb_platdata *pdata;
  193. struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
  194. int irq_no;
  195. unsigned long irq_flags;
  196. struct s3c_fb_vsync vsync_info;
  197. };
  198. /**
  199. * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
  200. * @win: The device window.
  201. * @bpp: The bit depth.
  202. */
  203. static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
  204. {
  205. return win->variant.valid_bpp & VALID_BPP(bpp);
  206. }
  207. /**
  208. * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
  209. * @var: The screen information to verify.
  210. * @info: The framebuffer device.
  211. *
  212. * Framebuffer layer call to verify the given information and allow us to
  213. * update various information depending on the hardware capabilities.
  214. */
  215. static int s3c_fb_check_var(struct fb_var_screeninfo *var,
  216. struct fb_info *info)
  217. {
  218. struct s3c_fb_win *win = info->par;
  219. struct s3c_fb *sfb = win->parent;
  220. dev_dbg(sfb->dev, "checking parameters\n");
  221. var->xres_virtual = max(var->xres_virtual, var->xres);
  222. var->yres_virtual = max(var->yres_virtual, var->yres);
  223. if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
  224. dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
  225. win->index, var->bits_per_pixel);
  226. return -EINVAL;
  227. }
  228. /* always ensure these are zero, for drop through cases below */
  229. var->transp.offset = 0;
  230. var->transp.length = 0;
  231. switch (var->bits_per_pixel) {
  232. case 1:
  233. case 2:
  234. case 4:
  235. case 8:
  236. if (sfb->variant.palette[win->index] != 0) {
  237. /* non palletised, A:1,R:2,G:3,B:2 mode */
  238. var->red.offset = 5;
  239. var->green.offset = 2;
  240. var->blue.offset = 0;
  241. var->red.length = 2;
  242. var->green.length = 3;
  243. var->blue.length = 2;
  244. var->transp.offset = 7;
  245. var->transp.length = 1;
  246. } else {
  247. var->red.offset = 0;
  248. var->red.length = var->bits_per_pixel;
  249. var->green = var->red;
  250. var->blue = var->red;
  251. }
  252. break;
  253. case 19:
  254. /* 666 with one bit alpha/transparency */
  255. var->transp.offset = 18;
  256. var->transp.length = 1;
  257. fallthrough;
  258. case 18:
  259. var->bits_per_pixel = 32;
  260. /* 666 format */
  261. var->red.offset = 12;
  262. var->green.offset = 6;
  263. var->blue.offset = 0;
  264. var->red.length = 6;
  265. var->green.length = 6;
  266. var->blue.length = 6;
  267. break;
  268. case 16:
  269. /* 16 bpp, 565 format */
  270. var->red.offset = 11;
  271. var->green.offset = 5;
  272. var->blue.offset = 0;
  273. var->red.length = 5;
  274. var->green.length = 6;
  275. var->blue.length = 5;
  276. break;
  277. case 32:
  278. case 28:
  279. case 25:
  280. var->transp.length = var->bits_per_pixel - 24;
  281. var->transp.offset = 24;
  282. fallthrough;
  283. case 24:
  284. /* our 24bpp is unpacked, so 32bpp */
  285. var->bits_per_pixel = 32;
  286. var->red.offset = 16;
  287. var->red.length = 8;
  288. var->green.offset = 8;
  289. var->green.length = 8;
  290. var->blue.offset = 0;
  291. var->blue.length = 8;
  292. break;
  293. default:
  294. dev_err(sfb->dev, "invalid bpp\n");
  295. return -EINVAL;
  296. }
  297. dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
  298. return 0;
  299. }
  300. /**
  301. * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
  302. * @sfb: The hardware state.
  303. * @pixclock: The pixel clock wanted, in picoseconds.
  304. *
  305. * Given the specified pixel clock, work out the necessary divider to get
  306. * close to the output frequency.
  307. */
  308. static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
  309. {
  310. unsigned long clk;
  311. unsigned long long tmp;
  312. unsigned int result;
  313. if (sfb->variant.has_clksel)
  314. clk = clk_get_rate(sfb->bus_clk);
  315. else
  316. clk = clk_get_rate(sfb->lcd_clk);
  317. tmp = (unsigned long long)clk;
  318. tmp *= pixclk;
  319. do_div(tmp, 1000000000UL);
  320. result = (unsigned int)tmp / 1000;
  321. dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
  322. pixclk, clk, result, result ? clk / result : clk);
  323. return result;
  324. }
  325. /**
  326. * s3c_fb_align_word() - align pixel count to word boundary
  327. * @bpp: The number of bits per pixel
  328. * @pix: The value to be aligned.
  329. *
  330. * Align the given pixel count so that it will start on an 32bit word
  331. * boundary.
  332. */
  333. static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
  334. {
  335. int pix_per_word;
  336. if (bpp > 16)
  337. return pix;
  338. pix_per_word = (8 * 32) / bpp;
  339. return ALIGN(pix, pix_per_word);
  340. }
  341. /**
  342. * vidosd_set_size() - set OSD size for a window
  343. *
  344. * @win: the window to set OSD size for
  345. * @size: OSD size register value
  346. */
  347. static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
  348. {
  349. struct s3c_fb *sfb = win->parent;
  350. /* OSD can be set up if osd_size_off != 0 for this window */
  351. if (win->variant.osd_size_off)
  352. writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
  353. + win->variant.osd_size_off);
  354. }
  355. /**
  356. * vidosd_set_alpha() - set alpha transparency for a window
  357. *
  358. * @win: the window to set OSD size for
  359. * @alpha: alpha register value
  360. */
  361. static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
  362. {
  363. struct s3c_fb *sfb = win->parent;
  364. if (win->variant.has_osd_alpha)
  365. writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
  366. }
  367. /**
  368. * shadow_protect_win() - disable updating values from shadow registers at vsync
  369. *
  370. * @win: window to protect registers for
  371. * @protect: 1 to protect (disable updates)
  372. */
  373. static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
  374. {
  375. struct s3c_fb *sfb = win->parent;
  376. u32 reg;
  377. if (protect) {
  378. if (sfb->variant.has_prtcon) {
  379. writel(PRTCON_PROTECT, sfb->regs + PRTCON);
  380. } else if (sfb->variant.has_shadowcon) {
  381. reg = readl(sfb->regs + SHADOWCON);
  382. writel(reg | SHADOWCON_WINx_PROTECT(win->index),
  383. sfb->regs + SHADOWCON);
  384. }
  385. } else {
  386. if (sfb->variant.has_prtcon) {
  387. writel(0, sfb->regs + PRTCON);
  388. } else if (sfb->variant.has_shadowcon) {
  389. reg = readl(sfb->regs + SHADOWCON);
  390. writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
  391. sfb->regs + SHADOWCON);
  392. }
  393. }
  394. }
  395. /**
  396. * s3c_fb_enable() - Set the state of the main LCD output
  397. * @sfb: The main framebuffer state.
  398. * @enable: The state to set.
  399. */
  400. static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
  401. {
  402. u32 vidcon0 = readl(sfb->regs + VIDCON0);
  403. if (enable && !sfb->output_on)
  404. pm_runtime_get_sync(sfb->dev);
  405. if (enable) {
  406. vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
  407. } else {
  408. /* see the note in the framebuffer datasheet about
  409. * why you cannot take both of these bits down at the
  410. * same time. */
  411. if (vidcon0 & VIDCON0_ENVID) {
  412. vidcon0 |= VIDCON0_ENVID;
  413. vidcon0 &= ~VIDCON0_ENVID_F;
  414. }
  415. }
  416. writel(vidcon0, sfb->regs + VIDCON0);
  417. if (!enable && sfb->output_on)
  418. pm_runtime_put_sync(sfb->dev);
  419. sfb->output_on = enable;
  420. }
  421. /**
  422. * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
  423. * @info: The framebuffer to change.
  424. *
  425. * Framebuffer layer request to set a new mode for the specified framebuffer
  426. */
  427. static int s3c_fb_set_par(struct fb_info *info)
  428. {
  429. struct fb_var_screeninfo *var = &info->var;
  430. struct s3c_fb_win *win = info->par;
  431. struct s3c_fb *sfb = win->parent;
  432. void __iomem *regs = sfb->regs;
  433. void __iomem *buf = regs;
  434. int win_no = win->index;
  435. u32 alpha = 0;
  436. u32 data;
  437. u32 pagewidth;
  438. dev_dbg(sfb->dev, "setting framebuffer parameters\n");
  439. pm_runtime_get_sync(sfb->dev);
  440. shadow_protect_win(win, 1);
  441. switch (var->bits_per_pixel) {
  442. case 32:
  443. case 24:
  444. case 16:
  445. case 12:
  446. info->fix.visual = FB_VISUAL_TRUECOLOR;
  447. break;
  448. case 8:
  449. if (win->variant.palette_sz >= 256)
  450. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  451. else
  452. info->fix.visual = FB_VISUAL_TRUECOLOR;
  453. break;
  454. case 1:
  455. info->fix.visual = FB_VISUAL_MONO01;
  456. break;
  457. default:
  458. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  459. break;
  460. }
  461. info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
  462. info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
  463. info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
  464. /* disable the window whilst we update it */
  465. writel(0, regs + WINCON(win_no));
  466. if (!sfb->output_on)
  467. s3c_fb_enable(sfb, 1);
  468. /* write the buffer address */
  469. /* start and end registers stride is 8 */
  470. buf = regs + win_no * 8;
  471. writel(info->fix.smem_start, buf + sfb->variant.buf_start);
  472. data = info->fix.smem_start + info->fix.line_length * var->yres;
  473. writel(data, buf + sfb->variant.buf_end);
  474. pagewidth = (var->xres * var->bits_per_pixel) >> 3;
  475. data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
  476. VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |
  477. VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |
  478. VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);
  479. writel(data, regs + sfb->variant.buf_size + (win_no * 4));
  480. /* write 'OSD' registers to control position of framebuffer */
  481. data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
  482. VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);
  483. writel(data, regs + VIDOSD_A(win_no, sfb->variant));
  484. data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
  485. var->xres - 1)) |
  486. VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |
  487. VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,
  488. var->xres - 1)) |
  489. VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);
  490. writel(data, regs + VIDOSD_B(win_no, sfb->variant));
  491. data = var->xres * var->yres;
  492. alpha = VIDISD14C_ALPHA1_R(0xf) |
  493. VIDISD14C_ALPHA1_G(0xf) |
  494. VIDISD14C_ALPHA1_B(0xf);
  495. vidosd_set_alpha(win, alpha);
  496. vidosd_set_size(win, data);
  497. /* Enable DMA channel for this window */
  498. if (sfb->variant.has_shadowcon) {
  499. data = readl(sfb->regs + SHADOWCON);
  500. data |= SHADOWCON_CHx_ENABLE(win_no);
  501. writel(data, sfb->regs + SHADOWCON);
  502. }
  503. data = WINCONx_ENWIN;
  504. sfb->enabled |= (1 << win->index);
  505. /* note, since we have to round up the bits-per-pixel, we end up
  506. * relying on the bitfield information for r/g/b/a to work out
  507. * exactly which mode of operation is intended. */
  508. switch (var->bits_per_pixel) {
  509. case 1:
  510. data |= WINCON0_BPPMODE_1BPP;
  511. data |= WINCONx_BITSWP;
  512. data |= WINCONx_BURSTLEN_4WORD;
  513. break;
  514. case 2:
  515. data |= WINCON0_BPPMODE_2BPP;
  516. data |= WINCONx_BITSWP;
  517. data |= WINCONx_BURSTLEN_8WORD;
  518. break;
  519. case 4:
  520. data |= WINCON0_BPPMODE_4BPP;
  521. data |= WINCONx_BITSWP;
  522. data |= WINCONx_BURSTLEN_8WORD;
  523. break;
  524. case 8:
  525. if (var->transp.length != 0)
  526. data |= WINCON1_BPPMODE_8BPP_1232;
  527. else
  528. data |= WINCON0_BPPMODE_8BPP_PALETTE;
  529. data |= WINCONx_BURSTLEN_8WORD;
  530. data |= WINCONx_BYTSWP;
  531. break;
  532. case 16:
  533. if (var->transp.length != 0)
  534. data |= WINCON1_BPPMODE_16BPP_A1555;
  535. else
  536. data |= WINCON0_BPPMODE_16BPP_565;
  537. data |= WINCONx_HAWSWP;
  538. data |= WINCONx_BURSTLEN_16WORD;
  539. break;
  540. case 24:
  541. case 32:
  542. if (var->red.length == 6) {
  543. if (var->transp.length != 0)
  544. data |= WINCON1_BPPMODE_19BPP_A1666;
  545. else
  546. data |= WINCON1_BPPMODE_18BPP_666;
  547. } else if (var->transp.length == 1)
  548. data |= WINCON1_BPPMODE_25BPP_A1888
  549. | WINCON1_BLD_PIX;
  550. else if ((var->transp.length == 4) ||
  551. (var->transp.length == 8))
  552. data |= WINCON1_BPPMODE_28BPP_A4888
  553. | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
  554. else
  555. data |= WINCON0_BPPMODE_24BPP_888;
  556. data |= WINCONx_WSWP;
  557. data |= WINCONx_BURSTLEN_16WORD;
  558. break;
  559. }
  560. /* Enable the colour keying for the window below this one */
  561. if (win_no > 0) {
  562. u32 keycon0_data = 0, keycon1_data = 0;
  563. void __iomem *keycon = regs + sfb->variant.keycon;
  564. keycon0_data = ~(WxKEYCON0_KEYBL_EN |
  565. WxKEYCON0_KEYEN_F |
  566. WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
  567. keycon1_data = WxKEYCON1_COLVAL(0xffffff);
  568. keycon += (win_no - 1) * 8;
  569. writel(keycon0_data, keycon + WKEYCON0);
  570. writel(keycon1_data, keycon + WKEYCON1);
  571. }
  572. writel(data, regs + sfb->variant.wincon + (win_no * 4));
  573. writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
  574. /* Set alpha value width */
  575. if (sfb->variant.has_blendcon) {
  576. data = readl(sfb->regs + BLENDCON);
  577. data &= ~BLENDCON_NEW_MASK;
  578. if (var->transp.length > 4)
  579. data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;
  580. else
  581. data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;
  582. writel(data, sfb->regs + BLENDCON);
  583. }
  584. shadow_protect_win(win, 0);
  585. pm_runtime_put_sync(sfb->dev);
  586. return 0;
  587. }
  588. /**
  589. * s3c_fb_update_palette() - set or schedule a palette update.
  590. * @sfb: The hardware information.
  591. * @win: The window being updated.
  592. * @reg: The palette index being changed.
  593. * @value: The computed palette value.
  594. *
  595. * Change the value of a palette register, either by directly writing to
  596. * the palette (this requires the palette RAM to be disconnected from the
  597. * hardware whilst this is in progress) or schedule the update for later.
  598. *
  599. * At the moment, since we have no VSYNC interrupt support, we simply set
  600. * the palette entry directly.
  601. */
  602. static void s3c_fb_update_palette(struct s3c_fb *sfb,
  603. struct s3c_fb_win *win,
  604. unsigned int reg,
  605. u32 value)
  606. {
  607. void __iomem *palreg;
  608. u32 palcon;
  609. palreg = sfb->regs + sfb->variant.palette[win->index];
  610. dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
  611. __func__, win->index, reg, palreg, value);
  612. win->palette_buffer[reg] = value;
  613. palcon = readl(sfb->regs + WPALCON);
  614. writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
  615. if (win->variant.palette_16bpp)
  616. writew(value, palreg + (reg * 2));
  617. else
  618. writel(value, palreg + (reg * 4));
  619. writel(palcon, sfb->regs + WPALCON);
  620. }
  621. static inline unsigned int chan_to_field(unsigned int chan,
  622. struct fb_bitfield *bf)
  623. {
  624. chan &= 0xffff;
  625. chan >>= 16 - bf->length;
  626. return chan << bf->offset;
  627. }
  628. /**
  629. * s3c_fb_setcolreg() - framebuffer layer request to change palette.
  630. * @regno: The palette index to change.
  631. * @red: The red field for the palette data.
  632. * @green: The green field for the palette data.
  633. * @blue: The blue field for the palette data.
  634. * @trans: The transparency (alpha) field for the palette data.
  635. * @info: The framebuffer being changed.
  636. */
  637. static int s3c_fb_setcolreg(unsigned regno,
  638. unsigned red, unsigned green, unsigned blue,
  639. unsigned transp, struct fb_info *info)
  640. {
  641. struct s3c_fb_win *win = info->par;
  642. struct s3c_fb *sfb = win->parent;
  643. unsigned int val;
  644. dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
  645. __func__, win->index, regno, red, green, blue);
  646. pm_runtime_get_sync(sfb->dev);
  647. switch (info->fix.visual) {
  648. case FB_VISUAL_TRUECOLOR:
  649. /* true-colour, use pseudo-palette */
  650. if (regno < 16) {
  651. u32 *pal = info->pseudo_palette;
  652. val = chan_to_field(red, &info->var.red);
  653. val |= chan_to_field(green, &info->var.green);
  654. val |= chan_to_field(blue, &info->var.blue);
  655. pal[regno] = val;
  656. }
  657. break;
  658. case FB_VISUAL_PSEUDOCOLOR:
  659. if (regno < win->variant.palette_sz) {
  660. val = chan_to_field(red, &win->palette.r);
  661. val |= chan_to_field(green, &win->palette.g);
  662. val |= chan_to_field(blue, &win->palette.b);
  663. s3c_fb_update_palette(sfb, win, regno, val);
  664. }
  665. break;
  666. default:
  667. pm_runtime_put_sync(sfb->dev);
  668. return 1; /* unknown type */
  669. }
  670. pm_runtime_put_sync(sfb->dev);
  671. return 0;
  672. }
  673. /**
  674. * s3c_fb_blank() - blank or unblank the given window
  675. * @blank_mode: The blank state from FB_BLANK_*
  676. * @info: The framebuffer to blank.
  677. *
  678. * Framebuffer layer request to change the power state.
  679. */
  680. static int s3c_fb_blank(int blank_mode, struct fb_info *info)
  681. {
  682. struct s3c_fb_win *win = info->par;
  683. struct s3c_fb *sfb = win->parent;
  684. unsigned int index = win->index;
  685. u32 wincon;
  686. u32 output_on = sfb->output_on;
  687. dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
  688. pm_runtime_get_sync(sfb->dev);
  689. wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
  690. switch (blank_mode) {
  691. case FB_BLANK_POWERDOWN:
  692. wincon &= ~WINCONx_ENWIN;
  693. sfb->enabled &= ~(1 << index);
  694. fallthrough; /* to FB_BLANK_NORMAL */
  695. case FB_BLANK_NORMAL:
  696. /* disable the DMA and display 0x0 (black) */
  697. shadow_protect_win(win, 1);
  698. writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
  699. sfb->regs + sfb->variant.winmap + (index * 4));
  700. shadow_protect_win(win, 0);
  701. break;
  702. case FB_BLANK_UNBLANK:
  703. shadow_protect_win(win, 1);
  704. writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
  705. shadow_protect_win(win, 0);
  706. wincon |= WINCONx_ENWIN;
  707. sfb->enabled |= (1 << index);
  708. break;
  709. case FB_BLANK_VSYNC_SUSPEND:
  710. case FB_BLANK_HSYNC_SUSPEND:
  711. default:
  712. pm_runtime_put_sync(sfb->dev);
  713. return 1;
  714. }
  715. shadow_protect_win(win, 1);
  716. writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
  717. /* Check the enabled state to see if we need to be running the
  718. * main LCD interface, as if there are no active windows then
  719. * it is highly likely that we also do not need to output
  720. * anything.
  721. */
  722. s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
  723. shadow_protect_win(win, 0);
  724. pm_runtime_put_sync(sfb->dev);
  725. return output_on == sfb->output_on;
  726. }
  727. /**
  728. * s3c_fb_pan_display() - Pan the display.
  729. *
  730. * Note that the offsets can be written to the device at any time, as their
  731. * values are latched at each vsync automatically. This also means that only
  732. * the last call to this function will have any effect on next vsync, but
  733. * there is no need to sleep waiting for it to prevent tearing.
  734. *
  735. * @var: The screen information to verify.
  736. * @info: The framebuffer device.
  737. */
  738. static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
  739. struct fb_info *info)
  740. {
  741. struct s3c_fb_win *win = info->par;
  742. struct s3c_fb *sfb = win->parent;
  743. void __iomem *buf = sfb->regs + win->index * 8;
  744. unsigned int start_boff, end_boff;
  745. pm_runtime_get_sync(sfb->dev);
  746. /* Offset in bytes to the start of the displayed area */
  747. start_boff = var->yoffset * info->fix.line_length;
  748. /* X offset depends on the current bpp */
  749. if (info->var.bits_per_pixel >= 8) {
  750. start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
  751. } else {
  752. switch (info->var.bits_per_pixel) {
  753. case 4:
  754. start_boff += var->xoffset >> 1;
  755. break;
  756. case 2:
  757. start_boff += var->xoffset >> 2;
  758. break;
  759. case 1:
  760. start_boff += var->xoffset >> 3;
  761. break;
  762. default:
  763. dev_err(sfb->dev, "invalid bpp\n");
  764. pm_runtime_put_sync(sfb->dev);
  765. return -EINVAL;
  766. }
  767. }
  768. /* Offset in bytes to the end of the displayed area */
  769. end_boff = start_boff + info->var.yres * info->fix.line_length;
  770. /* Temporarily turn off per-vsync update from shadow registers until
  771. * both start and end addresses are updated to prevent corruption */
  772. shadow_protect_win(win, 1);
  773. writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
  774. writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
  775. shadow_protect_win(win, 0);
  776. pm_runtime_put_sync(sfb->dev);
  777. return 0;
  778. }
  779. /**
  780. * s3c_fb_enable_irq() - enable framebuffer interrupts
  781. * @sfb: main hardware state
  782. */
  783. static void s3c_fb_enable_irq(struct s3c_fb *sfb)
  784. {
  785. void __iomem *regs = sfb->regs;
  786. u32 irq_ctrl_reg;
  787. if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
  788. /* IRQ disabled, enable it */
  789. irq_ctrl_reg = readl(regs + VIDINTCON0);
  790. irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
  791. irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
  792. irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
  793. irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
  794. irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
  795. irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
  796. writel(irq_ctrl_reg, regs + VIDINTCON0);
  797. }
  798. }
  799. /**
  800. * s3c_fb_disable_irq() - disable framebuffer interrupts
  801. * @sfb: main hardware state
  802. */
  803. static void s3c_fb_disable_irq(struct s3c_fb *sfb)
  804. {
  805. void __iomem *regs = sfb->regs;
  806. u32 irq_ctrl_reg;
  807. if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
  808. /* IRQ enabled, disable it */
  809. irq_ctrl_reg = readl(regs + VIDINTCON0);
  810. irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
  811. irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
  812. writel(irq_ctrl_reg, regs + VIDINTCON0);
  813. }
  814. }
  815. static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
  816. {
  817. struct s3c_fb *sfb = dev_id;
  818. void __iomem *regs = sfb->regs;
  819. u32 irq_sts_reg;
  820. spin_lock(&sfb->slock);
  821. irq_sts_reg = readl(regs + VIDINTCON1);
  822. if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
  823. /* VSYNC interrupt, accept it */
  824. writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
  825. sfb->vsync_info.count++;
  826. wake_up_interruptible(&sfb->vsync_info.wait);
  827. }
  828. /* We only support waiting for VSYNC for now, so it's safe
  829. * to always disable irqs here.
  830. */
  831. s3c_fb_disable_irq(sfb);
  832. spin_unlock(&sfb->slock);
  833. return IRQ_HANDLED;
  834. }
  835. /**
  836. * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
  837. * @sfb: main hardware state
  838. * @crtc: head index.
  839. */
  840. static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
  841. {
  842. unsigned long count;
  843. int ret;
  844. if (crtc != 0)
  845. return -ENODEV;
  846. pm_runtime_get_sync(sfb->dev);
  847. count = sfb->vsync_info.count;
  848. s3c_fb_enable_irq(sfb);
  849. ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
  850. count != sfb->vsync_info.count,
  851. msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
  852. pm_runtime_put_sync(sfb->dev);
  853. if (ret == 0)
  854. return -ETIMEDOUT;
  855. return 0;
  856. }
  857. static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
  858. unsigned long arg)
  859. {
  860. struct s3c_fb_win *win = info->par;
  861. struct s3c_fb *sfb = win->parent;
  862. int ret;
  863. u32 crtc;
  864. switch (cmd) {
  865. case FBIO_WAITFORVSYNC:
  866. if (get_user(crtc, (u32 __user *)arg)) {
  867. ret = -EFAULT;
  868. break;
  869. }
  870. ret = s3c_fb_wait_for_vsync(sfb, crtc);
  871. break;
  872. default:
  873. ret = -ENOTTY;
  874. }
  875. return ret;
  876. }
  877. static const struct fb_ops s3c_fb_ops = {
  878. .owner = THIS_MODULE,
  879. .fb_check_var = s3c_fb_check_var,
  880. .fb_set_par = s3c_fb_set_par,
  881. .fb_blank = s3c_fb_blank,
  882. .fb_setcolreg = s3c_fb_setcolreg,
  883. .fb_fillrect = cfb_fillrect,
  884. .fb_copyarea = cfb_copyarea,
  885. .fb_imageblit = cfb_imageblit,
  886. .fb_pan_display = s3c_fb_pan_display,
  887. .fb_ioctl = s3c_fb_ioctl,
  888. };
  889. /**
  890. * s3c_fb_missing_pixclock() - calculates pixel clock
  891. * @mode: The video mode to change.
  892. *
  893. * Calculate the pixel clock when none has been given through platform data.
  894. */
  895. static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
  896. {
  897. u64 pixclk = 1000000000000ULL;
  898. u32 div;
  899. div = mode->left_margin + mode->hsync_len + mode->right_margin +
  900. mode->xres;
  901. div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
  902. mode->yres;
  903. div *= mode->refresh ? : 60;
  904. do_div(pixclk, div);
  905. mode->pixclock = pixclk;
  906. }
  907. /**
  908. * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
  909. * @sfb: The base resources for the hardware.
  910. * @win: The window to initialise memory for.
  911. *
  912. * Allocate memory for the given framebuffer.
  913. */
  914. static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
  915. {
  916. struct s3c_fb_pd_win *windata = win->windata;
  917. unsigned int real_size, virt_size, size;
  918. struct fb_info *fbi = win->fbinfo;
  919. dma_addr_t map_dma;
  920. dev_dbg(sfb->dev, "allocating memory for display\n");
  921. real_size = windata->xres * windata->yres;
  922. virt_size = windata->virtual_x * windata->virtual_y;
  923. dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
  924. real_size, windata->xres, windata->yres,
  925. virt_size, windata->virtual_x, windata->virtual_y);
  926. size = (real_size > virt_size) ? real_size : virt_size;
  927. size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
  928. size /= 8;
  929. fbi->fix.smem_len = size;
  930. size = PAGE_ALIGN(size);
  931. dev_dbg(sfb->dev, "want %u bytes for window\n", size);
  932. fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL);
  933. if (!fbi->screen_buffer)
  934. return -ENOMEM;
  935. dev_dbg(sfb->dev, "mapped %x to %p\n",
  936. (unsigned int)map_dma, fbi->screen_buffer);
  937. memset(fbi->screen_buffer, 0x0, size);
  938. fbi->fix.smem_start = map_dma;
  939. return 0;
  940. }
  941. /**
  942. * s3c_fb_free_memory() - free the display memory for the given window
  943. * @sfb: The base resources for the hardware.
  944. * @win: The window to free the display memory for.
  945. *
  946. * Free the display memory allocated by s3c_fb_alloc_memory().
  947. */
  948. static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
  949. {
  950. struct fb_info *fbi = win->fbinfo;
  951. if (fbi->screen_buffer)
  952. dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
  953. fbi->screen_buffer, fbi->fix.smem_start);
  954. }
  955. /**
  956. * s3c_fb_release_win() - release resources for a framebuffer window.
  957. * @win: The window to cleanup the resources for.
  958. *
  959. * Release the resources that where claimed for the hardware window,
  960. * such as the framebuffer instance and any memory claimed for it.
  961. */
  962. static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
  963. {
  964. u32 data;
  965. if (win->fbinfo) {
  966. if (sfb->variant.has_shadowcon) {
  967. data = readl(sfb->regs + SHADOWCON);
  968. data &= ~SHADOWCON_CHx_ENABLE(win->index);
  969. data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
  970. writel(data, sfb->regs + SHADOWCON);
  971. }
  972. unregister_framebuffer(win->fbinfo);
  973. if (win->fbinfo->cmap.len)
  974. fb_dealloc_cmap(&win->fbinfo->cmap);
  975. s3c_fb_free_memory(sfb, win);
  976. framebuffer_release(win->fbinfo);
  977. }
  978. }
  979. /**
  980. * s3c_fb_probe_win() - register an hardware window
  981. * @sfb: The base resources for the hardware
  982. * @variant: The variant information for this window.
  983. * @res: Pointer to where to place the resultant window.
  984. *
  985. * Allocate and do the basic initialisation for one of the hardware's graphics
  986. * windows.
  987. */
  988. static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
  989. struct s3c_fb_win_variant *variant,
  990. struct s3c_fb_win **res)
  991. {
  992. struct fb_var_screeninfo *var;
  993. struct fb_videomode initmode;
  994. struct s3c_fb_pd_win *windata;
  995. struct s3c_fb_win *win;
  996. struct fb_info *fbinfo;
  997. int palette_size;
  998. int ret;
  999. dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
  1000. init_waitqueue_head(&sfb->vsync_info.wait);
  1001. palette_size = variant->palette_sz * 4;
  1002. fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
  1003. palette_size * sizeof(u32), sfb->dev);
  1004. if (!fbinfo)
  1005. return -ENOMEM;
  1006. windata = sfb->pdata->win[win_no];
  1007. initmode = *sfb->pdata->vtiming;
  1008. WARN_ON(windata->max_bpp == 0);
  1009. WARN_ON(windata->xres == 0);
  1010. WARN_ON(windata->yres == 0);
  1011. win = fbinfo->par;
  1012. *res = win;
  1013. var = &fbinfo->var;
  1014. win->variant = *variant;
  1015. win->fbinfo = fbinfo;
  1016. win->parent = sfb;
  1017. win->windata = windata;
  1018. win->index = win_no;
  1019. win->palette_buffer = (u32 *)(win + 1);
  1020. ret = s3c_fb_alloc_memory(sfb, win);
  1021. if (ret) {
  1022. dev_err(sfb->dev, "failed to allocate display memory\n");
  1023. return ret;
  1024. }
  1025. /* setup the r/b/g positions for the window's palette */
  1026. if (win->variant.palette_16bpp) {
  1027. /* Set RGB 5:6:5 as default */
  1028. win->palette.r.offset = 11;
  1029. win->palette.r.length = 5;
  1030. win->palette.g.offset = 5;
  1031. win->palette.g.length = 6;
  1032. win->palette.b.offset = 0;
  1033. win->palette.b.length = 5;
  1034. } else {
  1035. /* Set 8bpp or 8bpp and 1bit alpha */
  1036. win->palette.r.offset = 16;
  1037. win->palette.r.length = 8;
  1038. win->palette.g.offset = 8;
  1039. win->palette.g.length = 8;
  1040. win->palette.b.offset = 0;
  1041. win->palette.b.length = 8;
  1042. }
  1043. /* setup the initial video mode from the window */
  1044. initmode.xres = windata->xres;
  1045. initmode.yres = windata->yres;
  1046. fb_videomode_to_var(&fbinfo->var, &initmode);
  1047. fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
  1048. fbinfo->fix.accel = FB_ACCEL_NONE;
  1049. fbinfo->var.activate = FB_ACTIVATE_NOW;
  1050. fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
  1051. fbinfo->var.bits_per_pixel = windata->default_bpp;
  1052. fbinfo->fbops = &s3c_fb_ops;
  1053. fbinfo->flags = FBINFO_FLAG_DEFAULT;
  1054. fbinfo->pseudo_palette = &win->pseudo_palette;
  1055. /* prepare to actually start the framebuffer */
  1056. ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
  1057. if (ret < 0) {
  1058. dev_err(sfb->dev, "check_var failed on initial video params\n");
  1059. return ret;
  1060. }
  1061. /* create initial colour map */
  1062. ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
  1063. if (ret == 0)
  1064. fb_set_cmap(&fbinfo->cmap, fbinfo);
  1065. else
  1066. dev_err(sfb->dev, "failed to allocate fb cmap\n");
  1067. s3c_fb_set_par(fbinfo);
  1068. dev_dbg(sfb->dev, "about to register framebuffer\n");
  1069. /* run the check_var and set_par on our configuration. */
  1070. ret = register_framebuffer(fbinfo);
  1071. if (ret < 0) {
  1072. dev_err(sfb->dev, "failed to register framebuffer\n");
  1073. return ret;
  1074. }
  1075. dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
  1076. return 0;
  1077. }
  1078. /**
  1079. * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
  1080. * @sfb: The base resources for the hardware.
  1081. *
  1082. * Set horizontal and vertical lcd rgb interface timing.
  1083. */
  1084. static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
  1085. {
  1086. struct fb_videomode *vmode = sfb->pdata->vtiming;
  1087. void __iomem *regs = sfb->regs;
  1088. int clkdiv;
  1089. u32 data;
  1090. if (!vmode->pixclock)
  1091. s3c_fb_missing_pixclock(vmode);
  1092. clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
  1093. data = sfb->pdata->vidcon0;
  1094. data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
  1095. if (clkdiv > 1)
  1096. data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
  1097. else
  1098. data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
  1099. if (sfb->variant.is_2443)
  1100. data |= (1 << 5);
  1101. writel(data, regs + VIDCON0);
  1102. data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
  1103. VIDTCON0_VFPD(vmode->lower_margin - 1) |
  1104. VIDTCON0_VSPW(vmode->vsync_len - 1);
  1105. writel(data, regs + sfb->variant.vidtcon);
  1106. data = VIDTCON1_HBPD(vmode->left_margin - 1) |
  1107. VIDTCON1_HFPD(vmode->right_margin - 1) |
  1108. VIDTCON1_HSPW(vmode->hsync_len - 1);
  1109. writel(data, regs + sfb->variant.vidtcon + 4);
  1110. data = VIDTCON2_LINEVAL(vmode->yres - 1) |
  1111. VIDTCON2_HOZVAL(vmode->xres - 1) |
  1112. VIDTCON2_LINEVAL_E(vmode->yres - 1) |
  1113. VIDTCON2_HOZVAL_E(vmode->xres - 1);
  1114. writel(data, regs + sfb->variant.vidtcon + 8);
  1115. }
  1116. /**
  1117. * s3c_fb_clear_win() - clear hardware window registers.
  1118. * @sfb: The base resources for the hardware.
  1119. * @win: The window to process.
  1120. *
  1121. * Reset the specific window registers to a known state.
  1122. */
  1123. static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
  1124. {
  1125. void __iomem *regs = sfb->regs;
  1126. u32 reg;
  1127. writel(0, regs + sfb->variant.wincon + (win * 4));
  1128. writel(0, regs + VIDOSD_A(win, sfb->variant));
  1129. writel(0, regs + VIDOSD_B(win, sfb->variant));
  1130. writel(0, regs + VIDOSD_C(win, sfb->variant));
  1131. if (sfb->variant.has_shadowcon) {
  1132. reg = readl(sfb->regs + SHADOWCON);
  1133. reg &= ~(SHADOWCON_WINx_PROTECT(win) |
  1134. SHADOWCON_CHx_ENABLE(win) |
  1135. SHADOWCON_CHx_LOCAL_ENABLE(win));
  1136. writel(reg, sfb->regs + SHADOWCON);
  1137. }
  1138. }
  1139. static int s3c_fb_probe(struct platform_device *pdev)
  1140. {
  1141. const struct platform_device_id *platid;
  1142. struct s3c_fb_driverdata *fbdrv;
  1143. struct device *dev = &pdev->dev;
  1144. struct s3c_fb_platdata *pd;
  1145. struct s3c_fb *sfb;
  1146. struct resource *res;
  1147. int win;
  1148. int ret = 0;
  1149. u32 reg;
  1150. platid = platform_get_device_id(pdev);
  1151. fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
  1152. if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
  1153. dev_err(dev, "too many windows, cannot attach\n");
  1154. return -EINVAL;
  1155. }
  1156. pd = dev_get_platdata(&pdev->dev);
  1157. if (!pd) {
  1158. dev_err(dev, "no platform data specified\n");
  1159. return -EINVAL;
  1160. }
  1161. sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL);
  1162. if (!sfb)
  1163. return -ENOMEM;
  1164. dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
  1165. sfb->dev = dev;
  1166. sfb->pdata = pd;
  1167. sfb->variant = fbdrv->variant;
  1168. spin_lock_init(&sfb->slock);
  1169. sfb->bus_clk = devm_clk_get(dev, "lcd");
  1170. if (IS_ERR(sfb->bus_clk)) {
  1171. dev_err(dev, "failed to get bus clock\n");
  1172. return PTR_ERR(sfb->bus_clk);
  1173. }
  1174. clk_prepare_enable(sfb->bus_clk);
  1175. if (!sfb->variant.has_clksel) {
  1176. sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
  1177. if (IS_ERR(sfb->lcd_clk)) {
  1178. dev_err(dev, "failed to get lcd clock\n");
  1179. ret = PTR_ERR(sfb->lcd_clk);
  1180. goto err_bus_clk;
  1181. }
  1182. clk_prepare_enable(sfb->lcd_clk);
  1183. }
  1184. pm_runtime_enable(sfb->dev);
  1185. sfb->regs = devm_platform_ioremap_resource(pdev, 0);
  1186. if (IS_ERR(sfb->regs)) {
  1187. ret = PTR_ERR(sfb->regs);
  1188. goto err_lcd_clk;
  1189. }
  1190. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1191. if (!res) {
  1192. dev_err(dev, "failed to acquire irq resource\n");
  1193. ret = -ENOENT;
  1194. goto err_lcd_clk;
  1195. }
  1196. sfb->irq_no = res->start;
  1197. ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
  1198. 0, "s3c_fb", sfb);
  1199. if (ret) {
  1200. dev_err(dev, "irq request failed\n");
  1201. goto err_lcd_clk;
  1202. }
  1203. dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
  1204. platform_set_drvdata(pdev, sfb);
  1205. pm_runtime_get_sync(sfb->dev);
  1206. /* setup gpio and output polarity controls */
  1207. pd->setup_gpio();
  1208. writel(pd->vidcon1, sfb->regs + VIDCON1);
  1209. /* set video clock running at under-run */
  1210. if (sfb->variant.has_fixvclk) {
  1211. reg = readl(sfb->regs + VIDCON1);
  1212. reg &= ~VIDCON1_VCLK_MASK;
  1213. reg |= VIDCON1_VCLK_RUN;
  1214. writel(reg, sfb->regs + VIDCON1);
  1215. }
  1216. /* zero all windows before we do anything */
  1217. for (win = 0; win < fbdrv->variant.nr_windows; win++)
  1218. s3c_fb_clear_win(sfb, win);
  1219. /* initialise colour key controls */
  1220. for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
  1221. void __iomem *regs = sfb->regs + sfb->variant.keycon;
  1222. regs += (win * 8);
  1223. writel(0xffffff, regs + WKEYCON0);
  1224. writel(0xffffff, regs + WKEYCON1);
  1225. }
  1226. s3c_fb_set_rgb_timing(sfb);
  1227. /* we have the register setup, start allocating framebuffers */
  1228. for (win = 0; win < fbdrv->variant.nr_windows; win++) {
  1229. if (!pd->win[win])
  1230. continue;
  1231. ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
  1232. &sfb->windows[win]);
  1233. if (ret < 0) {
  1234. dev_err(dev, "failed to create window %d\n", win);
  1235. for (; win >= 0; win--)
  1236. s3c_fb_release_win(sfb, sfb->windows[win]);
  1237. goto err_pm_runtime;
  1238. }
  1239. }
  1240. platform_set_drvdata(pdev, sfb);
  1241. pm_runtime_put_sync(sfb->dev);
  1242. return 0;
  1243. err_pm_runtime:
  1244. pm_runtime_put_sync(sfb->dev);
  1245. err_lcd_clk:
  1246. pm_runtime_disable(sfb->dev);
  1247. if (!sfb->variant.has_clksel)
  1248. clk_disable_unprepare(sfb->lcd_clk);
  1249. err_bus_clk:
  1250. clk_disable_unprepare(sfb->bus_clk);
  1251. return ret;
  1252. }
  1253. /**
  1254. * s3c_fb_remove() - Cleanup on module finalisation
  1255. * @pdev: The platform device we are bound to.
  1256. *
  1257. * Shutdown and then release all the resources that the driver allocated
  1258. * on initialisation.
  1259. */
  1260. static int s3c_fb_remove(struct platform_device *pdev)
  1261. {
  1262. struct s3c_fb *sfb = platform_get_drvdata(pdev);
  1263. int win;
  1264. pm_runtime_get_sync(sfb->dev);
  1265. for (win = 0; win < S3C_FB_MAX_WIN; win++)
  1266. if (sfb->windows[win])
  1267. s3c_fb_release_win(sfb, sfb->windows[win]);
  1268. if (!sfb->variant.has_clksel)
  1269. clk_disable_unprepare(sfb->lcd_clk);
  1270. clk_disable_unprepare(sfb->bus_clk);
  1271. pm_runtime_put_sync(sfb->dev);
  1272. pm_runtime_disable(sfb->dev);
  1273. return 0;
  1274. }
  1275. #ifdef CONFIG_PM_SLEEP
  1276. static int s3c_fb_suspend(struct device *dev)
  1277. {
  1278. struct s3c_fb *sfb = dev_get_drvdata(dev);
  1279. struct s3c_fb_win *win;
  1280. int win_no;
  1281. pm_runtime_get_sync(sfb->dev);
  1282. for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
  1283. win = sfb->windows[win_no];
  1284. if (!win)
  1285. continue;
  1286. /* use the blank function to push into power-down */
  1287. s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
  1288. }
  1289. if (!sfb->variant.has_clksel)
  1290. clk_disable_unprepare(sfb->lcd_clk);
  1291. clk_disable_unprepare(sfb->bus_clk);
  1292. pm_runtime_put_sync(sfb->dev);
  1293. return 0;
  1294. }
  1295. static int s3c_fb_resume(struct device *dev)
  1296. {
  1297. struct s3c_fb *sfb = dev_get_drvdata(dev);
  1298. struct s3c_fb_platdata *pd = sfb->pdata;
  1299. struct s3c_fb_win *win;
  1300. int win_no;
  1301. u32 reg;
  1302. pm_runtime_get_sync(sfb->dev);
  1303. clk_prepare_enable(sfb->bus_clk);
  1304. if (!sfb->variant.has_clksel)
  1305. clk_prepare_enable(sfb->lcd_clk);
  1306. /* setup gpio and output polarity controls */
  1307. pd->setup_gpio();
  1308. writel(pd->vidcon1, sfb->regs + VIDCON1);
  1309. /* set video clock running at under-run */
  1310. if (sfb->variant.has_fixvclk) {
  1311. reg = readl(sfb->regs + VIDCON1);
  1312. reg &= ~VIDCON1_VCLK_MASK;
  1313. reg |= VIDCON1_VCLK_RUN;
  1314. writel(reg, sfb->regs + VIDCON1);
  1315. }
  1316. /* zero all windows before we do anything */
  1317. for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
  1318. s3c_fb_clear_win(sfb, win_no);
  1319. for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
  1320. void __iomem *regs = sfb->regs + sfb->variant.keycon;
  1321. win = sfb->windows[win_no];
  1322. if (!win)
  1323. continue;
  1324. shadow_protect_win(win, 1);
  1325. regs += (win_no * 8);
  1326. writel(0xffffff, regs + WKEYCON0);
  1327. writel(0xffffff, regs + WKEYCON1);
  1328. shadow_protect_win(win, 0);
  1329. }
  1330. s3c_fb_set_rgb_timing(sfb);
  1331. /* restore framebuffers */
  1332. for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
  1333. win = sfb->windows[win_no];
  1334. if (!win)
  1335. continue;
  1336. dev_dbg(dev, "resuming window %d\n", win_no);
  1337. s3c_fb_set_par(win->fbinfo);
  1338. }
  1339. pm_runtime_put_sync(sfb->dev);
  1340. return 0;
  1341. }
  1342. #endif
  1343. #ifdef CONFIG_PM
  1344. static int s3c_fb_runtime_suspend(struct device *dev)
  1345. {
  1346. struct s3c_fb *sfb = dev_get_drvdata(dev);
  1347. if (!sfb->variant.has_clksel)
  1348. clk_disable_unprepare(sfb->lcd_clk);
  1349. clk_disable_unprepare(sfb->bus_clk);
  1350. return 0;
  1351. }
  1352. static int s3c_fb_runtime_resume(struct device *dev)
  1353. {
  1354. struct s3c_fb *sfb = dev_get_drvdata(dev);
  1355. struct s3c_fb_platdata *pd = sfb->pdata;
  1356. clk_prepare_enable(sfb->bus_clk);
  1357. if (!sfb->variant.has_clksel)
  1358. clk_prepare_enable(sfb->lcd_clk);
  1359. /* setup gpio and output polarity controls */
  1360. pd->setup_gpio();
  1361. writel(pd->vidcon1, sfb->regs + VIDCON1);
  1362. return 0;
  1363. }
  1364. #endif
  1365. #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
  1366. #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
  1367. static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
  1368. [0] = {
  1369. .has_osd_c = 1,
  1370. .osd_size_off = 0x8,
  1371. .palette_sz = 256,
  1372. .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
  1373. VALID_BPP(18) | VALID_BPP(24)),
  1374. },
  1375. [1] = {
  1376. .has_osd_c = 1,
  1377. .has_osd_d = 1,
  1378. .osd_size_off = 0xc,
  1379. .has_osd_alpha = 1,
  1380. .palette_sz = 256,
  1381. .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
  1382. VALID_BPP(18) | VALID_BPP(19) |
  1383. VALID_BPP(24) | VALID_BPP(25) |
  1384. VALID_BPP(28)),
  1385. },
  1386. [2] = {
  1387. .has_osd_c = 1,
  1388. .has_osd_d = 1,
  1389. .osd_size_off = 0xc,
  1390. .has_osd_alpha = 1,
  1391. .palette_sz = 16,
  1392. .palette_16bpp = 1,
  1393. .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
  1394. VALID_BPP(18) | VALID_BPP(19) |
  1395. VALID_BPP(24) | VALID_BPP(25) |
  1396. VALID_BPP(28)),
  1397. },
  1398. [3] = {
  1399. .has_osd_c = 1,
  1400. .has_osd_alpha = 1,
  1401. .palette_sz = 16,
  1402. .palette_16bpp = 1,
  1403. .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
  1404. VALID_BPP(18) | VALID_BPP(19) |
  1405. VALID_BPP(24) | VALID_BPP(25) |
  1406. VALID_BPP(28)),
  1407. },
  1408. [4] = {
  1409. .has_osd_c = 1,
  1410. .has_osd_alpha = 1,
  1411. .palette_sz = 4,
  1412. .palette_16bpp = 1,
  1413. .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
  1414. VALID_BPP(16) | VALID_BPP(18) |
  1415. VALID_BPP(19) | VALID_BPP(24) |
  1416. VALID_BPP(25) | VALID_BPP(28)),
  1417. },
  1418. };
  1419. static struct s3c_fb_driverdata s3c_fb_data_64xx = {
  1420. .variant = {
  1421. .nr_windows = 5,
  1422. .vidtcon = VIDTCON0,
  1423. .wincon = WINCON(0),
  1424. .winmap = WINxMAP(0),
  1425. .keycon = WKEYCON,
  1426. .osd = VIDOSD_BASE,
  1427. .osd_stride = 16,
  1428. .buf_start = VIDW_BUF_START(0),
  1429. .buf_size = VIDW_BUF_SIZE(0),
  1430. .buf_end = VIDW_BUF_END(0),
  1431. .palette = {
  1432. [0] = 0x400,
  1433. [1] = 0x800,
  1434. [2] = 0x300,
  1435. [3] = 0x320,
  1436. [4] = 0x340,
  1437. },
  1438. .has_prtcon = 1,
  1439. .has_clksel = 1,
  1440. },
  1441. .win[0] = &s3c_fb_data_64xx_wins[0],
  1442. .win[1] = &s3c_fb_data_64xx_wins[1],
  1443. .win[2] = &s3c_fb_data_64xx_wins[2],
  1444. .win[3] = &s3c_fb_data_64xx_wins[3],
  1445. .win[4] = &s3c_fb_data_64xx_wins[4],
  1446. };
  1447. /* S3C2443/S3C2416 style hardware */
  1448. static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
  1449. .variant = {
  1450. .nr_windows = 2,
  1451. .is_2443 = 1,
  1452. .vidtcon = 0x08,
  1453. .wincon = 0x14,
  1454. .winmap = 0xd0,
  1455. .keycon = 0xb0,
  1456. .osd = 0x28,
  1457. .osd_stride = 12,
  1458. .buf_start = 0x64,
  1459. .buf_size = 0x94,
  1460. .buf_end = 0x7c,
  1461. .palette = {
  1462. [0] = 0x400,
  1463. [1] = 0x800,
  1464. },
  1465. .has_clksel = 1,
  1466. },
  1467. .win[0] = &(struct s3c_fb_win_variant) {
  1468. .palette_sz = 256,
  1469. .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
  1470. },
  1471. .win[1] = &(struct s3c_fb_win_variant) {
  1472. .has_osd_c = 1,
  1473. .has_osd_alpha = 1,
  1474. .palette_sz = 256,
  1475. .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
  1476. VALID_BPP(18) | VALID_BPP(19) |
  1477. VALID_BPP(24) | VALID_BPP(25) |
  1478. VALID_BPP(28)),
  1479. },
  1480. };
  1481. static const struct platform_device_id s3c_fb_driver_ids[] = {
  1482. {
  1483. .name = "s3c-fb",
  1484. .driver_data = (unsigned long)&s3c_fb_data_64xx,
  1485. }, {
  1486. .name = "s3c2443-fb",
  1487. .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
  1488. },
  1489. {},
  1490. };
  1491. MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
  1492. static const struct dev_pm_ops s3cfb_pm_ops = {
  1493. SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
  1494. SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
  1495. NULL)
  1496. };
  1497. static struct platform_driver s3c_fb_driver = {
  1498. .probe = s3c_fb_probe,
  1499. .remove = s3c_fb_remove,
  1500. .id_table = s3c_fb_driver_ids,
  1501. .driver = {
  1502. .name = "s3c-fb",
  1503. .pm = &s3cfb_pm_ops,
  1504. },
  1505. };
  1506. module_platform_driver(s3c_fb_driver);
  1507. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  1508. MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
  1509. MODULE_LICENSE("GPL");
  1510. MODULE_ALIAS("platform:s3c-fb");