pxa168fb.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __PXA168FB_H__
  3. #define __PXA168FB_H__
  4. /* ------------< LCD register >------------ */
  5. /* Video Frame 0&1 start address registers */
  6. #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
  7. #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
  8. #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
  9. #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
  10. #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
  11. #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
  12. #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
  13. #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
  14. /* YC & UV Pitch */
  15. #define LCD_SPU_DMA_PITCH_YC 0x00E0
  16. #define SPU_DMA_PITCH_C(c) ((c) << 16)
  17. #define SPU_DMA_PITCH_Y(y) (y)
  18. #define LCD_SPU_DMA_PITCH_UV 0x00E4
  19. #define SPU_DMA_PITCH_V(v) ((v) << 16)
  20. #define SPU_DMA_PITCH_U(u) (u)
  21. /* Video Starting Point on Screen Register */
  22. #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8
  23. #define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */
  24. #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */
  25. /* Video Size Register */
  26. #define LCD_SPU_DMA_HPXL_VLN 0x00EC
  27. #define CFG_DMA_VLN(y) ((y) << 16)
  28. #define CFG_DMA_HPXL(x) (x)
  29. /* Video Size After zooming Register */
  30. #define LCD_SPU_DZM_HPXL_VLN 0x00F0
  31. #define CFG_DZM_VLN(y) ((y) << 16)
  32. #define CFG_DZM_HPXL(x) (x)
  33. /* Graphic Frame 0&1 Starting Address Register */
  34. #define LCD_CFG_GRA_START_ADDR0 0x00F4
  35. #define LCD_CFG_GRA_START_ADDR1 0x00F8
  36. /* Graphic Frame Pitch */
  37. #define LCD_CFG_GRA_PITCH 0x00FC
  38. /* Graphic Starting Point on Screen Register */
  39. #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
  40. #define CFG_GRA_OVSA_VLN(y) ((y) << 16)
  41. #define CFG_GRA_OVSA_HPXL(x) (x)
  42. /* Graphic Size Register */
  43. #define LCD_SPU_GRA_HPXL_VLN 0x0104
  44. #define CFG_GRA_VLN(y) ((y) << 16)
  45. #define CFG_GRA_HPXL(x) (x)
  46. /* Graphic Size after Zooming Register */
  47. #define LCD_SPU_GZM_HPXL_VLN 0x0108
  48. #define CFG_GZM_VLN(y) ((y) << 16)
  49. #define CFG_GZM_HPXL(x) (x)
  50. /* HW Cursor Starting Point on Screen Register */
  51. #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C
  52. #define CFG_HWC_OVSA_VLN(y) ((y) << 16)
  53. #define CFG_HWC_OVSA_HPXL(x) (x)
  54. /* HW Cursor Size */
  55. #define LCD_SPU_HWC_HPXL_VLN 0x0110
  56. #define CFG_HWC_VLN(y) ((y) << 16)
  57. #define CFG_HWC_HPXL(x) (x)
  58. /* Total Screen Size Register */
  59. #define LCD_SPUT_V_H_TOTAL 0x0114
  60. #define CFG_V_TOTAL(y) ((y) << 16)
  61. #define CFG_H_TOTAL(x) (x)
  62. /* Total Screen Active Size Register */
  63. #define LCD_SPU_V_H_ACTIVE 0x0118
  64. #define CFG_V_ACTIVE(y) ((y) << 16)
  65. #define CFG_H_ACTIVE(x) (x)
  66. /* Screen H&V Porch Register */
  67. #define LCD_SPU_H_PORCH 0x011C
  68. #define CFG_H_BACK_PORCH(b) ((b) << 16)
  69. #define CFG_H_FRONT_PORCH(f) (f)
  70. #define LCD_SPU_V_PORCH 0x0120
  71. #define CFG_V_BACK_PORCH(b) ((b) << 16)
  72. #define CFG_V_FRONT_PORCH(f) (f)
  73. /* Screen Blank Color Register */
  74. #define LCD_SPU_BLANKCOLOR 0x0124
  75. #define CFG_BLANKCOLOR_MASK 0x00FFFFFF
  76. #define CFG_BLANKCOLOR_R_MASK 0x000000FF
  77. #define CFG_BLANKCOLOR_G_MASK 0x0000FF00
  78. #define CFG_BLANKCOLOR_B_MASK 0x00FF0000
  79. /* HW Cursor Color 1&2 Register */
  80. #define LCD_SPU_ALPHA_COLOR1 0x0128
  81. #define CFG_HWC_COLOR1 0x00FFFFFF
  82. #define CFG_HWC_COLOR1_R(red) ((red) << 16)
  83. #define CFG_HWC_COLOR1_G(green) ((green) << 8)
  84. #define CFG_HWC_COLOR1_B(blue) (blue)
  85. #define CFG_HWC_COLOR1_R_MASK 0x000000FF
  86. #define CFG_HWC_COLOR1_G_MASK 0x0000FF00
  87. #define CFG_HWC_COLOR1_B_MASK 0x00FF0000
  88. #define LCD_SPU_ALPHA_COLOR2 0x012C
  89. #define CFG_HWC_COLOR2 0x00FFFFFF
  90. #define CFG_HWC_COLOR2_R_MASK 0x000000FF
  91. #define CFG_HWC_COLOR2_G_MASK 0x0000FF00
  92. #define CFG_HWC_COLOR2_B_MASK 0x00FF0000
  93. /* Video YUV Color Key Control */
  94. #define LCD_SPU_COLORKEY_Y 0x0130
  95. #define CFG_CKEY_Y2(y2) ((y2) << 24)
  96. #define CFG_CKEY_Y2_MASK 0xFF000000
  97. #define CFG_CKEY_Y1(y1) ((y1) << 16)
  98. #define CFG_CKEY_Y1_MASK 0x00FF0000
  99. #define CFG_CKEY_Y(y) ((y) << 8)
  100. #define CFG_CKEY_Y_MASK 0x0000FF00
  101. #define CFG_ALPHA_Y(y) (y)
  102. #define CFG_ALPHA_Y_MASK 0x000000FF
  103. #define LCD_SPU_COLORKEY_U 0x0134
  104. #define CFG_CKEY_U2(u2) ((u2) << 24)
  105. #define CFG_CKEY_U2_MASK 0xFF000000
  106. #define CFG_CKEY_U1(u1) ((u1) << 16)
  107. #define CFG_CKEY_U1_MASK 0x00FF0000
  108. #define CFG_CKEY_U(u) ((u) << 8)
  109. #define CFG_CKEY_U_MASK 0x0000FF00
  110. #define CFG_ALPHA_U(u) (u)
  111. #define CFG_ALPHA_U_MASK 0x000000FF
  112. #define LCD_SPU_COLORKEY_V 0x0138
  113. #define CFG_CKEY_V2(v2) ((v2) << 24)
  114. #define CFG_CKEY_V2_MASK 0xFF000000
  115. #define CFG_CKEY_V1(v1) ((v1) << 16)
  116. #define CFG_CKEY_V1_MASK 0x00FF0000
  117. #define CFG_CKEY_V(v) ((v) << 8)
  118. #define CFG_CKEY_V_MASK 0x0000FF00
  119. #define CFG_ALPHA_V(v) (v)
  120. #define CFG_ALPHA_V_MASK 0x000000FF
  121. /* SPI Read Data Register */
  122. #define LCD_SPU_SPI_RXDATA 0x0140
  123. /* Smart Panel Read Data Register */
  124. #define LCD_SPU_ISA_RSDATA 0x0144
  125. #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF
  126. #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00
  127. #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000
  128. #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000
  129. #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF
  130. /* HWC SRAM Read Data Register */
  131. #define LCD_SPU_HWC_RDDAT 0x0158
  132. /* Gamma Table SRAM Read Data Register */
  133. #define LCD_SPU_GAMMA_RDDAT 0x015c
  134. #define CFG_GAMMA_RDDAT_MASK 0x000000FF
  135. /* Palette Table SRAM Read Data Register */
  136. #define LCD_SPU_PALETTE_RDDAT 0x0160
  137. #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF
  138. /* I/O Pads Input Read Only Register */
  139. #define LCD_SPU_IOPAD_IN 0x0178
  140. #define CFG_IOPAD_IN_MASK 0x0FFFFFFF
  141. /* Reserved Read Only Registers */
  142. #define LCD_CFG_RDREG5F 0x017C
  143. #define IRE_FRAME_CNT_MASK 0x000000C0
  144. #define IPE_FRAME_CNT_MASK 0x00000030
  145. #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */
  146. #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */
  147. /* SPI Control Register. */
  148. #define LCD_SPU_SPI_CTRL 0x0180
  149. #define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */
  150. #define CFG_SCLKCNT_MASK 0xFF000000
  151. #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */
  152. #define CFG_RXBITS_MASK 0x00FF0000
  153. #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */
  154. #define CFG_TXBITS_MASK 0x0000FF00
  155. #define CFG_CLKINV(clk) ((clk) << 7)
  156. #define CFG_CLKINV_MASK 0x00000080
  157. #define CFG_KEEPXFER(transfer) ((transfer) << 6)
  158. #define CFG_KEEPXFER_MASK 0x00000040
  159. #define CFG_RXBITSTO0(rx) ((rx) << 5)
  160. #define CFG_RXBITSTO0_MASK 0x00000020
  161. #define CFG_TXBITSTO0(tx) ((tx) << 4)
  162. #define CFG_TXBITSTO0_MASK 0x00000010
  163. #define CFG_SPI_ENA(spi) ((spi) << 3)
  164. #define CFG_SPI_ENA_MASK 0x00000008
  165. #define CFG_SPI_SEL(spi) ((spi) << 2)
  166. #define CFG_SPI_SEL_MASK 0x00000004
  167. #define CFG_SPI_3W4WB(wire) ((wire) << 1)
  168. #define CFG_SPI_3W4WB_MASK 0x00000002
  169. #define CFG_SPI_START(start) (start)
  170. #define CFG_SPI_START_MASK 0x00000001
  171. /* SPI Tx Data Register */
  172. #define LCD_SPU_SPI_TXDATA 0x0184
  173. /*
  174. 1. Smart Pannel 8-bit Bus Control Register.
  175. 2. AHB Slave Path Data Port Register
  176. */
  177. #define LCD_SPU_SMPN_CTRL 0x0188
  178. /* DMA Control 0 Register */
  179. #define LCD_SPU_DMA_CTRL0 0x0190
  180. #define CFG_NOBLENDING(nb) ((nb) << 31)
  181. #define CFG_NOBLENDING_MASK 0x80000000
  182. #define CFG_GAMMA_ENA(gn) ((gn) << 30)
  183. #define CFG_GAMMA_ENA_MASK 0x40000000
  184. #define CFG_CBSH_ENA(cn) ((cn) << 29)
  185. #define CFG_CBSH_ENA_MASK 0x20000000
  186. #define CFG_PALETTE_ENA(pn) ((pn) << 28)
  187. #define CFG_PALETTE_ENA_MASK 0x10000000
  188. #define CFG_ARBFAST_ENA(an) ((an) << 27)
  189. #define CFG_ARBFAST_ENA_MASK 0x08000000
  190. #define CFG_HWC_1BITMOD(mode) ((mode) << 26)
  191. #define CFG_HWC_1BITMOD_MASK 0x04000000
  192. #define CFG_HWC_1BITENA(mn) ((mn) << 25)
  193. #define CFG_HWC_1BITENA_MASK 0x02000000
  194. #define CFG_HWC_ENA(cn) ((cn) << 24)
  195. #define CFG_HWC_ENA_MASK 0x01000000
  196. #define CFG_DMAFORMAT(dmaformat) ((dmaformat) << 20)
  197. #define CFG_DMAFORMAT_MASK 0x00F00000
  198. #define CFG_GRAFORMAT(graformat) ((graformat) << 16)
  199. #define CFG_GRAFORMAT_MASK 0x000F0000
  200. /* for graphic part */
  201. #define CFG_GRA_FTOGGLE(toggle) ((toggle) << 15)
  202. #define CFG_GRA_FTOGGLE_MASK 0x00008000
  203. #define CFG_GRA_HSMOOTH(smooth) ((smooth) << 14)
  204. #define CFG_GRA_HSMOOTH_MASK 0x00004000
  205. #define CFG_GRA_TSTMODE(test) ((test) << 13)
  206. #define CFG_GRA_TSTMODE_MASK 0x00002000
  207. #define CFG_GRA_SWAPRB(swap) ((swap) << 12)
  208. #define CFG_GRA_SWAPRB_MASK 0x00001000
  209. #define CFG_GRA_SWAPUV(swap) ((swap) << 11)
  210. #define CFG_GRA_SWAPUV_MASK 0x00000800
  211. #define CFG_GRA_SWAPYU(swap) ((swap) << 10)
  212. #define CFG_GRA_SWAPYU_MASK 0x00000400
  213. #define CFG_YUV2RGB_GRA(cvrt) ((cvrt) << 9)
  214. #define CFG_YUV2RGB_GRA_MASK 0x00000200
  215. #define CFG_GRA_ENA(gra) ((gra) << 8)
  216. #define CFG_GRA_ENA_MASK 0x00000100
  217. /* for video part */
  218. #define CFG_DMA_FTOGGLE(toggle) ((toggle) << 7)
  219. #define CFG_DMA_FTOGGLE_MASK 0x00000080
  220. #define CFG_DMA_HSMOOTH(smooth) ((smooth) << 6)
  221. #define CFG_DMA_HSMOOTH_MASK 0x00000040
  222. #define CFG_DMA_TSTMODE(test) ((test) << 5)
  223. #define CFG_DMA_TSTMODE_MASK 0x00000020
  224. #define CFG_DMA_SWAPRB(swap) ((swap) << 4)
  225. #define CFG_DMA_SWAPRB_MASK 0x00000010
  226. #define CFG_DMA_SWAPUV(swap) ((swap) << 3)
  227. #define CFG_DMA_SWAPUV_MASK 0x00000008
  228. #define CFG_DMA_SWAPYU(swap) ((swap) << 2)
  229. #define CFG_DMA_SWAPYU_MASK 0x00000004
  230. #define CFG_DMA_SWAP_MASK 0x0000001C
  231. #define CFG_YUV2RGB_DMA(cvrt) ((cvrt) << 1)
  232. #define CFG_YUV2RGB_DMA_MASK 0x00000002
  233. #define CFG_DMA_ENA(video) (video)
  234. #define CFG_DMA_ENA_MASK 0x00000001
  235. /* DMA Control 1 Register */
  236. #define LCD_SPU_DMA_CTRL1 0x0194
  237. #define CFG_FRAME_TRIG(trig) ((trig) << 31)
  238. #define CFG_FRAME_TRIG_MASK 0x80000000
  239. #define CFG_VSYNC_TRIG(trig) ((trig) << 28)
  240. #define CFG_VSYNC_TRIG_MASK 0x70000000
  241. #define CFG_VSYNC_INV(inv) ((inv) << 27)
  242. #define CFG_VSYNC_INV_MASK 0x08000000
  243. #define CFG_COLOR_KEY_MODE(cmode) ((cmode) << 24)
  244. #define CFG_COLOR_KEY_MASK 0x07000000
  245. #define CFG_CARRY(carry) ((carry) << 23)
  246. #define CFG_CARRY_MASK 0x00800000
  247. #define CFG_LNBUF_ENA(lnbuf) ((lnbuf) << 22)
  248. #define CFG_LNBUF_ENA_MASK 0x00400000
  249. #define CFG_GATED_ENA(gated) ((gated) << 21)
  250. #define CFG_GATED_ENA_MASK 0x00200000
  251. #define CFG_PWRDN_ENA(power) ((power) << 20)
  252. #define CFG_PWRDN_ENA_MASK 0x00100000
  253. #define CFG_DSCALE(dscale) ((dscale) << 18)
  254. #define CFG_DSCALE_MASK 0x000C0000
  255. #define CFG_ALPHA_MODE(amode) ((amode) << 16)
  256. #define CFG_ALPHA_MODE_MASK 0x00030000
  257. #define CFG_ALPHA(alpha) ((alpha) << 8)
  258. #define CFG_ALPHA_MASK 0x0000FF00
  259. #define CFG_PXLCMD(pxlcmd) (pxlcmd)
  260. #define CFG_PXLCMD_MASK 0x000000FF
  261. /* SRAM Control Register */
  262. #define LCD_SPU_SRAM_CTRL 0x0198
  263. #define CFG_SRAM_INIT_WR_RD(mode) ((mode) << 14)
  264. #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000
  265. #define CFG_SRAM_ADDR_LCDID(id) ((id) << 8)
  266. #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00
  267. #define CFG_SRAM_ADDR(addr) (addr)
  268. #define CFG_SRAM_ADDR_MASK 0x000000FF
  269. /* SRAM Write Data Register */
  270. #define LCD_SPU_SRAM_WRDAT 0x019C
  271. /* SRAM RTC/WTC Control Register */
  272. #define LCD_SPU_SRAM_PARA0 0x01A0
  273. /* SRAM Power Down Control Register */
  274. #define LCD_SPU_SRAM_PARA1 0x01A4
  275. #define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */
  276. #define CFG_CSB_256x32_MASK 0x00008000
  277. #define CFG_CSB_256x24(palette) ((palette) << 14) /* Palette */
  278. #define CFG_CSB_256x24_MASK 0x00004000
  279. #define CFG_CSB_256x8(gamma) ((gamma) << 13) /* Gamma */
  280. #define CFG_CSB_256x8_MASK 0x00002000
  281. #define CFG_PDWN256x32(pdwn) ((pdwn) << 7) /* HWC */
  282. #define CFG_PDWN256x32_MASK 0x00000080
  283. #define CFG_PDWN256x24(pdwn) ((pdwn) << 6) /* Palette */
  284. #define CFG_PDWN256x24_MASK 0x00000040
  285. #define CFG_PDWN256x8(pdwn) ((pdwn) << 5) /* Gamma */
  286. #define CFG_PDWN256x8_MASK 0x00000020
  287. #define CFG_PDWN32x32(pdwn) ((pdwn) << 3)
  288. #define CFG_PDWN32x32_MASK 0x00000008
  289. #define CFG_PDWN16x66(pdwn) ((pdwn) << 2)
  290. #define CFG_PDWN16x66_MASK 0x00000004
  291. #define CFG_PDWN32x66(pdwn) ((pdwn) << 1)
  292. #define CFG_PDWN32x66_MASK 0x00000002
  293. #define CFG_PDWN64x66(pdwn) (pdwn)
  294. #define CFG_PDWN64x66_MASK 0x00000001
  295. /* Smart or Dumb Panel Clock Divider */
  296. #define LCD_CFG_SCLK_DIV 0x01A8
  297. #define SCLK_SOURCE_SELECT(src) ((src) << 31)
  298. #define SCLK_SOURCE_SELECT_MASK 0x80000000
  299. #define CLK_FRACDIV(frac) ((frac) << 16)
  300. #define CLK_FRACDIV_MASK 0x0FFF0000
  301. #define CLK_INT_DIV(div) (div)
  302. #define CLK_INT_DIV_MASK 0x0000FFFF
  303. /* Video Contrast Register */
  304. #define LCD_SPU_CONTRAST 0x01AC
  305. #define CFG_BRIGHTNESS(bright) ((bright) << 16)
  306. #define CFG_BRIGHTNESS_MASK 0xFFFF0000
  307. #define CFG_CONTRAST(contrast) (contrast)
  308. #define CFG_CONTRAST_MASK 0x0000FFFF
  309. /* Video Saturation Register */
  310. #define LCD_SPU_SATURATION 0x01B0
  311. #define CFG_C_MULTS(mult) ((mult) << 16)
  312. #define CFG_C_MULTS_MASK 0xFFFF0000
  313. #define CFG_SATURATION(sat) (sat)
  314. #define CFG_SATURATION_MASK 0x0000FFFF
  315. /* Video Hue Adjust Register */
  316. #define LCD_SPU_CBSH_HUE 0x01B4
  317. #define CFG_SIN0(sin0) ((sin0) << 16)
  318. #define CFG_SIN0_MASK 0xFFFF0000
  319. #define CFG_COS0(con0) (con0)
  320. #define CFG_COS0_MASK 0x0000FFFF
  321. /* Dump LCD Panel Control Register */
  322. #define LCD_SPU_DUMB_CTRL 0x01B8
  323. #define CFG_DUMBMODE(mode) ((mode) << 28)
  324. #define CFG_DUMBMODE_MASK 0xF0000000
  325. #define CFG_LCDGPIO_O(data) ((data) << 20)
  326. #define CFG_LCDGPIO_O_MASK 0x0FF00000
  327. #define CFG_LCDGPIO_ENA(gpio) ((gpio) << 12)
  328. #define CFG_LCDGPIO_ENA_MASK 0x000FF000
  329. #define CFG_BIAS_OUT(bias) ((bias) << 8)
  330. #define CFG_BIAS_OUT_MASK 0x00000100
  331. #define CFG_REVERSE_RGB(rRGB) ((rRGB) << 7)
  332. #define CFG_REVERSE_RGB_MASK 0x00000080
  333. #define CFG_INV_COMPBLANK(blank) ((blank) << 6)
  334. #define CFG_INV_COMPBLANK_MASK 0x00000040
  335. #define CFG_INV_COMPSYNC(sync) ((sync) << 5)
  336. #define CFG_INV_COMPSYNC_MASK 0x00000020
  337. #define CFG_INV_HENA(hena) ((hena) << 4)
  338. #define CFG_INV_HENA_MASK 0x00000010
  339. #define CFG_INV_VSYNC(vsync) ((vsync) << 3)
  340. #define CFG_INV_VSYNC_MASK 0x00000008
  341. #define CFG_INV_HSYNC(hsync) ((hsync) << 2)
  342. #define CFG_INV_HSYNC_MASK 0x00000004
  343. #define CFG_INV_PCLK(pclk) ((pclk) << 1)
  344. #define CFG_INV_PCLK_MASK 0x00000002
  345. #define CFG_DUMB_ENA(dumb) (dumb)
  346. #define CFG_DUMB_ENA_MASK 0x00000001
  347. /* LCD I/O Pads Control Register */
  348. #define SPU_IOPAD_CONTROL 0x01BC
  349. #define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */
  350. #define CFG_GRA_VM_ENA_MASK 0x00008000
  351. #define CFG_DMA_VM_ENA(vm) ((vm) << 13) /* video */
  352. #define CFG_DMA_VM_ENA_MASK 0x00002000
  353. #define CFG_CMD_VM_ENA(vm) ((vm) << 13)
  354. #define CFG_CMD_VM_ENA_MASK 0x00000800
  355. #define CFG_CSC(csc) ((csc) << 8) /* csc */
  356. #define CFG_CSC_MASK 0x00000300
  357. #define CFG_AXICTRL(axi) ((axi) << 4)
  358. #define CFG_AXICTRL_MASK 0x000000F0
  359. #define CFG_IOPADMODE(iopad) (iopad)
  360. #define CFG_IOPADMODE_MASK 0x0000000F
  361. /* LCD Interrupt Control Register */
  362. #define SPU_IRQ_ENA 0x01C0
  363. #define DMA_FRAME_IRQ0_ENA(irq) ((irq) << 31)
  364. #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000
  365. #define DMA_FRAME_IRQ1_ENA(irq) ((irq) << 30)
  366. #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000
  367. #define DMA_FF_UNDERFLOW_ENA(ff) ((ff) << 29)
  368. #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000
  369. #define GRA_FRAME_IRQ0_ENA(irq) ((irq) << 27)
  370. #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000
  371. #define GRA_FRAME_IRQ1_ENA(irq) ((irq) << 26)
  372. #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000
  373. #define GRA_FF_UNDERFLOW_ENA(ff) ((ff) << 25)
  374. #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000
  375. #define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq) << 23)
  376. #define VSYNC_IRQ_ENA_MASK 0x00800000
  377. #define DUMB_FRAMEDONE_ENA(fdone) ((fdone) << 22)
  378. #define DUMB_FRAMEDONE_ENA_MASK 0x00400000
  379. #define TWC_FRAMEDONE_ENA(fdone) ((fdone) << 21)
  380. #define TWC_FRAMEDONE_ENA_MASK 0x00200000
  381. #define HWC_FRAMEDONE_ENA(fdone) ((fdone) << 20)
  382. #define HWC_FRAMEDONE_ENA_MASK 0x00100000
  383. #define SLV_IRQ_ENA(irq) ((irq) << 19)
  384. #define SLV_IRQ_ENA_MASK 0x00080000
  385. #define SPI_IRQ_ENA(irq) ((irq) << 18)
  386. #define SPI_IRQ_ENA_MASK 0x00040000
  387. #define PWRDN_IRQ_ENA(irq) ((irq) << 17)
  388. #define PWRDN_IRQ_ENA_MASK 0x00020000
  389. #define ERR_IRQ_ENA(irq) ((irq) << 16)
  390. #define ERR_IRQ_ENA_MASK 0x00010000
  391. #define CLEAN_SPU_IRQ_ISR(irq) (irq)
  392. #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF
  393. /* LCD Interrupt Status Register */
  394. #define SPU_IRQ_ISR 0x01C4
  395. #define DMA_FRAME_IRQ0(irq) ((irq) << 31)
  396. #define DMA_FRAME_IRQ0_MASK 0x80000000
  397. #define DMA_FRAME_IRQ1(irq) ((irq) << 30)
  398. #define DMA_FRAME_IRQ1_MASK 0x40000000
  399. #define DMA_FF_UNDERFLOW(ff) ((ff) << 29)
  400. #define DMA_FF_UNDERFLOW_MASK 0x20000000
  401. #define GRA_FRAME_IRQ0(irq) ((irq) << 27)
  402. #define GRA_FRAME_IRQ0_MASK 0x08000000
  403. #define GRA_FRAME_IRQ1(irq) ((irq) << 26)
  404. #define GRA_FRAME_IRQ1_MASK 0x04000000
  405. #define GRA_FF_UNDERFLOW(ff) ((ff) << 25)
  406. #define GRA_FF_UNDERFLOW_MASK 0x02000000
  407. #define VSYNC_IRQ(vsync_irq) ((vsync_irq) << 23)
  408. #define VSYNC_IRQ_MASK 0x00800000
  409. #define DUMB_FRAMEDONE(fdone) ((fdone) << 22)
  410. #define DUMB_FRAMEDONE_MASK 0x00400000
  411. #define TWC_FRAMEDONE(fdone) ((fdone) << 21)
  412. #define TWC_FRAMEDONE_MASK 0x00200000
  413. #define HWC_FRAMEDONE(fdone) ((fdone) << 20)
  414. #define HWC_FRAMEDONE_MASK 0x00100000
  415. #define SLV_IRQ(irq) ((irq) << 19)
  416. #define SLV_IRQ_MASK 0x00080000
  417. #define SPI_IRQ(irq) ((irq) << 18)
  418. #define SPI_IRQ_MASK 0x00040000
  419. #define PWRDN_IRQ(irq) ((irq) << 17)
  420. #define PWRDN_IRQ_MASK 0x00020000
  421. #define ERR_IRQ(irq) ((irq) << 16)
  422. #define ERR_IRQ_MASK 0x00010000
  423. /* read-only */
  424. #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000
  425. #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000
  426. #define DMA_FRAME_CNT_ISR_MASK 0x00003000
  427. #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800
  428. #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400
  429. #define GRA_FRAME_CNT_ISR_MASK 0x00000300
  430. #define VSYNC_IRQ_LEVEL_MASK 0x00000080
  431. #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040
  432. #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020
  433. #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010
  434. #define SLV_FF_EMPTY_MASK 0x00000008
  435. #define DMA_FF_ALLEMPTY_MASK 0x00000004
  436. #define GRA_FF_ALLEMPTY_MASK 0x00000002
  437. #define PWRDN_IRQ_LEVEL_MASK 0x00000001
  438. /*
  439. * defined Video Memory Color format for DMA control 0 register
  440. * DMA0 bit[23:20]
  441. */
  442. #define VMODE_RGB565 0x0
  443. #define VMODE_RGB1555 0x1
  444. #define VMODE_RGB888PACKED 0x2
  445. #define VMODE_RGB888UNPACKED 0x3
  446. #define VMODE_RGBA888 0x4
  447. #define VMODE_YUV422PACKED 0x5
  448. #define VMODE_YUV422PLANAR 0x6
  449. #define VMODE_YUV420PLANAR 0x7
  450. #define VMODE_SMPNCMD 0x8
  451. #define VMODE_PALETTE4BIT 0x9
  452. #define VMODE_PALETTE8BIT 0xa
  453. #define VMODE_RESERVED 0xb
  454. /*
  455. * defined Graphic Memory Color format for DMA control 0 register
  456. * DMA0 bit[19:16]
  457. */
  458. #define GMODE_RGB565 0x0
  459. #define GMODE_RGB1555 0x1
  460. #define GMODE_RGB888PACKED 0x2
  461. #define GMODE_RGB888UNPACKED 0x3
  462. #define GMODE_RGBA888 0x4
  463. #define GMODE_YUV422PACKED 0x5
  464. #define GMODE_YUV422PLANAR 0x6
  465. #define GMODE_YUV420PLANAR 0x7
  466. #define GMODE_SMPNCMD 0x8
  467. #define GMODE_PALETTE4BIT 0x9
  468. #define GMODE_PALETTE8BIT 0xa
  469. #define GMODE_RESERVED 0xb
  470. /*
  471. * define for DMA control 1 register
  472. */
  473. #define DMA1_FRAME_TRIG 31 /* bit location */
  474. #define DMA1_VSYNC_MODE 28
  475. #define DMA1_VSYNC_INV 27
  476. #define DMA1_CKEY 24
  477. #define DMA1_CARRY 23
  478. #define DMA1_LNBUF_ENA 22
  479. #define DMA1_GATED_ENA 21
  480. #define DMA1_PWRDN_ENA 20
  481. #define DMA1_DSCALE 18
  482. #define DMA1_ALPHA_MODE 16
  483. #define DMA1_ALPHA 08
  484. #define DMA1_PXLCMD 00
  485. /*
  486. * defined for Configure Dumb Mode
  487. * DUMB LCD Panel bit[31:28]
  488. */
  489. #define DUMB16_RGB565_0 0x0
  490. #define DUMB16_RGB565_1 0x1
  491. #define DUMB18_RGB666_0 0x2
  492. #define DUMB18_RGB666_1 0x3
  493. #define DUMB12_RGB444_0 0x4
  494. #define DUMB12_RGB444_1 0x5
  495. #define DUMB24_RGB888_0 0x6
  496. #define DUMB_BLANK 0x7
  497. /*
  498. * defined for Configure I/O Pin Allocation Mode
  499. * LCD LCD I/O Pads control register bit[3:0]
  500. */
  501. #define IOPAD_DUMB24 0x0
  502. #define IOPAD_DUMB18SPI 0x1
  503. #define IOPAD_DUMB18GPIO 0x2
  504. #define IOPAD_DUMB16SPI 0x3
  505. #define IOPAD_DUMB16GPIO 0x4
  506. #define IOPAD_DUMB12 0x5
  507. #define IOPAD_SMART18SPI 0x6
  508. #define IOPAD_SMART16SPI 0x7
  509. #define IOPAD_SMART8BOTH 0x8
  510. #endif /* __PXA168FB_H__ */