pm3fb.c 42 KB

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  1. /*
  2. * linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
  3. *
  4. * Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
  5. *
  6. * Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
  7. * based on pm2fb.c
  8. *
  9. * Based on code written by:
  10. * Sven Luther, <luther@dpt-info.u-strasbg.fr>
  11. * Alan Hourihane, <alanh@fairlite.demon.co.uk>
  12. * Russell King, <rmk@arm.linux.org.uk>
  13. * Based on linux/drivers/video/skeletonfb.c:
  14. * Copyright (C) 1997 Geert Uytterhoeven
  15. * Based on linux/driver/video/pm2fb.c:
  16. * Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  17. * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  18. *
  19. * This file is subject to the terms and conditions of the GNU General Public
  20. * License. See the file COPYING in the main directory of this archive for
  21. * more details.
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/errno.h>
  27. #include <linux/string.h>
  28. #include <linux/mm.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/fb.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <video/pm3fb.h>
  35. #if !defined(CONFIG_PCI)
  36. #error "Only generic PCI cards supported."
  37. #endif
  38. #undef PM3FB_MASTER_DEBUG
  39. #ifdef PM3FB_MASTER_DEBUG
  40. #define DPRINTK(a, b...) \
  41. printk(KERN_DEBUG "pm3fb: %s: " a, __func__ , ## b)
  42. #else
  43. #define DPRINTK(a, b...) no_printk(a, ##b)
  44. #endif
  45. #define PM3_PIXMAP_SIZE (2048 * 4)
  46. /*
  47. * Driver data
  48. */
  49. static int hwcursor = 1;
  50. static char *mode_option;
  51. static bool noaccel;
  52. static bool nomtrr;
  53. /*
  54. * This structure defines the hardware state of the graphics card. Normally
  55. * you place this in a header file in linux/include/video. This file usually
  56. * also includes register information. That allows other driver subsystems
  57. * and userland applications the ability to use the same header file to
  58. * avoid duplicate work and easy porting of software.
  59. */
  60. struct pm3_par {
  61. unsigned char __iomem *v_regs;/* virtual address of p_regs */
  62. u32 video; /* video flags before blanking */
  63. u32 base; /* screen base in 128 bits unit */
  64. u32 palette[16];
  65. int wc_cookie;
  66. };
  67. /*
  68. * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  69. * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
  70. * to get a fb_var_screeninfo. Otherwise define a default var as well.
  71. */
  72. static struct fb_fix_screeninfo pm3fb_fix = {
  73. .id = "Permedia3",
  74. .type = FB_TYPE_PACKED_PIXELS,
  75. .visual = FB_VISUAL_PSEUDOCOLOR,
  76. .xpanstep = 1,
  77. .ypanstep = 1,
  78. .ywrapstep = 0,
  79. .accel = FB_ACCEL_3DLABS_PERMEDIA3,
  80. };
  81. /*
  82. * Utility functions
  83. */
  84. static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
  85. {
  86. return fb_readl(par->v_regs + off);
  87. }
  88. static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
  89. {
  90. fb_writel(v, par->v_regs + off);
  91. }
  92. static inline void PM3_WAIT(struct pm3_par *par, u32 n)
  93. {
  94. while (PM3_READ_REG(par, PM3InFIFOSpace) < n)
  95. cpu_relax();
  96. }
  97. static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
  98. {
  99. PM3_WAIT(par, 3);
  100. PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
  101. PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
  102. wmb();
  103. PM3_WRITE_REG(par, PM3RD_IndexedData, v);
  104. wmb();
  105. }
  106. static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
  107. unsigned char r, unsigned char g, unsigned char b)
  108. {
  109. PM3_WAIT(par, 4);
  110. PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
  111. wmb();
  112. PM3_WRITE_REG(par, PM3RD_PaletteData, r);
  113. wmb();
  114. PM3_WRITE_REG(par, PM3RD_PaletteData, g);
  115. wmb();
  116. PM3_WRITE_REG(par, PM3RD_PaletteData, b);
  117. wmb();
  118. }
  119. static void pm3fb_clear_colormap(struct pm3_par *par,
  120. unsigned char r, unsigned char g, unsigned char b)
  121. {
  122. int i;
  123. for (i = 0; i < 256 ; i++)
  124. pm3fb_set_color(par, i, r, g, b);
  125. }
  126. /* Calculating various clock parameters */
  127. static void pm3fb_calculate_clock(unsigned long reqclock,
  128. unsigned char *prescale,
  129. unsigned char *feedback,
  130. unsigned char *postscale)
  131. {
  132. int f, pre, post;
  133. unsigned long freq;
  134. long freqerr = 1000;
  135. long currerr;
  136. for (f = 1; f < 256; f++) {
  137. for (pre = 1; pre < 256; pre++) {
  138. for (post = 0; post < 5; post++) {
  139. freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
  140. currerr = (reqclock > freq)
  141. ? reqclock - freq
  142. : freq - reqclock;
  143. if (currerr < freqerr) {
  144. freqerr = currerr;
  145. *feedback = f;
  146. *prescale = pre;
  147. *postscale = post;
  148. }
  149. }
  150. }
  151. }
  152. }
  153. static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
  154. {
  155. if (var->bits_per_pixel == 16)
  156. return var->red.length + var->green.length
  157. + var->blue.length;
  158. return var->bits_per_pixel;
  159. }
  160. static inline int pm3fb_shift_bpp(unsigned bpp, int v)
  161. {
  162. switch (bpp) {
  163. case 8:
  164. return (v >> 4);
  165. case 16:
  166. return (v >> 3);
  167. case 32:
  168. return (v >> 2);
  169. }
  170. DPRINTK("Unsupported depth %u\n", bpp);
  171. return 0;
  172. }
  173. /* acceleration */
  174. static int pm3fb_sync(struct fb_info *info)
  175. {
  176. struct pm3_par *par = info->par;
  177. PM3_WAIT(par, 2);
  178. PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
  179. PM3_WRITE_REG(par, PM3Sync, 0);
  180. mb();
  181. do {
  182. while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0)
  183. cpu_relax();
  184. } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
  185. return 0;
  186. }
  187. static void pm3fb_init_engine(struct fb_info *info)
  188. {
  189. struct pm3_par *par = info->par;
  190. const u32 width = (info->var.xres_virtual + 7) & ~7;
  191. PM3_WAIT(par, 50);
  192. PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
  193. PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
  194. PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
  195. PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
  196. PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
  197. PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
  198. PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
  199. PM3_WRITE_REG(par, PM3GIDMode, 0x0);
  200. PM3_WRITE_REG(par, PM3DepthMode, 0x0);
  201. PM3_WRITE_REG(par, PM3StencilMode, 0x0);
  202. PM3_WRITE_REG(par, PM3StencilData, 0x0);
  203. PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
  204. PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
  205. PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
  206. PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
  207. PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
  208. PM3_WRITE_REG(par, PM3LUTMode, 0x0);
  209. PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
  210. PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
  211. PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
  212. PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
  213. PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
  214. PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
  215. PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
  216. PM3_WRITE_REG(par, PM3FogMode, 0x0);
  217. PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
  218. PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
  219. PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
  220. PM3_WRITE_REG(par, PM3YUVMode, 0x0);
  221. PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
  222. PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
  223. PM3_WRITE_REG(par, PM3DitherMode, 0x0);
  224. PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
  225. PM3_WRITE_REG(par, PM3RouterMode, 0x0);
  226. PM3_WRITE_REG(par, PM3Window, 0x0);
  227. PM3_WRITE_REG(par, PM3Config2D, 0x0);
  228. PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
  229. PM3_WRITE_REG(par, PM3XBias, 0x0);
  230. PM3_WRITE_REG(par, PM3YBias, 0x0);
  231. PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
  232. PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
  233. PM3_WRITE_REG(par, PM3FBDestReadEnables,
  234. PM3FBDestReadEnables_E(0xff) |
  235. PM3FBDestReadEnables_R(0xff) |
  236. PM3FBDestReadEnables_ReferenceAlpha(0xff));
  237. PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
  238. PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
  239. PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
  240. PM3FBDestReadBufferWidth_Width(width));
  241. PM3_WRITE_REG(par, PM3FBDestReadMode,
  242. PM3FBDestReadMode_ReadEnable |
  243. PM3FBDestReadMode_Enable0);
  244. PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
  245. PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
  246. PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
  247. PM3FBSourceReadBufferWidth_Width(width));
  248. PM3_WRITE_REG(par, PM3FBSourceReadMode,
  249. PM3FBSourceReadMode_Blocking |
  250. PM3FBSourceReadMode_ReadEnable);
  251. PM3_WAIT(par, 2);
  252. {
  253. /* invert bits in bitmask */
  254. unsigned long rm = 1 | (3 << 7);
  255. switch (info->var.bits_per_pixel) {
  256. case 8:
  257. PM3_WRITE_REG(par, PM3PixelSize,
  258. PM3PixelSize_GLOBAL_8BIT);
  259. #ifdef __BIG_ENDIAN
  260. rm |= 3 << 15;
  261. #endif
  262. break;
  263. case 16:
  264. PM3_WRITE_REG(par, PM3PixelSize,
  265. PM3PixelSize_GLOBAL_16BIT);
  266. #ifdef __BIG_ENDIAN
  267. rm |= 2 << 15;
  268. #endif
  269. break;
  270. case 32:
  271. PM3_WRITE_REG(par, PM3PixelSize,
  272. PM3PixelSize_GLOBAL_32BIT);
  273. break;
  274. default:
  275. DPRINTK("Unsupported depth %d\n",
  276. info->var.bits_per_pixel);
  277. break;
  278. }
  279. PM3_WRITE_REG(par, PM3RasterizerMode, rm);
  280. }
  281. PM3_WAIT(par, 20);
  282. PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
  283. PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
  284. PM3_WRITE_REG(par, PM3FBWriteMode,
  285. PM3FBWriteMode_WriteEnable |
  286. PM3FBWriteMode_OpaqueSpan |
  287. PM3FBWriteMode_Enable0);
  288. PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
  289. PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
  290. PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
  291. PM3FBWriteBufferWidth_Width(width));
  292. PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
  293. {
  294. /* size in lines of FB */
  295. unsigned long sofb = info->screen_size /
  296. info->fix.line_length;
  297. if (sofb > 4095)
  298. PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
  299. else
  300. PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
  301. switch (info->var.bits_per_pixel) {
  302. case 8:
  303. PM3_WRITE_REG(par, PM3DitherMode,
  304. (1 << 10) | (2 << 3));
  305. break;
  306. case 16:
  307. PM3_WRITE_REG(par, PM3DitherMode,
  308. (1 << 10) | (1 << 3));
  309. break;
  310. case 32:
  311. PM3_WRITE_REG(par, PM3DitherMode,
  312. (1 << 10) | (0 << 3));
  313. break;
  314. default:
  315. DPRINTK("Unsupported depth %d\n",
  316. info->var.bits_per_pixel);
  317. break;
  318. }
  319. }
  320. PM3_WRITE_REG(par, PM3dXDom, 0x0);
  321. PM3_WRITE_REG(par, PM3dXSub, 0x0);
  322. PM3_WRITE_REG(par, PM3dY, 1 << 16);
  323. PM3_WRITE_REG(par, PM3StartXDom, 0x0);
  324. PM3_WRITE_REG(par, PM3StartXSub, 0x0);
  325. PM3_WRITE_REG(par, PM3StartY, 0x0);
  326. PM3_WRITE_REG(par, PM3Count, 0x0);
  327. /* Disable LocalBuffer. better safe than sorry */
  328. PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
  329. PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
  330. PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
  331. PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
  332. pm3fb_sync(info);
  333. }
  334. static void pm3fb_fillrect(struct fb_info *info,
  335. const struct fb_fillrect *region)
  336. {
  337. struct pm3_par *par = info->par;
  338. struct fb_fillrect modded;
  339. int vxres, vyres;
  340. int rop;
  341. u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
  342. ((u32 *)info->pseudo_palette)[region->color] : region->color;
  343. if (info->state != FBINFO_STATE_RUNNING)
  344. return;
  345. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  346. cfb_fillrect(info, region);
  347. return;
  348. }
  349. if (region->rop == ROP_COPY )
  350. rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
  351. else
  352. rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
  353. PM3Config2D_FBDestReadEnable;
  354. vxres = info->var.xres_virtual;
  355. vyres = info->var.yres_virtual;
  356. memcpy(&modded, region, sizeof(struct fb_fillrect));
  357. if (!modded.width || !modded.height ||
  358. modded.dx >= vxres || modded.dy >= vyres)
  359. return;
  360. if (modded.dx + modded.width > vxres)
  361. modded.width = vxres - modded.dx;
  362. if (modded.dy + modded.height > vyres)
  363. modded.height = vyres - modded.dy;
  364. if (info->var.bits_per_pixel == 8)
  365. color |= color << 8;
  366. if (info->var.bits_per_pixel <= 16)
  367. color |= color << 16;
  368. PM3_WAIT(par, 4);
  369. /* ROP Ox3 is GXcopy */
  370. PM3_WRITE_REG(par, PM3Config2D,
  371. PM3Config2D_UseConstantSource |
  372. PM3Config2D_ForegroundROPEnable |
  373. rop |
  374. PM3Config2D_FBWriteEnable);
  375. PM3_WRITE_REG(par, PM3ForegroundColor, color);
  376. PM3_WRITE_REG(par, PM3RectanglePosition,
  377. PM3RectanglePosition_XOffset(modded.dx) |
  378. PM3RectanglePosition_YOffset(modded.dy));
  379. PM3_WRITE_REG(par, PM3Render2D,
  380. PM3Render2D_XPositive |
  381. PM3Render2D_YPositive |
  382. PM3Render2D_Operation_Normal |
  383. PM3Render2D_SpanOperation |
  384. PM3Render2D_Width(modded.width) |
  385. PM3Render2D_Height(modded.height));
  386. }
  387. static void pm3fb_copyarea(struct fb_info *info,
  388. const struct fb_copyarea *area)
  389. {
  390. struct pm3_par *par = info->par;
  391. struct fb_copyarea modded;
  392. u32 vxres, vyres;
  393. int x_align, o_x, o_y;
  394. if (info->state != FBINFO_STATE_RUNNING)
  395. return;
  396. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  397. cfb_copyarea(info, area);
  398. return;
  399. }
  400. memcpy(&modded, area, sizeof(struct fb_copyarea));
  401. vxres = info->var.xres_virtual;
  402. vyres = info->var.yres_virtual;
  403. if (!modded.width || !modded.height ||
  404. modded.sx >= vxres || modded.sy >= vyres ||
  405. modded.dx >= vxres || modded.dy >= vyres)
  406. return;
  407. if (modded.sx + modded.width > vxres)
  408. modded.width = vxres - modded.sx;
  409. if (modded.dx + modded.width > vxres)
  410. modded.width = vxres - modded.dx;
  411. if (modded.sy + modded.height > vyres)
  412. modded.height = vyres - modded.sy;
  413. if (modded.dy + modded.height > vyres)
  414. modded.height = vyres - modded.dy;
  415. o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
  416. o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
  417. x_align = (modded.sx & 0x1f);
  418. PM3_WAIT(par, 6);
  419. PM3_WRITE_REG(par, PM3Config2D,
  420. PM3Config2D_UserScissorEnable |
  421. PM3Config2D_ForegroundROPEnable |
  422. PM3Config2D_Blocking |
  423. PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
  424. PM3Config2D_FBWriteEnable);
  425. PM3_WRITE_REG(par, PM3ScissorMinXY,
  426. ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
  427. PM3_WRITE_REG(par, PM3ScissorMaxXY,
  428. (((modded.dy + modded.height) & 0x0fff) << 16) |
  429. ((modded.dx + modded.width) & 0x0fff));
  430. PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
  431. PM3FBSourceReadBufferOffset_XOffset(o_x) |
  432. PM3FBSourceReadBufferOffset_YOffset(o_y));
  433. PM3_WRITE_REG(par, PM3RectanglePosition,
  434. PM3RectanglePosition_XOffset(modded.dx - x_align) |
  435. PM3RectanglePosition_YOffset(modded.dy));
  436. PM3_WRITE_REG(par, PM3Render2D,
  437. ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
  438. ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
  439. PM3Render2D_Operation_Normal |
  440. PM3Render2D_SpanOperation |
  441. PM3Render2D_FBSourceReadEnable |
  442. PM3Render2D_Width(modded.width + x_align) |
  443. PM3Render2D_Height(modded.height));
  444. }
  445. static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
  446. {
  447. struct pm3_par *par = info->par;
  448. u32 height = image->height;
  449. u32 fgx, bgx;
  450. const u32 *src = (const u32 *)image->data;
  451. if (info->state != FBINFO_STATE_RUNNING)
  452. return;
  453. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  454. cfb_imageblit(info, image);
  455. return;
  456. }
  457. switch (info->fix.visual) {
  458. case FB_VISUAL_PSEUDOCOLOR:
  459. fgx = image->fg_color;
  460. bgx = image->bg_color;
  461. break;
  462. case FB_VISUAL_TRUECOLOR:
  463. default:
  464. fgx = par->palette[image->fg_color];
  465. bgx = par->palette[image->bg_color];
  466. break;
  467. }
  468. if (image->depth != 1) {
  469. cfb_imageblit(info, image);
  470. return;
  471. }
  472. if (info->var.bits_per_pixel == 8) {
  473. fgx |= fgx << 8;
  474. bgx |= bgx << 8;
  475. }
  476. if (info->var.bits_per_pixel <= 16) {
  477. fgx |= fgx << 16;
  478. bgx |= bgx << 16;
  479. }
  480. PM3_WAIT(par, 7);
  481. PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
  482. PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
  483. /* ROP Ox3 is GXcopy */
  484. PM3_WRITE_REG(par, PM3Config2D,
  485. PM3Config2D_UserScissorEnable |
  486. PM3Config2D_UseConstantSource |
  487. PM3Config2D_ForegroundROPEnable |
  488. PM3Config2D_ForegroundROP(0x3) |
  489. PM3Config2D_OpaqueSpan |
  490. PM3Config2D_FBWriteEnable);
  491. PM3_WRITE_REG(par, PM3ScissorMinXY,
  492. ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
  493. PM3_WRITE_REG(par, PM3ScissorMaxXY,
  494. (((image->dy + image->height) & 0x0fff) << 16) |
  495. ((image->dx + image->width) & 0x0fff));
  496. PM3_WRITE_REG(par, PM3RectanglePosition,
  497. PM3RectanglePosition_XOffset(image->dx) |
  498. PM3RectanglePosition_YOffset(image->dy));
  499. PM3_WRITE_REG(par, PM3Render2D,
  500. PM3Render2D_XPositive |
  501. PM3Render2D_YPositive |
  502. PM3Render2D_Operation_SyncOnBitMask |
  503. PM3Render2D_SpanOperation |
  504. PM3Render2D_Width(image->width) |
  505. PM3Render2D_Height(image->height));
  506. while (height--) {
  507. int width = ((image->width + 7) >> 3)
  508. + info->pixmap.scan_align - 1;
  509. width >>= 2;
  510. while (width >= PM3_FIFO_SIZE) {
  511. int i = PM3_FIFO_SIZE - 1;
  512. PM3_WAIT(par, PM3_FIFO_SIZE);
  513. while (i--) {
  514. PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
  515. src++;
  516. }
  517. width -= PM3_FIFO_SIZE - 1;
  518. }
  519. PM3_WAIT(par, width + 1);
  520. while (width--) {
  521. PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
  522. src++;
  523. }
  524. }
  525. }
  526. /* end of acceleration functions */
  527. /*
  528. * Hardware Cursor support.
  529. */
  530. static const u8 cursor_bits_lookup[16] = {
  531. 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
  532. 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
  533. };
  534. static int pm3fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  535. {
  536. struct pm3_par *par = info->par;
  537. u8 mode;
  538. if (!hwcursor)
  539. return -EINVAL; /* just to force soft_cursor() call */
  540. /* Too large of a cursor or wrong bpp :-( */
  541. if (cursor->image.width > 64 ||
  542. cursor->image.height > 64 ||
  543. cursor->image.depth > 1)
  544. return -EINVAL;
  545. mode = PM3RD_CursorMode_TYPE_X;
  546. if (cursor->enable)
  547. mode |= PM3RD_CursorMode_CURSOR_ENABLE;
  548. PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
  549. /*
  550. * If the cursor is not be changed this means either we want the
  551. * current cursor state (if enable is set) or we want to query what
  552. * we can do with the cursor (if enable is not set)
  553. */
  554. if (!cursor->set)
  555. return 0;
  556. if (cursor->set & FB_CUR_SETPOS) {
  557. int x = cursor->image.dx - info->var.xoffset;
  558. int y = cursor->image.dy - info->var.yoffset;
  559. PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
  560. PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
  561. PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
  562. PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
  563. }
  564. if (cursor->set & FB_CUR_SETHOT) {
  565. PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
  566. cursor->hot.x & 0x3f);
  567. PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
  568. cursor->hot.y & 0x3f);
  569. }
  570. if (cursor->set & FB_CUR_SETCMAP) {
  571. u32 fg_idx = cursor->image.fg_color;
  572. u32 bg_idx = cursor->image.bg_color;
  573. struct fb_cmap cmap = info->cmap;
  574. /* the X11 driver says one should use these color registers */
  575. PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
  576. cmap.red[fg_idx] >> 8 );
  577. PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
  578. cmap.green[fg_idx] >> 8 );
  579. PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
  580. cmap.blue[fg_idx] >> 8 );
  581. PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
  582. cmap.red[bg_idx] >> 8 );
  583. PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
  584. cmap.green[bg_idx] >> 8 );
  585. PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
  586. cmap.blue[bg_idx] >> 8 );
  587. }
  588. if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
  589. u8 *bitmap = (u8 *)cursor->image.data;
  590. u8 *mask = (u8 *)cursor->mask;
  591. int i;
  592. int pos = PM3RD_CursorPattern(0);
  593. for (i = 0; i < cursor->image.height; i++) {
  594. int j = (cursor->image.width + 7) >> 3;
  595. int k = 8 - j;
  596. for (; j > 0; j--) {
  597. u8 data = *bitmap ^ *mask;
  598. if (cursor->rop == ROP_COPY)
  599. data = *mask & *bitmap;
  600. /* Upper 4 bits of bitmap data */
  601. PM3_WRITE_DAC_REG(par, pos++,
  602. cursor_bits_lookup[data >> 4] |
  603. (cursor_bits_lookup[*mask >> 4] << 1));
  604. /* Lower 4 bits of bitmap */
  605. PM3_WRITE_DAC_REG(par, pos++,
  606. cursor_bits_lookup[data & 0xf] |
  607. (cursor_bits_lookup[*mask & 0xf] << 1));
  608. bitmap++;
  609. mask++;
  610. }
  611. for (; k > 0; k--) {
  612. PM3_WRITE_DAC_REG(par, pos++, 0);
  613. PM3_WRITE_DAC_REG(par, pos++, 0);
  614. }
  615. }
  616. while (pos < PM3RD_CursorPattern(1024))
  617. PM3_WRITE_DAC_REG(par, pos++, 0);
  618. }
  619. return 0;
  620. }
  621. /* write the mode to registers */
  622. static void pm3fb_write_mode(struct fb_info *info)
  623. {
  624. struct pm3_par *par = info->par;
  625. char tempsync = 0x00;
  626. char tempmisc = 0x00;
  627. const u32 hsstart = info->var.right_margin;
  628. const u32 hsend = hsstart + info->var.hsync_len;
  629. const u32 hbend = hsend + info->var.left_margin;
  630. const u32 xres = (info->var.xres + 31) & ~31;
  631. const u32 htotal = xres + hbend;
  632. const u32 vsstart = info->var.lower_margin;
  633. const u32 vsend = vsstart + info->var.vsync_len;
  634. const u32 vbend = vsend + info->var.upper_margin;
  635. const u32 vtotal = info->var.yres + vbend;
  636. const u32 width = (info->var.xres_virtual + 7) & ~7;
  637. const unsigned bpp = info->var.bits_per_pixel;
  638. PM3_WAIT(par, 20);
  639. PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
  640. PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
  641. PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
  642. PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
  643. PM3_WRITE_REG(par, PM3HTotal,
  644. pm3fb_shift_bpp(bpp, htotal - 1));
  645. PM3_WRITE_REG(par, PM3HsEnd,
  646. pm3fb_shift_bpp(bpp, hsend));
  647. PM3_WRITE_REG(par, PM3HsStart,
  648. pm3fb_shift_bpp(bpp, hsstart));
  649. PM3_WRITE_REG(par, PM3HbEnd,
  650. pm3fb_shift_bpp(bpp, hbend));
  651. PM3_WRITE_REG(par, PM3HgEnd,
  652. pm3fb_shift_bpp(bpp, hbend));
  653. PM3_WRITE_REG(par, PM3ScreenStride,
  654. pm3fb_shift_bpp(bpp, width));
  655. PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
  656. PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
  657. PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
  658. PM3_WRITE_REG(par, PM3VbEnd, vbend);
  659. switch (bpp) {
  660. case 8:
  661. PM3_WRITE_REG(par, PM3ByAperture1Mode,
  662. PM3ByApertureMode_PIXELSIZE_8BIT);
  663. PM3_WRITE_REG(par, PM3ByAperture2Mode,
  664. PM3ByApertureMode_PIXELSIZE_8BIT);
  665. break;
  666. case 16:
  667. #ifndef __BIG_ENDIAN
  668. PM3_WRITE_REG(par, PM3ByAperture1Mode,
  669. PM3ByApertureMode_PIXELSIZE_16BIT);
  670. PM3_WRITE_REG(par, PM3ByAperture2Mode,
  671. PM3ByApertureMode_PIXELSIZE_16BIT);
  672. #else
  673. PM3_WRITE_REG(par, PM3ByAperture1Mode,
  674. PM3ByApertureMode_PIXELSIZE_16BIT |
  675. PM3ByApertureMode_BYTESWAP_BADC);
  676. PM3_WRITE_REG(par, PM3ByAperture2Mode,
  677. PM3ByApertureMode_PIXELSIZE_16BIT |
  678. PM3ByApertureMode_BYTESWAP_BADC);
  679. #endif /* ! __BIG_ENDIAN */
  680. break;
  681. case 32:
  682. #ifndef __BIG_ENDIAN
  683. PM3_WRITE_REG(par, PM3ByAperture1Mode,
  684. PM3ByApertureMode_PIXELSIZE_32BIT);
  685. PM3_WRITE_REG(par, PM3ByAperture2Mode,
  686. PM3ByApertureMode_PIXELSIZE_32BIT);
  687. #else
  688. PM3_WRITE_REG(par, PM3ByAperture1Mode,
  689. PM3ByApertureMode_PIXELSIZE_32BIT |
  690. PM3ByApertureMode_BYTESWAP_DCBA);
  691. PM3_WRITE_REG(par, PM3ByAperture2Mode,
  692. PM3ByApertureMode_PIXELSIZE_32BIT |
  693. PM3ByApertureMode_BYTESWAP_DCBA);
  694. #endif /* ! __BIG_ENDIAN */
  695. break;
  696. default:
  697. DPRINTK("Unsupported depth %d\n", bpp);
  698. break;
  699. }
  700. /*
  701. * Oxygen VX1 - it appears that setting PM3VideoControl and
  702. * then PM3RD_SyncControl to the same SYNC settings undoes
  703. * any net change - they seem to xor together. Only set the
  704. * sync options in PM3RD_SyncControl. --rmk
  705. */
  706. {
  707. unsigned int video = par->video;
  708. video &= ~(PM3VideoControl_HSYNC_MASK |
  709. PM3VideoControl_VSYNC_MASK);
  710. video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
  711. PM3VideoControl_VSYNC_ACTIVE_HIGH;
  712. PM3_WRITE_REG(par, PM3VideoControl, video);
  713. }
  714. PM3_WRITE_REG(par, PM3VClkCtl,
  715. (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
  716. PM3_WRITE_REG(par, PM3ScreenBase, par->base);
  717. PM3_WRITE_REG(par, PM3ChipConfig,
  718. (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
  719. wmb();
  720. {
  721. unsigned char m; /* ClkPreScale */
  722. unsigned char n; /* ClkFeedBackScale */
  723. unsigned char p; /* ClkPostScale */
  724. unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
  725. (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
  726. DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
  727. pixclock, (int) m, (int) n, (int) p);
  728. PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
  729. PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
  730. PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
  731. }
  732. /*
  733. PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
  734. */
  735. /*
  736. PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
  737. */
  738. if ((par->video & PM3VideoControl_HSYNC_MASK) ==
  739. PM3VideoControl_HSYNC_ACTIVE_HIGH)
  740. tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
  741. if ((par->video & PM3VideoControl_VSYNC_MASK) ==
  742. PM3VideoControl_VSYNC_ACTIVE_HIGH)
  743. tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
  744. PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
  745. DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
  746. PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
  747. switch (pm3fb_depth(&info->var)) {
  748. case 8:
  749. PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
  750. PM3RD_PixelSize_8_BIT_PIXELS);
  751. PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
  752. PM3RD_ColorFormat_CI8_COLOR |
  753. PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
  754. tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
  755. break;
  756. case 12:
  757. PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
  758. PM3RD_PixelSize_16_BIT_PIXELS);
  759. PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
  760. PM3RD_ColorFormat_4444_COLOR |
  761. PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
  762. PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
  763. tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
  764. PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
  765. break;
  766. case 15:
  767. PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
  768. PM3RD_PixelSize_16_BIT_PIXELS);
  769. PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
  770. PM3RD_ColorFormat_5551_FRONT_COLOR |
  771. PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
  772. PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
  773. tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
  774. PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
  775. break;
  776. case 16:
  777. PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
  778. PM3RD_PixelSize_16_BIT_PIXELS);
  779. PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
  780. PM3RD_ColorFormat_565_FRONT_COLOR |
  781. PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
  782. PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
  783. tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
  784. PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
  785. break;
  786. case 32:
  787. PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
  788. PM3RD_PixelSize_32_BIT_PIXELS);
  789. PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
  790. PM3RD_ColorFormat_8888_COLOR |
  791. PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
  792. tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
  793. PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
  794. break;
  795. }
  796. PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
  797. }
  798. /*
  799. * hardware independent functions
  800. */
  801. static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  802. {
  803. u32 lpitch;
  804. unsigned bpp = var->red.length + var->green.length
  805. + var->blue.length + var->transp.length;
  806. if (bpp != var->bits_per_pixel) {
  807. /* set predefined mode for bits_per_pixel settings */
  808. switch (var->bits_per_pixel) {
  809. case 8:
  810. var->red.length = 8;
  811. var->green.length = 8;
  812. var->blue.length = 8;
  813. var->red.offset = 0;
  814. var->green.offset = 0;
  815. var->blue.offset = 0;
  816. var->transp.offset = 0;
  817. var->transp.length = 0;
  818. break;
  819. case 16:
  820. var->red.length = 5;
  821. var->blue.length = 5;
  822. var->green.length = 6;
  823. var->transp.length = 0;
  824. break;
  825. case 32:
  826. var->red.length = 8;
  827. var->green.length = 8;
  828. var->blue.length = 8;
  829. var->transp.length = 8;
  830. break;
  831. default:
  832. DPRINTK("depth not supported: %u\n",
  833. var->bits_per_pixel);
  834. return -EINVAL;
  835. }
  836. }
  837. /* it is assumed BGRA order */
  838. if (var->bits_per_pixel > 8 ) {
  839. var->blue.offset = 0;
  840. var->green.offset = var->blue.length;
  841. var->red.offset = var->green.offset + var->green.length;
  842. var->transp.offset = var->red.offset + var->red.length;
  843. }
  844. var->height = -1;
  845. var->width = -1;
  846. if (var->xres != var->xres_virtual) {
  847. DPRINTK("virtual x resolution != "
  848. "physical x resolution not supported\n");
  849. return -EINVAL;
  850. }
  851. if (var->yres > var->yres_virtual) {
  852. DPRINTK("virtual y resolution < "
  853. "physical y resolution not possible\n");
  854. return -EINVAL;
  855. }
  856. if (var->xoffset) {
  857. DPRINTK("xoffset not supported\n");
  858. return -EINVAL;
  859. }
  860. if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  861. DPRINTK("interlace not supported\n");
  862. return -EINVAL;
  863. }
  864. var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
  865. lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
  866. if (var->xres < 200 || var->xres > 2048) {
  867. DPRINTK("width not supported: %u\n", var->xres);
  868. return -EINVAL;
  869. }
  870. if (var->yres < 200 || var->yres > 4095) {
  871. DPRINTK("height not supported: %u\n", var->yres);
  872. return -EINVAL;
  873. }
  874. if (lpitch * var->yres_virtual > info->fix.smem_len) {
  875. DPRINTK("no memory for screen (%ux%ux%u)\n",
  876. var->xres, var->yres_virtual, var->bits_per_pixel);
  877. return -EINVAL;
  878. }
  879. if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
  880. DPRINTK("pixclock too high (%ldKHz)\n",
  881. PICOS2KHZ(var->pixclock));
  882. return -EINVAL;
  883. }
  884. var->accel_flags = 0; /* Can't mmap if this is on */
  885. DPRINTK("Checking graphics mode at %dx%d depth %d\n",
  886. var->xres, var->yres, var->bits_per_pixel);
  887. return 0;
  888. }
  889. static int pm3fb_set_par(struct fb_info *info)
  890. {
  891. struct pm3_par *par = info->par;
  892. const u32 xres = (info->var.xres + 31) & ~31;
  893. const unsigned bpp = info->var.bits_per_pixel;
  894. par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
  895. + info->var.xoffset);
  896. par->video = 0;
  897. if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
  898. par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
  899. else
  900. par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
  901. if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
  902. par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
  903. else
  904. par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
  905. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
  906. par->video |= PM3VideoControl_LINE_DOUBLE_ON;
  907. if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
  908. par->video |= PM3VideoControl_ENABLE;
  909. else
  910. DPRINTK("PM3Video disabled\n");
  911. switch (bpp) {
  912. case 8:
  913. par->video |= PM3VideoControl_PIXELSIZE_8BIT;
  914. break;
  915. case 16:
  916. par->video |= PM3VideoControl_PIXELSIZE_16BIT;
  917. break;
  918. case 32:
  919. par->video |= PM3VideoControl_PIXELSIZE_32BIT;
  920. break;
  921. default:
  922. DPRINTK("Unsupported depth\n");
  923. break;
  924. }
  925. info->fix.visual =
  926. (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  927. info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp;
  928. /* pm3fb_clear_memory(info, 0);*/
  929. pm3fb_clear_colormap(par, 0, 0, 0);
  930. PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
  931. pm3fb_init_engine(info);
  932. pm3fb_write_mode(info);
  933. return 0;
  934. }
  935. static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  936. unsigned blue, unsigned transp,
  937. struct fb_info *info)
  938. {
  939. struct pm3_par *par = info->par;
  940. if (regno >= 256) /* no. of hw registers */
  941. return -EINVAL;
  942. /* grayscale works only partially under directcolor */
  943. /* grayscale = 0.30*R + 0.59*G + 0.11*B */
  944. if (info->var.grayscale)
  945. red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
  946. /* Directcolor:
  947. * var->{color}.offset contains start of bitfield
  948. * var->{color}.length contains length of bitfield
  949. * {hardwarespecific} contains width of DAC
  950. * pseudo_palette[X] is programmed to (X << red.offset) |
  951. * (X << green.offset) |
  952. * (X << blue.offset)
  953. * RAMDAC[X] is programmed to (red, green, blue)
  954. * color depth = SUM(var->{color}.length)
  955. *
  956. * Pseudocolor:
  957. * var->{color}.offset is 0
  958. * var->{color}.length contains width of DAC or the number
  959. * of unique colors available (color depth)
  960. * pseudo_palette is not used
  961. * RAMDAC[X] is programmed to (red, green, blue)
  962. * color depth = var->{color}.length
  963. */
  964. /*
  965. * This is the point where the color is converted to something that
  966. * is acceptable by the hardware.
  967. */
  968. #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
  969. red = CNVT_TOHW(red, info->var.red.length);
  970. green = CNVT_TOHW(green, info->var.green.length);
  971. blue = CNVT_TOHW(blue, info->var.blue.length);
  972. transp = CNVT_TOHW(transp, info->var.transp.length);
  973. #undef CNVT_TOHW
  974. if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
  975. info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
  976. u32 v;
  977. if (regno >= 16)
  978. return -EINVAL;
  979. v = (red << info->var.red.offset) |
  980. (green << info->var.green.offset) |
  981. (blue << info->var.blue.offset) |
  982. (transp << info->var.transp.offset);
  983. switch (info->var.bits_per_pixel) {
  984. case 8:
  985. break;
  986. case 16:
  987. case 32:
  988. ((u32 *)(info->pseudo_palette))[regno] = v;
  989. break;
  990. }
  991. return 0;
  992. } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
  993. pm3fb_set_color(par, regno, red, green, blue);
  994. return 0;
  995. }
  996. static int pm3fb_pan_display(struct fb_var_screeninfo *var,
  997. struct fb_info *info)
  998. {
  999. struct pm3_par *par = info->par;
  1000. const u32 xres = (info->var.xres + 31) & ~31;
  1001. par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
  1002. (var->yoffset * xres)
  1003. + var->xoffset);
  1004. PM3_WAIT(par, 1);
  1005. PM3_WRITE_REG(par, PM3ScreenBase, par->base);
  1006. return 0;
  1007. }
  1008. static int pm3fb_blank(int blank_mode, struct fb_info *info)
  1009. {
  1010. struct pm3_par *par = info->par;
  1011. u32 video = par->video;
  1012. /*
  1013. * Oxygen VX1 - it appears that setting PM3VideoControl and
  1014. * then PM3RD_SyncControl to the same SYNC settings undoes
  1015. * any net change - they seem to xor together. Only set the
  1016. * sync options in PM3RD_SyncControl. --rmk
  1017. */
  1018. video &= ~(PM3VideoControl_HSYNC_MASK |
  1019. PM3VideoControl_VSYNC_MASK);
  1020. video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
  1021. PM3VideoControl_VSYNC_ACTIVE_HIGH;
  1022. switch (blank_mode) {
  1023. case FB_BLANK_UNBLANK:
  1024. video |= PM3VideoControl_ENABLE;
  1025. break;
  1026. case FB_BLANK_NORMAL:
  1027. video &= ~PM3VideoControl_ENABLE;
  1028. break;
  1029. case FB_BLANK_HSYNC_SUSPEND:
  1030. video &= ~(PM3VideoControl_HSYNC_MASK |
  1031. PM3VideoControl_BLANK_ACTIVE_LOW);
  1032. break;
  1033. case FB_BLANK_VSYNC_SUSPEND:
  1034. video &= ~(PM3VideoControl_VSYNC_MASK |
  1035. PM3VideoControl_BLANK_ACTIVE_LOW);
  1036. break;
  1037. case FB_BLANK_POWERDOWN:
  1038. video &= ~(PM3VideoControl_HSYNC_MASK |
  1039. PM3VideoControl_VSYNC_MASK |
  1040. PM3VideoControl_BLANK_ACTIVE_LOW);
  1041. break;
  1042. default:
  1043. DPRINTK("Unsupported blanking %d\n", blank_mode);
  1044. return 1;
  1045. }
  1046. PM3_WAIT(par, 1);
  1047. PM3_WRITE_REG(par, PM3VideoControl, video);
  1048. return 0;
  1049. }
  1050. /*
  1051. * Frame buffer operations
  1052. */
  1053. static const struct fb_ops pm3fb_ops = {
  1054. .owner = THIS_MODULE,
  1055. .fb_check_var = pm3fb_check_var,
  1056. .fb_set_par = pm3fb_set_par,
  1057. .fb_setcolreg = pm3fb_setcolreg,
  1058. .fb_pan_display = pm3fb_pan_display,
  1059. .fb_fillrect = pm3fb_fillrect,
  1060. .fb_copyarea = pm3fb_copyarea,
  1061. .fb_imageblit = pm3fb_imageblit,
  1062. .fb_blank = pm3fb_blank,
  1063. .fb_sync = pm3fb_sync,
  1064. .fb_cursor = pm3fb_cursor,
  1065. };
  1066. /* ------------------------------------------------------------------------- */
  1067. /*
  1068. * Initialization
  1069. */
  1070. /* mmio register are already mapped when this function is called */
  1071. /* the pm3fb_fix.smem_start is also set */
  1072. static unsigned long pm3fb_size_memory(struct pm3_par *par)
  1073. {
  1074. unsigned long memsize = 0;
  1075. unsigned long tempBypass, i, temp1, temp2;
  1076. unsigned char __iomem *screen_mem;
  1077. pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
  1078. /* Linear frame buffer - request region and map it. */
  1079. if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
  1080. "pm3fb smem")) {
  1081. printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
  1082. return 0;
  1083. }
  1084. screen_mem =
  1085. ioremap(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
  1086. if (!screen_mem) {
  1087. printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
  1088. release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
  1089. return 0;
  1090. }
  1091. /* TODO: card-specific stuff, *before* accessing *any* FB memory */
  1092. /* For Appian Jeronimo 2000 board second head */
  1093. tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
  1094. DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
  1095. PM3_WAIT(par, 1);
  1096. PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
  1097. /* pm3 split up memory, replicates, and do a lot of
  1098. * nasty stuff IMHO ;-)
  1099. */
  1100. for (i = 0; i < 32; i++) {
  1101. fb_writel(i * 0x00345678,
  1102. (screen_mem + (i * 1048576)));
  1103. mb();
  1104. temp1 = fb_readl((screen_mem + (i * 1048576)));
  1105. /* Let's check for wrapover, write will fail at 16MB boundary */
  1106. if (temp1 == (i * 0x00345678))
  1107. memsize = i;
  1108. else
  1109. break;
  1110. }
  1111. DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
  1112. if (memsize + 1 == i) {
  1113. for (i = 0; i < 32; i++) {
  1114. /* Clear first 32MB ; 0 is 0, no need to byteswap */
  1115. writel(0x0000000, (screen_mem + (i * 1048576)));
  1116. }
  1117. wmb();
  1118. for (i = 32; i < 64; i++) {
  1119. fb_writel(i * 0x00345678,
  1120. (screen_mem + (i * 1048576)));
  1121. mb();
  1122. temp1 =
  1123. fb_readl((screen_mem + (i * 1048576)));
  1124. temp2 =
  1125. fb_readl((screen_mem + ((i - 32) * 1048576)));
  1126. /* different value, different RAM... */
  1127. if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
  1128. memsize = i;
  1129. else
  1130. break;
  1131. }
  1132. }
  1133. DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
  1134. PM3_WAIT(par, 1);
  1135. PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
  1136. iounmap(screen_mem);
  1137. release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
  1138. memsize = 1048576 * (memsize + 1);
  1139. DPRINTK("Returning 0x%08lx bytes\n", memsize);
  1140. return memsize;
  1141. }
  1142. static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
  1143. {
  1144. struct fb_info *info;
  1145. struct pm3_par *par;
  1146. struct device *device = &dev->dev; /* for pci drivers */
  1147. int err;
  1148. int retval = -ENXIO;
  1149. err = pci_enable_device(dev);
  1150. if (err) {
  1151. printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
  1152. return err;
  1153. }
  1154. /*
  1155. * Dynamically allocate info and par
  1156. */
  1157. info = framebuffer_alloc(sizeof(struct pm3_par), device);
  1158. if (!info)
  1159. return -ENOMEM;
  1160. par = info->par;
  1161. /*
  1162. * Here we set the screen_base to the virtual memory address
  1163. * for the framebuffer.
  1164. */
  1165. pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
  1166. pm3fb_fix.mmio_len = PM3_REGS_SIZE;
  1167. #if defined(__BIG_ENDIAN)
  1168. pm3fb_fix.mmio_start += PM3_REGS_SIZE;
  1169. DPRINTK("Adjusting register base for big-endian.\n");
  1170. #endif
  1171. /* Registers - request region and map it. */
  1172. if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
  1173. "pm3fb regbase")) {
  1174. printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
  1175. goto err_exit_neither;
  1176. }
  1177. par->v_regs =
  1178. ioremap(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
  1179. if (!par->v_regs) {
  1180. printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
  1181. pm3fb_fix.id);
  1182. release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
  1183. goto err_exit_neither;
  1184. }
  1185. /* Linear frame buffer - request region and map it. */
  1186. pm3fb_fix.smem_start = pci_resource_start(dev, 1);
  1187. pm3fb_fix.smem_len = pm3fb_size_memory(par);
  1188. if (!pm3fb_fix.smem_len) {
  1189. printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
  1190. goto err_exit_mmio;
  1191. }
  1192. if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
  1193. "pm3fb smem")) {
  1194. printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
  1195. goto err_exit_mmio;
  1196. }
  1197. info->screen_base = ioremap_wc(pm3fb_fix.smem_start,
  1198. pm3fb_fix.smem_len);
  1199. if (!info->screen_base) {
  1200. printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
  1201. release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
  1202. goto err_exit_mmio;
  1203. }
  1204. info->screen_size = pm3fb_fix.smem_len;
  1205. if (!nomtrr)
  1206. par->wc_cookie = arch_phys_wc_add(pm3fb_fix.smem_start,
  1207. pm3fb_fix.smem_len);
  1208. info->fbops = &pm3fb_ops;
  1209. par->video = PM3_READ_REG(par, PM3VideoControl);
  1210. info->fix = pm3fb_fix;
  1211. info->pseudo_palette = par->palette;
  1212. info->flags = FBINFO_DEFAULT |
  1213. FBINFO_HWACCEL_XPAN |
  1214. FBINFO_HWACCEL_YPAN |
  1215. FBINFO_HWACCEL_COPYAREA |
  1216. FBINFO_HWACCEL_IMAGEBLIT |
  1217. FBINFO_HWACCEL_FILLRECT;
  1218. if (noaccel) {
  1219. printk(KERN_DEBUG "disabling acceleration\n");
  1220. info->flags |= FBINFO_HWACCEL_DISABLED;
  1221. }
  1222. info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
  1223. if (!info->pixmap.addr) {
  1224. retval = -ENOMEM;
  1225. goto err_exit_pixmap;
  1226. }
  1227. info->pixmap.size = PM3_PIXMAP_SIZE;
  1228. info->pixmap.buf_align = 4;
  1229. info->pixmap.scan_align = 4;
  1230. info->pixmap.access_align = 32;
  1231. info->pixmap.flags = FB_PIXMAP_SYSTEM;
  1232. /*
  1233. * This should give a reasonable default video mode. The following is
  1234. * done when we can set a video mode.
  1235. */
  1236. if (!mode_option)
  1237. mode_option = "640x480@60";
  1238. retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
  1239. if (!retval || retval == 4) {
  1240. retval = -EINVAL;
  1241. goto err_exit_both;
  1242. }
  1243. if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
  1244. retval = -ENOMEM;
  1245. goto err_exit_both;
  1246. }
  1247. /*
  1248. * For drivers that can...
  1249. */
  1250. pm3fb_check_var(&info->var, info);
  1251. if (register_framebuffer(info) < 0) {
  1252. retval = -EINVAL;
  1253. goto err_exit_all;
  1254. }
  1255. fb_info(info, "%s frame buffer device\n", info->fix.id);
  1256. pci_set_drvdata(dev, info);
  1257. return 0;
  1258. err_exit_all:
  1259. fb_dealloc_cmap(&info->cmap);
  1260. err_exit_both:
  1261. kfree(info->pixmap.addr);
  1262. err_exit_pixmap:
  1263. iounmap(info->screen_base);
  1264. release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
  1265. err_exit_mmio:
  1266. iounmap(par->v_regs);
  1267. release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
  1268. err_exit_neither:
  1269. framebuffer_release(info);
  1270. return retval;
  1271. }
  1272. /*
  1273. * Cleanup
  1274. */
  1275. static void pm3fb_remove(struct pci_dev *dev)
  1276. {
  1277. struct fb_info *info = pci_get_drvdata(dev);
  1278. if (info) {
  1279. struct fb_fix_screeninfo *fix = &info->fix;
  1280. struct pm3_par *par = info->par;
  1281. unregister_framebuffer(info);
  1282. fb_dealloc_cmap(&info->cmap);
  1283. arch_phys_wc_del(par->wc_cookie);
  1284. iounmap(info->screen_base);
  1285. release_mem_region(fix->smem_start, fix->smem_len);
  1286. iounmap(par->v_regs);
  1287. release_mem_region(fix->mmio_start, fix->mmio_len);
  1288. kfree(info->pixmap.addr);
  1289. framebuffer_release(info);
  1290. }
  1291. }
  1292. static const struct pci_device_id pm3fb_id_table[] = {
  1293. { PCI_VENDOR_ID_3DLABS, 0x0a,
  1294. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1295. { 0, }
  1296. };
  1297. /* For PCI drivers */
  1298. static struct pci_driver pm3fb_driver = {
  1299. .name = "pm3fb",
  1300. .id_table = pm3fb_id_table,
  1301. .probe = pm3fb_probe,
  1302. .remove = pm3fb_remove,
  1303. };
  1304. MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
  1305. #ifndef MODULE
  1306. /*
  1307. * Setup
  1308. */
  1309. /*
  1310. * Only necessary if your driver takes special options,
  1311. * otherwise we fall back on the generic fb_setup().
  1312. */
  1313. static int __init pm3fb_setup(char *options)
  1314. {
  1315. char *this_opt;
  1316. /* Parse user specified options (`video=pm3fb:') */
  1317. if (!options || !*options)
  1318. return 0;
  1319. while ((this_opt = strsep(&options, ",")) != NULL) {
  1320. if (!*this_opt)
  1321. continue;
  1322. else if (!strncmp(this_opt, "noaccel", 7))
  1323. noaccel = 1;
  1324. else if (!strncmp(this_opt, "hwcursor=", 9))
  1325. hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
  1326. else if (!strncmp(this_opt, "nomtrr", 6))
  1327. nomtrr = 1;
  1328. else
  1329. mode_option = this_opt;
  1330. }
  1331. return 0;
  1332. }
  1333. #endif /* MODULE */
  1334. static int __init pm3fb_init(void)
  1335. {
  1336. /*
  1337. * For kernel boot options (in 'video=pm3fb:<options>' format)
  1338. */
  1339. #ifndef MODULE
  1340. char *option = NULL;
  1341. if (fb_get_options("pm3fb", &option))
  1342. return -ENODEV;
  1343. pm3fb_setup(option);
  1344. #endif
  1345. return pci_register_driver(&pm3fb_driver);
  1346. }
  1347. #ifdef MODULE
  1348. static void __exit pm3fb_exit(void)
  1349. {
  1350. pci_unregister_driver(&pm3fb_driver);
  1351. }
  1352. module_exit(pm3fb_exit);
  1353. #endif
  1354. module_init(pm3fb_init);
  1355. module_param(mode_option, charp, 0);
  1356. MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
  1357. module_param(noaccel, bool, 0);
  1358. MODULE_PARM_DESC(noaccel, "Disable acceleration");
  1359. module_param(hwcursor, int, 0644);
  1360. MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
  1361. "(1=enable, 0=disable, default=1)");
  1362. module_param(nomtrr, bool, 0);
  1363. MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
  1364. MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
  1365. MODULE_LICENSE("GPL");