mx3fb.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2008
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. *
  6. * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/sched.h>
  12. #include <linux/errno.h>
  13. #include <linux/string.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/slab.h>
  16. #include <linux/fb.h>
  17. #include <linux/delay.h>
  18. #include <linux/init.h>
  19. #include <linux/ioport.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/dmaengine.h>
  22. #include <linux/console.h>
  23. #include <linux/clk.h>
  24. #include <linux/mutex.h>
  25. #include <linux/dma/ipu-dma.h>
  26. #include <linux/backlight.h>
  27. #include <linux/platform_data/dma-imx.h>
  28. #include <linux/platform_data/video-mx3fb.h>
  29. #include <asm/io.h>
  30. #include <linux/uaccess.h>
  31. #define MX3FB_NAME "mx3_sdc_fb"
  32. #define MX3FB_REG_OFFSET 0xB4
  33. /* SDC Registers */
  34. #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
  35. #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
  36. #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
  37. #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
  38. #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
  39. #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
  40. #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
  41. #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
  42. #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
  43. #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
  44. #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
  45. /* Register bits */
  46. #define SDC_COM_TFT_COLOR 0x00000001UL
  47. #define SDC_COM_FG_EN 0x00000010UL
  48. #define SDC_COM_GWSEL 0x00000020UL
  49. #define SDC_COM_GLB_A 0x00000040UL
  50. #define SDC_COM_KEY_COLOR_G 0x00000080UL
  51. #define SDC_COM_BG_EN 0x00000200UL
  52. #define SDC_COM_SHARP 0x00001000UL
  53. #define SDC_V_SYNC_WIDTH_L 0x00000001UL
  54. /* Display Interface registers */
  55. #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
  56. #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
  57. #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
  58. #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
  59. #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
  60. #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
  61. #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
  62. #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
  63. #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
  64. #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
  65. #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
  66. #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
  67. #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
  68. #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
  69. #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
  70. #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
  71. #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
  72. #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
  73. #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
  74. #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
  75. #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
  76. #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
  77. #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
  78. #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
  79. #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
  80. #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
  81. #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
  82. #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
  83. #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
  84. #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
  85. #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
  86. #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
  87. #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
  88. #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
  89. #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
  90. #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
  91. #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
  92. #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
  93. #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
  94. /* DI_DISP_SIG_POL bits */
  95. #define DI_D3_VSYNC_POL_SHIFT 28
  96. #define DI_D3_HSYNC_POL_SHIFT 27
  97. #define DI_D3_DRDY_SHARP_POL_SHIFT 26
  98. #define DI_D3_CLK_POL_SHIFT 25
  99. #define DI_D3_DATA_POL_SHIFT 24
  100. /* DI_DISP_IF_CONF bits */
  101. #define DI_D3_CLK_IDLE_SHIFT 26
  102. #define DI_D3_CLK_SEL_SHIFT 25
  103. #define DI_D3_DATAMSK_SHIFT 24
  104. enum ipu_panel {
  105. IPU_PANEL_SHARP_TFT,
  106. IPU_PANEL_TFT,
  107. };
  108. struct ipu_di_signal_cfg {
  109. unsigned datamask_en:1;
  110. unsigned clksel_en:1;
  111. unsigned clkidle_en:1;
  112. unsigned data_pol:1; /* true = inverted */
  113. unsigned clk_pol:1; /* true = rising edge */
  114. unsigned enable_pol:1;
  115. unsigned Hsync_pol:1; /* true = active high */
  116. unsigned Vsync_pol:1;
  117. };
  118. static const struct fb_videomode mx3fb_modedb[] = {
  119. {
  120. /* 240x320 @ 60 Hz */
  121. .name = "Sharp-QVGA",
  122. .refresh = 60,
  123. .xres = 240,
  124. .yres = 320,
  125. .pixclock = 185925,
  126. .left_margin = 9,
  127. .right_margin = 16,
  128. .upper_margin = 7,
  129. .lower_margin = 9,
  130. .hsync_len = 1,
  131. .vsync_len = 1,
  132. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
  133. FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
  134. FB_SYNC_CLK_IDLE_EN,
  135. .vmode = FB_VMODE_NONINTERLACED,
  136. .flag = 0,
  137. }, {
  138. /* 240x33 @ 60 Hz */
  139. .name = "Sharp-CLI",
  140. .refresh = 60,
  141. .xres = 240,
  142. .yres = 33,
  143. .pixclock = 185925,
  144. .left_margin = 9,
  145. .right_margin = 16,
  146. .upper_margin = 7,
  147. .lower_margin = 9 + 287,
  148. .hsync_len = 1,
  149. .vsync_len = 1,
  150. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
  151. FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
  152. FB_SYNC_CLK_IDLE_EN,
  153. .vmode = FB_VMODE_NONINTERLACED,
  154. .flag = 0,
  155. }, {
  156. /* 640x480 @ 60 Hz */
  157. .name = "NEC-VGA",
  158. .refresh = 60,
  159. .xres = 640,
  160. .yres = 480,
  161. .pixclock = 38255,
  162. .left_margin = 144,
  163. .right_margin = 0,
  164. .upper_margin = 34,
  165. .lower_margin = 40,
  166. .hsync_len = 1,
  167. .vsync_len = 1,
  168. .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
  169. .vmode = FB_VMODE_NONINTERLACED,
  170. .flag = 0,
  171. }, {
  172. /* NTSC TV output */
  173. .name = "TV-NTSC",
  174. .refresh = 60,
  175. .xres = 640,
  176. .yres = 480,
  177. .pixclock = 37538,
  178. .left_margin = 38,
  179. .right_margin = 858 - 640 - 38 - 3,
  180. .upper_margin = 36,
  181. .lower_margin = 518 - 480 - 36 - 1,
  182. .hsync_len = 3,
  183. .vsync_len = 1,
  184. .sync = 0,
  185. .vmode = FB_VMODE_NONINTERLACED,
  186. .flag = 0,
  187. }, {
  188. /* PAL TV output */
  189. .name = "TV-PAL",
  190. .refresh = 50,
  191. .xres = 640,
  192. .yres = 480,
  193. .pixclock = 37538,
  194. .left_margin = 38,
  195. .right_margin = 960 - 640 - 38 - 32,
  196. .upper_margin = 32,
  197. .lower_margin = 555 - 480 - 32 - 3,
  198. .hsync_len = 32,
  199. .vsync_len = 3,
  200. .sync = 0,
  201. .vmode = FB_VMODE_NONINTERLACED,
  202. .flag = 0,
  203. }, {
  204. /* TV output VGA mode, 640x480 @ 65 Hz */
  205. .name = "TV-VGA",
  206. .refresh = 60,
  207. .xres = 640,
  208. .yres = 480,
  209. .pixclock = 40574,
  210. .left_margin = 35,
  211. .right_margin = 45,
  212. .upper_margin = 9,
  213. .lower_margin = 1,
  214. .hsync_len = 46,
  215. .vsync_len = 5,
  216. .sync = 0,
  217. .vmode = FB_VMODE_NONINTERLACED,
  218. .flag = 0,
  219. },
  220. };
  221. struct mx3fb_data {
  222. struct fb_info *fbi;
  223. int backlight_level;
  224. void __iomem *reg_base;
  225. spinlock_t lock;
  226. struct device *dev;
  227. struct backlight_device *bl;
  228. uint32_t h_start_width;
  229. uint32_t v_start_width;
  230. enum disp_data_mapping disp_data_fmt;
  231. };
  232. struct dma_chan_request {
  233. struct mx3fb_data *mx3fb;
  234. enum ipu_channel id;
  235. };
  236. /* MX3 specific framebuffer information. */
  237. struct mx3fb_info {
  238. int blank;
  239. enum ipu_channel ipu_ch;
  240. uint32_t cur_ipu_buf;
  241. u32 pseudo_palette[16];
  242. struct completion flip_cmpl;
  243. struct mutex mutex; /* Protects fb-ops */
  244. struct mx3fb_data *mx3fb;
  245. struct idmac_channel *idmac_channel;
  246. struct dma_async_tx_descriptor *txd;
  247. dma_cookie_t cookie;
  248. struct scatterlist sg[2];
  249. struct fb_var_screeninfo cur_var; /* current var info */
  250. };
  251. static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value);
  252. static u32 sdc_get_brightness(struct mx3fb_data *mx3fb);
  253. static int mx3fb_bl_get_brightness(struct backlight_device *bl)
  254. {
  255. struct mx3fb_data *fbd = bl_get_data(bl);
  256. return sdc_get_brightness(fbd);
  257. }
  258. static int mx3fb_bl_update_status(struct backlight_device *bl)
  259. {
  260. struct mx3fb_data *fbd = bl_get_data(bl);
  261. int brightness = bl->props.brightness;
  262. if (bl->props.power != FB_BLANK_UNBLANK)
  263. brightness = 0;
  264. if (bl->props.fb_blank != FB_BLANK_UNBLANK)
  265. brightness = 0;
  266. fbd->backlight_level = (fbd->backlight_level & ~0xFF) | brightness;
  267. sdc_set_brightness(fbd, fbd->backlight_level);
  268. return 0;
  269. }
  270. static const struct backlight_ops mx3fb_lcdc_bl_ops = {
  271. .update_status = mx3fb_bl_update_status,
  272. .get_brightness = mx3fb_bl_get_brightness,
  273. };
  274. static void mx3fb_init_backlight(struct mx3fb_data *fbd)
  275. {
  276. struct backlight_properties props;
  277. struct backlight_device *bl;
  278. if (fbd->bl)
  279. return;
  280. memset(&props, 0, sizeof(struct backlight_properties));
  281. props.max_brightness = 0xff;
  282. props.type = BACKLIGHT_RAW;
  283. sdc_set_brightness(fbd, fbd->backlight_level);
  284. bl = backlight_device_register("mx3fb-bl", fbd->dev, fbd,
  285. &mx3fb_lcdc_bl_ops, &props);
  286. if (IS_ERR(bl)) {
  287. dev_err(fbd->dev, "error %ld on backlight register\n",
  288. PTR_ERR(bl));
  289. return;
  290. }
  291. fbd->bl = bl;
  292. bl->props.power = FB_BLANK_UNBLANK;
  293. bl->props.fb_blank = FB_BLANK_UNBLANK;
  294. bl->props.brightness = mx3fb_bl_get_brightness(bl);
  295. }
  296. static void mx3fb_exit_backlight(struct mx3fb_data *fbd)
  297. {
  298. backlight_device_unregister(fbd->bl);
  299. }
  300. static void mx3fb_dma_done(void *);
  301. /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
  302. static const char *fb_mode;
  303. static unsigned long default_bpp = 16;
  304. static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
  305. {
  306. return __raw_readl(mx3fb->reg_base + reg);
  307. }
  308. static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
  309. {
  310. __raw_writel(value, mx3fb->reg_base + reg);
  311. }
  312. struct di_mapping {
  313. uint32_t b0, b1, b2;
  314. };
  315. static const struct di_mapping di_mappings[] = {
  316. [IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f },
  317. [IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f },
  318. [IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 },
  319. };
  320. static void sdc_fb_init(struct mx3fb_info *fbi)
  321. {
  322. struct mx3fb_data *mx3fb = fbi->mx3fb;
  323. uint32_t reg;
  324. reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
  325. mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
  326. }
  327. /* Returns enabled flag before uninit */
  328. static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
  329. {
  330. struct mx3fb_data *mx3fb = fbi->mx3fb;
  331. uint32_t reg;
  332. reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
  333. mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
  334. return reg & SDC_COM_BG_EN;
  335. }
  336. static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
  337. {
  338. struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
  339. struct idmac_channel *ichan = mx3_fbi->idmac_channel;
  340. struct dma_chan *dma_chan = &ichan->dma_chan;
  341. unsigned long flags;
  342. dma_cookie_t cookie;
  343. if (mx3_fbi->txd)
  344. dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
  345. to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
  346. else
  347. dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
  348. /* This enables the channel */
  349. if (mx3_fbi->cookie < 0) {
  350. mx3_fbi->txd = dmaengine_prep_slave_sg(dma_chan,
  351. &mx3_fbi->sg[0], 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
  352. if (!mx3_fbi->txd) {
  353. dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
  354. dma_chan->chan_id);
  355. return;
  356. }
  357. mx3_fbi->txd->callback_param = mx3_fbi->txd;
  358. mx3_fbi->txd->callback = mx3fb_dma_done;
  359. cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
  360. dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
  361. mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
  362. } else {
  363. if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
  364. dev_err(mx3fb->dev, "Cannot enable channel %d\n",
  365. dma_chan->chan_id);
  366. return;
  367. }
  368. /* Just re-activate the same buffer */
  369. dma_async_issue_pending(dma_chan);
  370. cookie = mx3_fbi->cookie;
  371. dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
  372. mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
  373. }
  374. if (cookie >= 0) {
  375. spin_lock_irqsave(&mx3fb->lock, flags);
  376. sdc_fb_init(mx3_fbi);
  377. mx3_fbi->cookie = cookie;
  378. spin_unlock_irqrestore(&mx3fb->lock, flags);
  379. }
  380. /*
  381. * Attention! Without this msleep the channel keeps generating
  382. * interrupts. Next sdc_set_brightness() is going to be called
  383. * from mx3fb_blank().
  384. */
  385. msleep(2);
  386. }
  387. static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
  388. {
  389. struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
  390. uint32_t enabled;
  391. unsigned long flags;
  392. if (mx3_fbi->txd == NULL)
  393. return;
  394. spin_lock_irqsave(&mx3fb->lock, flags);
  395. enabled = sdc_fb_uninit(mx3_fbi);
  396. spin_unlock_irqrestore(&mx3fb->lock, flags);
  397. dmaengine_terminate_all(mx3_fbi->txd->chan);
  398. mx3_fbi->txd = NULL;
  399. mx3_fbi->cookie = -EINVAL;
  400. }
  401. /**
  402. * sdc_set_window_pos() - set window position of the respective plane.
  403. * @mx3fb: mx3fb context.
  404. * @channel: IPU DMAC channel ID.
  405. * @x_pos: X coordinate relative to the top left corner to place window at.
  406. * @y_pos: Y coordinate relative to the top left corner to place window at.
  407. * @return: 0 on success or negative error code on failure.
  408. */
  409. static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
  410. int16_t x_pos, int16_t y_pos)
  411. {
  412. if (channel != IDMAC_SDC_0)
  413. return -EINVAL;
  414. x_pos += mx3fb->h_start_width;
  415. y_pos += mx3fb->v_start_width;
  416. mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
  417. return 0;
  418. }
  419. /**
  420. * sdc_init_panel() - initialize a synchronous LCD panel.
  421. * @mx3fb: mx3fb context.
  422. * @panel: panel type.
  423. * @pixel_clk: desired pixel clock frequency in Hz.
  424. * @width: width of panel in pixels.
  425. * @height: height of panel in pixels.
  426. * @h_start_width: number of pixel clocks between the HSYNC signal pulse
  427. * and the start of valid data.
  428. * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
  429. * @h_end_width: number of pixel clocks between the end of valid data
  430. * and the HSYNC signal for next line.
  431. * @v_start_width: number of lines between the VSYNC signal pulse and the
  432. * start of valid data.
  433. * @v_sync_width: width of the VSYNC signal in units of lines
  434. * @v_end_width: number of lines between the end of valid data and the
  435. * VSYNC signal for next frame.
  436. * @sig: bitfield of signal polarities for LCD interface.
  437. * @return: 0 on success or negative error code on failure.
  438. */
  439. static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
  440. uint32_t pixel_clk,
  441. uint16_t width, uint16_t height,
  442. uint16_t h_start_width, uint16_t h_sync_width,
  443. uint16_t h_end_width, uint16_t v_start_width,
  444. uint16_t v_sync_width, uint16_t v_end_width,
  445. const struct ipu_di_signal_cfg *sig)
  446. {
  447. unsigned long lock_flags;
  448. uint32_t reg;
  449. uint32_t old_conf;
  450. uint32_t div;
  451. struct clk *ipu_clk;
  452. const struct di_mapping *map;
  453. dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
  454. if (v_sync_width == 0 || h_sync_width == 0)
  455. return -EINVAL;
  456. /* Init panel size and blanking periods */
  457. reg = ((uint32_t) (h_sync_width - 1) << 26) |
  458. ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
  459. mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
  460. #ifdef DEBUG
  461. printk(KERN_CONT " hor_conf %x,", reg);
  462. #endif
  463. reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
  464. ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
  465. mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
  466. #ifdef DEBUG
  467. printk(KERN_CONT " ver_conf %x\n", reg);
  468. #endif
  469. mx3fb->h_start_width = h_start_width;
  470. mx3fb->v_start_width = v_start_width;
  471. switch (panel) {
  472. case IPU_PANEL_SHARP_TFT:
  473. mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
  474. mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
  475. mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
  476. break;
  477. case IPU_PANEL_TFT:
  478. mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
  479. break;
  480. default:
  481. return -EINVAL;
  482. }
  483. /* Init clocking */
  484. /*
  485. * Calculate divider: fractional part is 4 bits so simply multiple by
  486. * 2^4 to get fractional part, as long as we stay under ~250MHz and on
  487. * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
  488. */
  489. ipu_clk = clk_get(mx3fb->dev, NULL);
  490. if (!IS_ERR(ipu_clk)) {
  491. div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
  492. clk_put(ipu_clk);
  493. } else {
  494. div = 0;
  495. }
  496. if (div < 0x40) { /* Divider less than 4 */
  497. dev_dbg(mx3fb->dev,
  498. "InitPanel() - Pixel clock divider less than 4\n");
  499. div = 0x40;
  500. }
  501. dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
  502. pixel_clk, div >> 4, (div & 7) * 125);
  503. spin_lock_irqsave(&mx3fb->lock, lock_flags);
  504. /*
  505. * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
  506. * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
  507. * debug. DISP3_IF_CLK_UP_WR is 0
  508. */
  509. mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
  510. /* DI settings */
  511. old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
  512. old_conf |= sig->datamask_en << DI_D3_DATAMSK_SHIFT |
  513. sig->clksel_en << DI_D3_CLK_SEL_SHIFT |
  514. sig->clkidle_en << DI_D3_CLK_IDLE_SHIFT;
  515. mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
  516. old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
  517. old_conf |= sig->data_pol << DI_D3_DATA_POL_SHIFT |
  518. sig->clk_pol << DI_D3_CLK_POL_SHIFT |
  519. sig->enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
  520. sig->Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
  521. sig->Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
  522. mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
  523. map = &di_mappings[mx3fb->disp_data_fmt];
  524. mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP);
  525. mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP);
  526. mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP);
  527. spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
  528. dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
  529. mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
  530. dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
  531. mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
  532. dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
  533. mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
  534. return 0;
  535. }
  536. /**
  537. * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
  538. * @mx3fb: mx3fb context.
  539. * @channel: IPU DMAC channel ID.
  540. * @enable: boolean to enable or disable color keyl.
  541. * @color_key: 24-bit RGB color to use as transparent color key.
  542. * @return: 0 on success or negative error code on failure.
  543. */
  544. static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
  545. bool enable, uint32_t color_key)
  546. {
  547. uint32_t reg, sdc_conf;
  548. unsigned long lock_flags;
  549. spin_lock_irqsave(&mx3fb->lock, lock_flags);
  550. sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
  551. if (channel == IDMAC_SDC_0)
  552. sdc_conf &= ~SDC_COM_GWSEL;
  553. else
  554. sdc_conf |= SDC_COM_GWSEL;
  555. if (enable) {
  556. reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
  557. mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
  558. SDC_GW_CTRL);
  559. sdc_conf |= SDC_COM_KEY_COLOR_G;
  560. } else {
  561. sdc_conf &= ~SDC_COM_KEY_COLOR_G;
  562. }
  563. mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
  564. spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
  565. return 0;
  566. }
  567. /**
  568. * sdc_set_global_alpha() - set global alpha blending modes.
  569. * @mx3fb: mx3fb context.
  570. * @enable: boolean to enable or disable global alpha blending. If disabled,
  571. * per pixel blending is used.
  572. * @alpha: global alpha value.
  573. * @return: 0 on success or negative error code on failure.
  574. */
  575. static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
  576. {
  577. uint32_t reg;
  578. unsigned long lock_flags;
  579. spin_lock_irqsave(&mx3fb->lock, lock_flags);
  580. if (enable) {
  581. reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
  582. mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
  583. reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
  584. mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
  585. } else {
  586. reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
  587. mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
  588. }
  589. spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
  590. return 0;
  591. }
  592. static u32 sdc_get_brightness(struct mx3fb_data *mx3fb)
  593. {
  594. u32 brightness;
  595. brightness = mx3fb_read_reg(mx3fb, SDC_PWM_CTRL);
  596. brightness = (brightness >> 16) & 0xFF;
  597. return brightness;
  598. }
  599. static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
  600. {
  601. dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
  602. /* This might be board-specific */
  603. mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
  604. return;
  605. }
  606. static uint32_t bpp_to_pixfmt(int bpp)
  607. {
  608. uint32_t pixfmt = 0;
  609. switch (bpp) {
  610. case 24:
  611. pixfmt = IPU_PIX_FMT_BGR24;
  612. break;
  613. case 32:
  614. pixfmt = IPU_PIX_FMT_BGR32;
  615. break;
  616. case 16:
  617. pixfmt = IPU_PIX_FMT_RGB565;
  618. break;
  619. }
  620. return pixfmt;
  621. }
  622. static int mx3fb_blank(int blank, struct fb_info *fbi);
  623. static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
  624. bool lock);
  625. static int mx3fb_unmap_video_memory(struct fb_info *fbi);
  626. /**
  627. * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
  628. * @info: framebuffer information pointer
  629. * @return: 0 on success or negative error code on failure.
  630. */
  631. static int mx3fb_set_fix(struct fb_info *fbi)
  632. {
  633. struct fb_fix_screeninfo *fix = &fbi->fix;
  634. struct fb_var_screeninfo *var = &fbi->var;
  635. strncpy(fix->id, "DISP3 BG", 8);
  636. fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
  637. fix->type = FB_TYPE_PACKED_PIXELS;
  638. fix->accel = FB_ACCEL_NONE;
  639. fix->visual = FB_VISUAL_TRUECOLOR;
  640. fix->xpanstep = 1;
  641. fix->ypanstep = 1;
  642. return 0;
  643. }
  644. static void mx3fb_dma_done(void *arg)
  645. {
  646. struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
  647. struct dma_chan *chan = tx_desc->txd.chan;
  648. struct idmac_channel *ichannel = to_idmac_chan(chan);
  649. struct mx3fb_data *mx3fb = ichannel->client;
  650. struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
  651. dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
  652. /* We only need one interrupt, it will be re-enabled as needed */
  653. disable_irq_nosync(ichannel->eof_irq);
  654. complete(&mx3_fbi->flip_cmpl);
  655. }
  656. static bool mx3fb_must_set_par(struct fb_info *fbi)
  657. {
  658. struct mx3fb_info *mx3_fbi = fbi->par;
  659. struct fb_var_screeninfo old_var = mx3_fbi->cur_var;
  660. struct fb_var_screeninfo new_var = fbi->var;
  661. if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
  662. (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
  663. return true;
  664. /*
  665. * Ignore xoffset and yoffset update,
  666. * because pan display handles this case.
  667. */
  668. old_var.xoffset = new_var.xoffset;
  669. old_var.yoffset = new_var.yoffset;
  670. return !!memcmp(&old_var, &new_var, sizeof(struct fb_var_screeninfo));
  671. }
  672. static int __set_par(struct fb_info *fbi, bool lock)
  673. {
  674. u32 mem_len, cur_xoffset, cur_yoffset;
  675. struct ipu_di_signal_cfg sig_cfg;
  676. enum ipu_panel mode = IPU_PANEL_TFT;
  677. struct mx3fb_info *mx3_fbi = fbi->par;
  678. struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
  679. struct idmac_channel *ichan = mx3_fbi->idmac_channel;
  680. struct idmac_video_param *video = &ichan->params.video;
  681. struct scatterlist *sg = mx3_fbi->sg;
  682. /* Total cleanup */
  683. if (mx3_fbi->txd)
  684. sdc_disable_channel(mx3_fbi);
  685. mx3fb_set_fix(fbi);
  686. mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
  687. if (mem_len > fbi->fix.smem_len) {
  688. if (fbi->fix.smem_start)
  689. mx3fb_unmap_video_memory(fbi);
  690. if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
  691. return -ENOMEM;
  692. }
  693. sg_init_table(&sg[0], 1);
  694. sg_init_table(&sg[1], 1);
  695. sg_dma_address(&sg[0]) = fbi->fix.smem_start;
  696. sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
  697. fbi->fix.smem_len,
  698. offset_in_page(fbi->screen_base));
  699. if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
  700. memset(&sig_cfg, 0, sizeof(sig_cfg));
  701. if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
  702. sig_cfg.Hsync_pol = true;
  703. if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
  704. sig_cfg.Vsync_pol = true;
  705. if (fbi->var.sync & FB_SYNC_CLK_INVERT)
  706. sig_cfg.clk_pol = true;
  707. if (fbi->var.sync & FB_SYNC_DATA_INVERT)
  708. sig_cfg.data_pol = true;
  709. if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
  710. sig_cfg.enable_pol = true;
  711. if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
  712. sig_cfg.clkidle_en = true;
  713. if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
  714. sig_cfg.clksel_en = true;
  715. if (fbi->var.sync & FB_SYNC_SHARP_MODE)
  716. mode = IPU_PANEL_SHARP_TFT;
  717. dev_dbg(fbi->device, "pixclock = %u Hz\n",
  718. (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
  719. if (sdc_init_panel(mx3fb, mode,
  720. (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
  721. fbi->var.xres, fbi->var.yres,
  722. fbi->var.left_margin,
  723. fbi->var.hsync_len,
  724. fbi->var.right_margin +
  725. fbi->var.hsync_len,
  726. fbi->var.upper_margin,
  727. fbi->var.vsync_len,
  728. fbi->var.lower_margin +
  729. fbi->var.vsync_len, &sig_cfg) != 0) {
  730. dev_err(fbi->device,
  731. "mx3fb: Error initializing panel.\n");
  732. return -EINVAL;
  733. }
  734. }
  735. sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
  736. mx3_fbi->cur_ipu_buf = 0;
  737. video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
  738. video->out_width = fbi->var.xres;
  739. video->out_height = fbi->var.yres;
  740. video->out_stride = fbi->var.xres_virtual;
  741. if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
  742. sdc_enable_channel(mx3_fbi);
  743. /*
  744. * sg[0] points to fb smem_start address
  745. * and is actually active in controller.
  746. */
  747. mx3_fbi->cur_var.xoffset = 0;
  748. mx3_fbi->cur_var.yoffset = 0;
  749. }
  750. /*
  751. * Preserve xoffset and yoffest in case they are
  752. * inactive in controller as fb is blanked.
  753. */
  754. cur_xoffset = mx3_fbi->cur_var.xoffset;
  755. cur_yoffset = mx3_fbi->cur_var.yoffset;
  756. mx3_fbi->cur_var = fbi->var;
  757. mx3_fbi->cur_var.xoffset = cur_xoffset;
  758. mx3_fbi->cur_var.yoffset = cur_yoffset;
  759. return 0;
  760. }
  761. /**
  762. * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
  763. * @fbi: framebuffer information pointer.
  764. * @return: 0 on success or negative error code on failure.
  765. */
  766. static int mx3fb_set_par(struct fb_info *fbi)
  767. {
  768. struct mx3fb_info *mx3_fbi = fbi->par;
  769. struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
  770. struct idmac_channel *ichan = mx3_fbi->idmac_channel;
  771. int ret;
  772. dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
  773. mutex_lock(&mx3_fbi->mutex);
  774. ret = mx3fb_must_set_par(fbi) ? __set_par(fbi, true) : 0;
  775. mutex_unlock(&mx3_fbi->mutex);
  776. return ret;
  777. }
  778. /**
  779. * mx3fb_check_var() - check and adjust framebuffer variable parameters.
  780. * @var: framebuffer variable parameters
  781. * @fbi: framebuffer information pointer
  782. */
  783. static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
  784. {
  785. struct mx3fb_info *mx3_fbi = fbi->par;
  786. u32 vtotal;
  787. u32 htotal;
  788. dev_dbg(fbi->device, "%s\n", __func__);
  789. if (var->xres_virtual < var->xres)
  790. var->xres_virtual = var->xres;
  791. if (var->yres_virtual < var->yres)
  792. var->yres_virtual = var->yres;
  793. if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
  794. (var->bits_per_pixel != 16))
  795. var->bits_per_pixel = default_bpp;
  796. switch (var->bits_per_pixel) {
  797. case 16:
  798. var->red.length = 5;
  799. var->red.offset = 11;
  800. var->red.msb_right = 0;
  801. var->green.length = 6;
  802. var->green.offset = 5;
  803. var->green.msb_right = 0;
  804. var->blue.length = 5;
  805. var->blue.offset = 0;
  806. var->blue.msb_right = 0;
  807. var->transp.length = 0;
  808. var->transp.offset = 0;
  809. var->transp.msb_right = 0;
  810. break;
  811. case 24:
  812. var->red.length = 8;
  813. var->red.offset = 16;
  814. var->red.msb_right = 0;
  815. var->green.length = 8;
  816. var->green.offset = 8;
  817. var->green.msb_right = 0;
  818. var->blue.length = 8;
  819. var->blue.offset = 0;
  820. var->blue.msb_right = 0;
  821. var->transp.length = 0;
  822. var->transp.offset = 0;
  823. var->transp.msb_right = 0;
  824. break;
  825. case 32:
  826. var->red.length = 8;
  827. var->red.offset = 16;
  828. var->red.msb_right = 0;
  829. var->green.length = 8;
  830. var->green.offset = 8;
  831. var->green.msb_right = 0;
  832. var->blue.length = 8;
  833. var->blue.offset = 0;
  834. var->blue.msb_right = 0;
  835. var->transp.length = 8;
  836. var->transp.offset = 24;
  837. var->transp.msb_right = 0;
  838. break;
  839. }
  840. if (var->pixclock < 1000) {
  841. htotal = var->xres + var->right_margin + var->hsync_len +
  842. var->left_margin;
  843. vtotal = var->yres + var->lower_margin + var->vsync_len +
  844. var->upper_margin;
  845. var->pixclock = (vtotal * htotal * 6UL) / 100UL;
  846. var->pixclock = KHZ2PICOS(var->pixclock);
  847. dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
  848. var->pixclock);
  849. }
  850. var->height = -1;
  851. var->width = -1;
  852. var->grayscale = 0;
  853. /* Preserve sync flags */
  854. var->sync |= mx3_fbi->cur_var.sync;
  855. mx3_fbi->cur_var.sync |= var->sync;
  856. return 0;
  857. }
  858. static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
  859. {
  860. chan &= 0xffff;
  861. chan >>= 16 - bf->length;
  862. return chan << bf->offset;
  863. }
  864. static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
  865. unsigned int green, unsigned int blue,
  866. unsigned int trans, struct fb_info *fbi)
  867. {
  868. struct mx3fb_info *mx3_fbi = fbi->par;
  869. u32 val;
  870. int ret = 1;
  871. dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
  872. mutex_lock(&mx3_fbi->mutex);
  873. /*
  874. * If greyscale is true, then we convert the RGB value
  875. * to greyscale no matter what visual we are using.
  876. */
  877. if (fbi->var.grayscale)
  878. red = green = blue = (19595 * red + 38470 * green +
  879. 7471 * blue) >> 16;
  880. switch (fbi->fix.visual) {
  881. case FB_VISUAL_TRUECOLOR:
  882. /*
  883. * 16-bit True Colour. We encode the RGB value
  884. * according to the RGB bitfield information.
  885. */
  886. if (regno < 16) {
  887. u32 *pal = fbi->pseudo_palette;
  888. val = chan_to_field(red, &fbi->var.red);
  889. val |= chan_to_field(green, &fbi->var.green);
  890. val |= chan_to_field(blue, &fbi->var.blue);
  891. pal[regno] = val;
  892. ret = 0;
  893. }
  894. break;
  895. case FB_VISUAL_STATIC_PSEUDOCOLOR:
  896. case FB_VISUAL_PSEUDOCOLOR:
  897. break;
  898. }
  899. mutex_unlock(&mx3_fbi->mutex);
  900. return ret;
  901. }
  902. static void __blank(int blank, struct fb_info *fbi)
  903. {
  904. struct mx3fb_info *mx3_fbi = fbi->par;
  905. struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
  906. int was_blank = mx3_fbi->blank;
  907. mx3_fbi->blank = blank;
  908. /* Attention!
  909. * Do not call sdc_disable_channel() for a channel that is disabled
  910. * already! This will result in a kernel NULL pointer dereference
  911. * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are
  912. * handled equally by this driver.
  913. */
  914. if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK)
  915. return;
  916. switch (blank) {
  917. case FB_BLANK_POWERDOWN:
  918. case FB_BLANK_VSYNC_SUSPEND:
  919. case FB_BLANK_HSYNC_SUSPEND:
  920. case FB_BLANK_NORMAL:
  921. sdc_set_brightness(mx3fb, 0);
  922. memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
  923. /* Give LCD time to update - enough for 50 and 60 Hz */
  924. msleep(25);
  925. sdc_disable_channel(mx3_fbi);
  926. break;
  927. case FB_BLANK_UNBLANK:
  928. sdc_enable_channel(mx3_fbi);
  929. sdc_set_brightness(mx3fb, mx3fb->backlight_level);
  930. break;
  931. }
  932. }
  933. /**
  934. * mx3fb_blank() - blank the display.
  935. */
  936. static int mx3fb_blank(int blank, struct fb_info *fbi)
  937. {
  938. struct mx3fb_info *mx3_fbi = fbi->par;
  939. dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
  940. blank, fbi->screen_base, fbi->fix.smem_len);
  941. if (mx3_fbi->blank == blank)
  942. return 0;
  943. mutex_lock(&mx3_fbi->mutex);
  944. __blank(blank, fbi);
  945. mutex_unlock(&mx3_fbi->mutex);
  946. return 0;
  947. }
  948. /**
  949. * mx3fb_pan_display() - pan or wrap the display
  950. * @var: variable screen buffer information.
  951. * @info: framebuffer information pointer.
  952. *
  953. * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
  954. */
  955. static int mx3fb_pan_display(struct fb_var_screeninfo *var,
  956. struct fb_info *fbi)
  957. {
  958. struct mx3fb_info *mx3_fbi = fbi->par;
  959. u32 y_bottom;
  960. unsigned long base;
  961. off_t offset;
  962. dma_cookie_t cookie;
  963. struct scatterlist *sg = mx3_fbi->sg;
  964. struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
  965. struct dma_async_tx_descriptor *txd;
  966. int ret;
  967. dev_dbg(fbi->device, "%s [%c]\n", __func__,
  968. list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
  969. if (var->xoffset > 0) {
  970. dev_dbg(fbi->device, "x panning not supported\n");
  971. return -EINVAL;
  972. }
  973. if (mx3_fbi->cur_var.xoffset == var->xoffset &&
  974. mx3_fbi->cur_var.yoffset == var->yoffset)
  975. return 0; /* No change, do nothing */
  976. y_bottom = var->yoffset;
  977. if (!(var->vmode & FB_VMODE_YWRAP))
  978. y_bottom += fbi->var.yres;
  979. if (y_bottom > fbi->var.yres_virtual)
  980. return -EINVAL;
  981. mutex_lock(&mx3_fbi->mutex);
  982. offset = var->yoffset * fbi->fix.line_length
  983. + var->xoffset * (fbi->var.bits_per_pixel / 8);
  984. base = fbi->fix.smem_start + offset;
  985. dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
  986. mx3_fbi->cur_ipu_buf, base);
  987. /*
  988. * We enable the End of Frame interrupt, which will free a tx-descriptor,
  989. * which we will need for the next dmaengine_prep_slave_sg(). The
  990. * IRQ-handler will disable the IRQ again.
  991. */
  992. init_completion(&mx3_fbi->flip_cmpl);
  993. enable_irq(mx3_fbi->idmac_channel->eof_irq);
  994. ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
  995. if (ret <= 0) {
  996. mutex_unlock(&mx3_fbi->mutex);
  997. dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
  998. "user interrupt" : "timeout");
  999. disable_irq(mx3_fbi->idmac_channel->eof_irq);
  1000. return ret ? : -ETIMEDOUT;
  1001. }
  1002. mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
  1003. sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
  1004. sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
  1005. virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
  1006. offset_in_page(fbi->screen_base + offset));
  1007. if (mx3_fbi->txd)
  1008. async_tx_ack(mx3_fbi->txd);
  1009. txd = dmaengine_prep_slave_sg(dma_chan, sg +
  1010. mx3_fbi->cur_ipu_buf, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
  1011. if (!txd) {
  1012. dev_err(fbi->device,
  1013. "Error preparing a DMA transaction descriptor.\n");
  1014. mutex_unlock(&mx3_fbi->mutex);
  1015. return -EIO;
  1016. }
  1017. txd->callback_param = txd;
  1018. txd->callback = mx3fb_dma_done;
  1019. /*
  1020. * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
  1021. * should switch to another buffer
  1022. */
  1023. cookie = txd->tx_submit(txd);
  1024. dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
  1025. if (cookie < 0) {
  1026. dev_err(fbi->device,
  1027. "Error updating SDC buf %d to address=0x%08lX\n",
  1028. mx3_fbi->cur_ipu_buf, base);
  1029. mutex_unlock(&mx3_fbi->mutex);
  1030. return -EIO;
  1031. }
  1032. mx3_fbi->txd = txd;
  1033. fbi->var.xoffset = var->xoffset;
  1034. fbi->var.yoffset = var->yoffset;
  1035. if (var->vmode & FB_VMODE_YWRAP)
  1036. fbi->var.vmode |= FB_VMODE_YWRAP;
  1037. else
  1038. fbi->var.vmode &= ~FB_VMODE_YWRAP;
  1039. mx3_fbi->cur_var = fbi->var;
  1040. mutex_unlock(&mx3_fbi->mutex);
  1041. dev_dbg(fbi->device, "Update complete\n");
  1042. return 0;
  1043. }
  1044. /*
  1045. * This structure contains the pointers to the control functions that are
  1046. * invoked by the core framebuffer driver to perform operations like
  1047. * blitting, rectangle filling, copy regions and cursor definition.
  1048. */
  1049. static const struct fb_ops mx3fb_ops = {
  1050. .owner = THIS_MODULE,
  1051. .fb_set_par = mx3fb_set_par,
  1052. .fb_check_var = mx3fb_check_var,
  1053. .fb_setcolreg = mx3fb_setcolreg,
  1054. .fb_pan_display = mx3fb_pan_display,
  1055. .fb_fillrect = cfb_fillrect,
  1056. .fb_copyarea = cfb_copyarea,
  1057. .fb_imageblit = cfb_imageblit,
  1058. .fb_blank = mx3fb_blank,
  1059. };
  1060. #ifdef CONFIG_PM
  1061. /*
  1062. * Power management hooks. Note that we won't be called from IRQ context,
  1063. * unlike the blank functions above, so we may sleep.
  1064. */
  1065. /*
  1066. * Suspends the framebuffer and blanks the screen. Power management support
  1067. */
  1068. static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
  1069. {
  1070. struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
  1071. struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
  1072. console_lock();
  1073. fb_set_suspend(mx3fb->fbi, 1);
  1074. console_unlock();
  1075. if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
  1076. sdc_disable_channel(mx3_fbi);
  1077. sdc_set_brightness(mx3fb, 0);
  1078. }
  1079. return 0;
  1080. }
  1081. /*
  1082. * Resumes the framebuffer and unblanks the screen. Power management support
  1083. */
  1084. static int mx3fb_resume(struct platform_device *pdev)
  1085. {
  1086. struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
  1087. struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
  1088. if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
  1089. sdc_enable_channel(mx3_fbi);
  1090. sdc_set_brightness(mx3fb, mx3fb->backlight_level);
  1091. }
  1092. console_lock();
  1093. fb_set_suspend(mx3fb->fbi, 0);
  1094. console_unlock();
  1095. return 0;
  1096. }
  1097. #else
  1098. #define mx3fb_suspend NULL
  1099. #define mx3fb_resume NULL
  1100. #endif
  1101. /*
  1102. * Main framebuffer functions
  1103. */
  1104. /**
  1105. * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
  1106. * @fbi: framebuffer information pointer
  1107. * @mem_len: length of mapped memory
  1108. * @lock: do not lock during initialisation
  1109. * @return: Error code indicating success or failure
  1110. *
  1111. * This buffer is remapped into a non-cached, non-buffered, memory region to
  1112. * allow palette and pixel writes to occur without flushing the cache. Once this
  1113. * area is remapped, all virtual memory access to the video memory should occur
  1114. * at the new region.
  1115. */
  1116. static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
  1117. bool lock)
  1118. {
  1119. int retval = 0;
  1120. dma_addr_t addr;
  1121. fbi->screen_base = dma_alloc_wc(fbi->device, mem_len, &addr,
  1122. GFP_DMA | GFP_KERNEL);
  1123. if (!fbi->screen_base) {
  1124. dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
  1125. mem_len);
  1126. retval = -EBUSY;
  1127. goto err0;
  1128. }
  1129. if (lock)
  1130. mutex_lock(&fbi->mm_lock);
  1131. fbi->fix.smem_start = addr;
  1132. fbi->fix.smem_len = mem_len;
  1133. if (lock)
  1134. mutex_unlock(&fbi->mm_lock);
  1135. dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
  1136. (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
  1137. fbi->screen_size = fbi->fix.smem_len;
  1138. /* Clear the screen */
  1139. memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
  1140. return 0;
  1141. err0:
  1142. fbi->fix.smem_len = 0;
  1143. fbi->fix.smem_start = 0;
  1144. fbi->screen_base = NULL;
  1145. return retval;
  1146. }
  1147. /**
  1148. * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
  1149. * @fbi: framebuffer information pointer
  1150. * @return: error code indicating success or failure
  1151. */
  1152. static int mx3fb_unmap_video_memory(struct fb_info *fbi)
  1153. {
  1154. dma_free_wc(fbi->device, fbi->fix.smem_len, fbi->screen_base,
  1155. fbi->fix.smem_start);
  1156. fbi->screen_base = NULL;
  1157. mutex_lock(&fbi->mm_lock);
  1158. fbi->fix.smem_start = 0;
  1159. fbi->fix.smem_len = 0;
  1160. mutex_unlock(&fbi->mm_lock);
  1161. return 0;
  1162. }
  1163. /**
  1164. * mx3fb_init_fbinfo() - initialize framebuffer information object.
  1165. * @return: initialized framebuffer structure.
  1166. */
  1167. static struct fb_info *mx3fb_init_fbinfo(struct device *dev,
  1168. const struct fb_ops *ops)
  1169. {
  1170. struct fb_info *fbi;
  1171. struct mx3fb_info *mx3fbi;
  1172. int ret;
  1173. /* Allocate sufficient memory for the fb structure */
  1174. fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
  1175. if (!fbi)
  1176. return NULL;
  1177. mx3fbi = fbi->par;
  1178. mx3fbi->cookie = -EINVAL;
  1179. mx3fbi->cur_ipu_buf = 0;
  1180. fbi->var.activate = FB_ACTIVATE_NOW;
  1181. fbi->fbops = ops;
  1182. fbi->flags = FBINFO_FLAG_DEFAULT;
  1183. fbi->pseudo_palette = mx3fbi->pseudo_palette;
  1184. mutex_init(&mx3fbi->mutex);
  1185. /* Allocate colormap */
  1186. ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
  1187. if (ret < 0) {
  1188. framebuffer_release(fbi);
  1189. return NULL;
  1190. }
  1191. return fbi;
  1192. }
  1193. static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
  1194. {
  1195. struct device *dev = mx3fb->dev;
  1196. struct mx3fb_platform_data *mx3fb_pdata = dev_get_platdata(dev);
  1197. const char *name = mx3fb_pdata->name;
  1198. unsigned int irq;
  1199. struct fb_info *fbi;
  1200. struct mx3fb_info *mx3fbi;
  1201. const struct fb_videomode *mode;
  1202. int ret, num_modes;
  1203. if (mx3fb_pdata->disp_data_fmt >= ARRAY_SIZE(di_mappings)) {
  1204. dev_err(dev, "Illegal display data format %d\n",
  1205. mx3fb_pdata->disp_data_fmt);
  1206. return -EINVAL;
  1207. }
  1208. ichan->client = mx3fb;
  1209. irq = ichan->eof_irq;
  1210. if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
  1211. return -EINVAL;
  1212. fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
  1213. if (!fbi)
  1214. return -ENOMEM;
  1215. if (!fb_mode)
  1216. fb_mode = name;
  1217. if (!fb_mode) {
  1218. ret = -EINVAL;
  1219. goto emode;
  1220. }
  1221. if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
  1222. mode = mx3fb_pdata->mode;
  1223. num_modes = mx3fb_pdata->num_modes;
  1224. } else {
  1225. mode = mx3fb_modedb;
  1226. num_modes = ARRAY_SIZE(mx3fb_modedb);
  1227. }
  1228. if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
  1229. num_modes, NULL, default_bpp)) {
  1230. ret = -EBUSY;
  1231. goto emode;
  1232. }
  1233. fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
  1234. /* Default Y virtual size is 2x panel size */
  1235. fbi->var.yres_virtual = fbi->var.yres * 2;
  1236. mx3fb->fbi = fbi;
  1237. /* set Display Interface clock period */
  1238. mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
  1239. /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
  1240. sdc_set_brightness(mx3fb, 255);
  1241. sdc_set_global_alpha(mx3fb, true, 0xFF);
  1242. sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
  1243. mx3fbi = fbi->par;
  1244. mx3fbi->idmac_channel = ichan;
  1245. mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
  1246. mx3fbi->mx3fb = mx3fb;
  1247. mx3fbi->blank = FB_BLANK_NORMAL;
  1248. mx3fb->disp_data_fmt = mx3fb_pdata->disp_data_fmt;
  1249. init_completion(&mx3fbi->flip_cmpl);
  1250. disable_irq(ichan->eof_irq);
  1251. dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
  1252. ret = __set_par(fbi, false);
  1253. if (ret < 0)
  1254. goto esetpar;
  1255. __blank(FB_BLANK_UNBLANK, fbi);
  1256. dev_info(dev, "registered, using mode %s\n", fb_mode);
  1257. ret = register_framebuffer(fbi);
  1258. if (ret < 0)
  1259. goto erfb;
  1260. return 0;
  1261. erfb:
  1262. esetpar:
  1263. emode:
  1264. fb_dealloc_cmap(&fbi->cmap);
  1265. framebuffer_release(fbi);
  1266. return ret;
  1267. }
  1268. static bool chan_filter(struct dma_chan *chan, void *arg)
  1269. {
  1270. struct dma_chan_request *rq = arg;
  1271. struct device *dev;
  1272. struct mx3fb_platform_data *mx3fb_pdata;
  1273. if (!imx_dma_is_ipu(chan))
  1274. return false;
  1275. if (!rq)
  1276. return false;
  1277. dev = rq->mx3fb->dev;
  1278. mx3fb_pdata = dev_get_platdata(dev);
  1279. return rq->id == chan->chan_id &&
  1280. mx3fb_pdata->dma_dev == chan->device->dev;
  1281. }
  1282. static void release_fbi(struct fb_info *fbi)
  1283. {
  1284. mx3fb_unmap_video_memory(fbi);
  1285. fb_dealloc_cmap(&fbi->cmap);
  1286. unregister_framebuffer(fbi);
  1287. framebuffer_release(fbi);
  1288. }
  1289. static int mx3fb_probe(struct platform_device *pdev)
  1290. {
  1291. struct device *dev = &pdev->dev;
  1292. int ret;
  1293. struct resource *sdc_reg;
  1294. struct mx3fb_data *mx3fb;
  1295. dma_cap_mask_t mask;
  1296. struct dma_chan *chan;
  1297. struct dma_chan_request rq;
  1298. /*
  1299. * Display Interface (DI) and Synchronous Display Controller (SDC)
  1300. * registers
  1301. */
  1302. sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1303. if (!sdc_reg)
  1304. return -EINVAL;
  1305. mx3fb = devm_kzalloc(&pdev->dev, sizeof(*mx3fb), GFP_KERNEL);
  1306. if (!mx3fb)
  1307. return -ENOMEM;
  1308. spin_lock_init(&mx3fb->lock);
  1309. mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
  1310. if (!mx3fb->reg_base) {
  1311. ret = -ENOMEM;
  1312. goto eremap;
  1313. }
  1314. pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
  1315. /* IDMAC interface */
  1316. dmaengine_get();
  1317. mx3fb->dev = dev;
  1318. platform_set_drvdata(pdev, mx3fb);
  1319. rq.mx3fb = mx3fb;
  1320. dma_cap_zero(mask);
  1321. dma_cap_set(DMA_SLAVE, mask);
  1322. dma_cap_set(DMA_PRIVATE, mask);
  1323. rq.id = IDMAC_SDC_0;
  1324. chan = dma_request_channel(mask, chan_filter, &rq);
  1325. if (!chan) {
  1326. ret = -EBUSY;
  1327. goto ersdc0;
  1328. }
  1329. mx3fb->backlight_level = 255;
  1330. ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
  1331. if (ret < 0)
  1332. goto eisdc0;
  1333. mx3fb_init_backlight(mx3fb);
  1334. return 0;
  1335. eisdc0:
  1336. dma_release_channel(chan);
  1337. ersdc0:
  1338. dmaengine_put();
  1339. iounmap(mx3fb->reg_base);
  1340. eremap:
  1341. dev_err(dev, "mx3fb: failed to register fb\n");
  1342. return ret;
  1343. }
  1344. static int mx3fb_remove(struct platform_device *dev)
  1345. {
  1346. struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
  1347. struct fb_info *fbi = mx3fb->fbi;
  1348. struct mx3fb_info *mx3_fbi = fbi->par;
  1349. struct dma_chan *chan;
  1350. chan = &mx3_fbi->idmac_channel->dma_chan;
  1351. release_fbi(fbi);
  1352. mx3fb_exit_backlight(mx3fb);
  1353. dma_release_channel(chan);
  1354. dmaengine_put();
  1355. iounmap(mx3fb->reg_base);
  1356. return 0;
  1357. }
  1358. static struct platform_driver mx3fb_driver = {
  1359. .driver = {
  1360. .name = MX3FB_NAME,
  1361. },
  1362. .probe = mx3fb_probe,
  1363. .remove = mx3fb_remove,
  1364. .suspend = mx3fb_suspend,
  1365. .resume = mx3fb_resume,
  1366. };
  1367. /*
  1368. * Parse user specified options (`video=mx3fb:')
  1369. * example:
  1370. * video=mx3fb:bpp=16
  1371. */
  1372. static int __init mx3fb_setup(void)
  1373. {
  1374. #ifndef MODULE
  1375. char *opt, *options = NULL;
  1376. if (fb_get_options("mx3fb", &options))
  1377. return -ENODEV;
  1378. if (!options || !*options)
  1379. return 0;
  1380. while ((opt = strsep(&options, ",")) != NULL) {
  1381. if (!*opt)
  1382. continue;
  1383. if (!strncmp(opt, "bpp=", 4))
  1384. default_bpp = simple_strtoul(opt + 4, NULL, 0);
  1385. else
  1386. fb_mode = opt;
  1387. }
  1388. #endif
  1389. return 0;
  1390. }
  1391. static int __init mx3fb_init(void)
  1392. {
  1393. int ret = mx3fb_setup();
  1394. if (ret < 0)
  1395. return ret;
  1396. ret = platform_driver_register(&mx3fb_driver);
  1397. return ret;
  1398. }
  1399. static void __exit mx3fb_exit(void)
  1400. {
  1401. platform_driver_unregister(&mx3fb_driver);
  1402. }
  1403. module_init(mx3fb_init);
  1404. module_exit(mx3fb_exit);
  1405. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  1406. MODULE_DESCRIPTION("MX3 framebuffer driver");
  1407. MODULE_ALIAS("platform:" MX3FB_NAME);
  1408. MODULE_LICENSE("GPL v2");