imxfb.c 26 KB

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  1. /*
  2. * Freescale i.MX Frame Buffer device driver
  3. *
  4. * Copyright (C) 2004 Sascha Hauer, Pengutronix
  5. * Based on acornfb.c Copyright (C) Russell King.
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive for
  9. * more details.
  10. *
  11. * Please direct your questions and comments on this driver to the following
  12. * email address:
  13. *
  14. * linux-arm-kernel@lists.arm.linux.org.uk
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/string.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/slab.h>
  22. #include <linux/mm.h>
  23. #include <linux/fb.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/cpufreq.h>
  28. #include <linux/clk.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/io.h>
  32. #include <linux/lcd.h>
  33. #include <linux/math64.h>
  34. #include <linux/of.h>
  35. #include <linux/of_device.h>
  36. #include <linux/regulator/consumer.h>
  37. #include <video/of_display_timing.h>
  38. #include <video/of_videomode.h>
  39. #include <video/videomode.h>
  40. #include <linux/platform_data/video-imxfb.h>
  41. /*
  42. * Complain if VAR is out of range.
  43. */
  44. #define DEBUG_VAR 1
  45. #define DRIVER_NAME "imx-fb"
  46. #define LCDC_SSA 0x00
  47. #define LCDC_SIZE 0x04
  48. #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
  49. #define YMAX_MASK_IMX1 0x1ff
  50. #define YMAX_MASK_IMX21 0x3ff
  51. #define LCDC_VPW 0x08
  52. #define VPW_VPW(x) ((x) & 0x3ff)
  53. #define LCDC_CPOS 0x0C
  54. #define CPOS_CC1 (1<<31)
  55. #define CPOS_CC0 (1<<30)
  56. #define CPOS_OP (1<<28)
  57. #define CPOS_CXP(x) (((x) & 3ff) << 16)
  58. #define LCDC_LCWHB 0x10
  59. #define LCWHB_BK_EN (1<<31)
  60. #define LCWHB_CW(w) (((w) & 0x1f) << 24)
  61. #define LCWHB_CH(h) (((h) & 0x1f) << 16)
  62. #define LCWHB_BD(x) ((x) & 0xff)
  63. #define LCDC_LCHCC 0x14
  64. #define LCDC_PCR 0x18
  65. #define LCDC_HCR 0x1C
  66. #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
  67. #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
  68. #define HCR_H_WAIT_2(x) ((x) & 0xff)
  69. #define LCDC_VCR 0x20
  70. #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
  71. #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
  72. #define VCR_V_WAIT_2(x) ((x) & 0xff)
  73. #define LCDC_POS 0x24
  74. #define POS_POS(x) ((x) & 1f)
  75. #define LCDC_LSCR1 0x28
  76. /* bit fields in imxfb.h */
  77. #define LCDC_PWMR 0x2C
  78. /* bit fields in imxfb.h */
  79. #define LCDC_DMACR 0x30
  80. /* bit fields in imxfb.h */
  81. #define LCDC_RMCR 0x34
  82. #define RMCR_LCDC_EN_MX1 (1<<1)
  83. #define RMCR_SELF_REF (1<<0)
  84. #define LCDC_LCDICR 0x38
  85. #define LCDICR_INT_SYN (1<<2)
  86. #define LCDICR_INT_CON (1)
  87. #define LCDC_LCDISR 0x40
  88. #define LCDISR_UDR_ERR (1<<3)
  89. #define LCDISR_ERR_RES (1<<2)
  90. #define LCDISR_EOF (1<<1)
  91. #define LCDISR_BOF (1<<0)
  92. #define IMXFB_LSCR1_DEFAULT 0x00120300
  93. #define LCDC_LAUSCR 0x80
  94. #define LAUSCR_AUS_MODE (1<<31)
  95. /* Used fb-mode. Can be set on kernel command line, therefore file-static. */
  96. static const char *fb_mode;
  97. /*
  98. * These are the bitfields for each
  99. * display depth that we support.
  100. */
  101. struct imxfb_rgb {
  102. struct fb_bitfield red;
  103. struct fb_bitfield green;
  104. struct fb_bitfield blue;
  105. struct fb_bitfield transp;
  106. };
  107. enum imxfb_type {
  108. IMX1_FB,
  109. IMX21_FB,
  110. };
  111. struct imxfb_info {
  112. struct platform_device *pdev;
  113. void __iomem *regs;
  114. struct clk *clk_ipg;
  115. struct clk *clk_ahb;
  116. struct clk *clk_per;
  117. enum imxfb_type devtype;
  118. bool enabled;
  119. /*
  120. * These are the addresses we mapped
  121. * the framebuffer memory region to.
  122. */
  123. dma_addr_t map_dma;
  124. u_int map_size;
  125. u_int palette_size;
  126. dma_addr_t dbar1;
  127. dma_addr_t dbar2;
  128. u_int pcr;
  129. u_int lauscr;
  130. u_int pwmr;
  131. u_int lscr1;
  132. u_int dmacr;
  133. bool cmap_inverse;
  134. bool cmap_static;
  135. struct imx_fb_videomode *mode;
  136. int num_modes;
  137. struct regulator *lcd_pwr;
  138. int lcd_pwr_enabled;
  139. };
  140. static const struct platform_device_id imxfb_devtype[] = {
  141. {
  142. .name = "imx1-fb",
  143. .driver_data = IMX1_FB,
  144. }, {
  145. .name = "imx21-fb",
  146. .driver_data = IMX21_FB,
  147. }, {
  148. /* sentinel */
  149. }
  150. };
  151. MODULE_DEVICE_TABLE(platform, imxfb_devtype);
  152. static const struct of_device_id imxfb_of_dev_id[] = {
  153. {
  154. .compatible = "fsl,imx1-fb",
  155. .data = &imxfb_devtype[IMX1_FB],
  156. }, {
  157. .compatible = "fsl,imx21-fb",
  158. .data = &imxfb_devtype[IMX21_FB],
  159. }, {
  160. /* sentinel */
  161. }
  162. };
  163. MODULE_DEVICE_TABLE(of, imxfb_of_dev_id);
  164. static inline int is_imx1_fb(struct imxfb_info *fbi)
  165. {
  166. return fbi->devtype == IMX1_FB;
  167. }
  168. #define IMX_NAME "IMX"
  169. /*
  170. * Minimum X and Y resolutions
  171. */
  172. #define MIN_XRES 64
  173. #define MIN_YRES 64
  174. /* Actually this really is 18bit support, the lowest 2 bits of each colour
  175. * are unused in hardware. We claim to have 24bit support to make software
  176. * like X work, which does not support 18bit.
  177. */
  178. static struct imxfb_rgb def_rgb_18 = {
  179. .red = {.offset = 16, .length = 8,},
  180. .green = {.offset = 8, .length = 8,},
  181. .blue = {.offset = 0, .length = 8,},
  182. .transp = {.offset = 0, .length = 0,},
  183. };
  184. static struct imxfb_rgb def_rgb_16_tft = {
  185. .red = {.offset = 11, .length = 5,},
  186. .green = {.offset = 5, .length = 6,},
  187. .blue = {.offset = 0, .length = 5,},
  188. .transp = {.offset = 0, .length = 0,},
  189. };
  190. static struct imxfb_rgb def_rgb_16_stn = {
  191. .red = {.offset = 8, .length = 4,},
  192. .green = {.offset = 4, .length = 4,},
  193. .blue = {.offset = 0, .length = 4,},
  194. .transp = {.offset = 0, .length = 0,},
  195. };
  196. static struct imxfb_rgb def_rgb_8 = {
  197. .red = {.offset = 0, .length = 8,},
  198. .green = {.offset = 0, .length = 8,},
  199. .blue = {.offset = 0, .length = 8,},
  200. .transp = {.offset = 0, .length = 0,},
  201. };
  202. static int imxfb_activate_var(struct fb_var_screeninfo *var,
  203. struct fb_info *info);
  204. static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  205. {
  206. chan &= 0xffff;
  207. chan >>= 16 - bf->length;
  208. return chan << bf->offset;
  209. }
  210. static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
  211. u_int trans, struct fb_info *info)
  212. {
  213. struct imxfb_info *fbi = info->par;
  214. u_int val, ret = 1;
  215. #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
  216. if (regno < fbi->palette_size) {
  217. val = (CNVT_TOHW(red, 4) << 8) |
  218. (CNVT_TOHW(green,4) << 4) |
  219. CNVT_TOHW(blue, 4);
  220. writel(val, fbi->regs + 0x800 + (regno << 2));
  221. ret = 0;
  222. }
  223. return ret;
  224. }
  225. static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  226. u_int trans, struct fb_info *info)
  227. {
  228. struct imxfb_info *fbi = info->par;
  229. unsigned int val;
  230. int ret = 1;
  231. /*
  232. * If inverse mode was selected, invert all the colours
  233. * rather than the register number. The register number
  234. * is what you poke into the framebuffer to produce the
  235. * colour you requested.
  236. */
  237. if (fbi->cmap_inverse) {
  238. red = 0xffff - red;
  239. green = 0xffff - green;
  240. blue = 0xffff - blue;
  241. }
  242. /*
  243. * If greyscale is true, then we convert the RGB value
  244. * to greyscale no mater what visual we are using.
  245. */
  246. if (info->var.grayscale)
  247. red = green = blue = (19595 * red + 38470 * green +
  248. 7471 * blue) >> 16;
  249. switch (info->fix.visual) {
  250. case FB_VISUAL_TRUECOLOR:
  251. /*
  252. * 12 or 16-bit True Colour. We encode the RGB value
  253. * according to the RGB bitfield information.
  254. */
  255. if (regno < 16) {
  256. u32 *pal = info->pseudo_palette;
  257. val = chan_to_field(red, &info->var.red);
  258. val |= chan_to_field(green, &info->var.green);
  259. val |= chan_to_field(blue, &info->var.blue);
  260. pal[regno] = val;
  261. ret = 0;
  262. }
  263. break;
  264. case FB_VISUAL_STATIC_PSEUDOCOLOR:
  265. case FB_VISUAL_PSEUDOCOLOR:
  266. ret = imxfb_setpalettereg(regno, red, green, blue, trans, info);
  267. break;
  268. }
  269. return ret;
  270. }
  271. static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
  272. {
  273. struct imx_fb_videomode *m;
  274. int i;
  275. if (!fb_mode)
  276. return &fbi->mode[0];
  277. for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
  278. if (!strcmp(m->mode.name, fb_mode))
  279. return m;
  280. }
  281. return NULL;
  282. }
  283. /*
  284. * imxfb_check_var():
  285. * Round up in the following order: bits_per_pixel, xres,
  286. * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
  287. * bitfields, horizontal timing, vertical timing.
  288. */
  289. static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  290. {
  291. struct imxfb_info *fbi = info->par;
  292. struct imxfb_rgb *rgb;
  293. const struct imx_fb_videomode *imxfb_mode;
  294. unsigned long lcd_clk;
  295. unsigned long long tmp;
  296. u32 pcr = 0;
  297. if (var->xres < MIN_XRES)
  298. var->xres = MIN_XRES;
  299. if (var->yres < MIN_YRES)
  300. var->yres = MIN_YRES;
  301. imxfb_mode = imxfb_find_mode(fbi);
  302. if (!imxfb_mode)
  303. return -EINVAL;
  304. var->xres = imxfb_mode->mode.xres;
  305. var->yres = imxfb_mode->mode.yres;
  306. var->bits_per_pixel = imxfb_mode->bpp;
  307. var->pixclock = imxfb_mode->mode.pixclock;
  308. var->hsync_len = imxfb_mode->mode.hsync_len;
  309. var->left_margin = imxfb_mode->mode.left_margin;
  310. var->right_margin = imxfb_mode->mode.right_margin;
  311. var->vsync_len = imxfb_mode->mode.vsync_len;
  312. var->upper_margin = imxfb_mode->mode.upper_margin;
  313. var->lower_margin = imxfb_mode->mode.lower_margin;
  314. var->sync = imxfb_mode->mode.sync;
  315. var->xres_virtual = max(var->xres_virtual, var->xres);
  316. var->yres_virtual = max(var->yres_virtual, var->yres);
  317. pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
  318. lcd_clk = clk_get_rate(fbi->clk_per);
  319. tmp = var->pixclock * (unsigned long long)lcd_clk;
  320. do_div(tmp, 1000000);
  321. if (do_div(tmp, 1000000) > 500000)
  322. tmp++;
  323. pcr = (unsigned int)tmp;
  324. if (--pcr > 0x3F) {
  325. pcr = 0x3F;
  326. printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
  327. lcd_clk / pcr);
  328. }
  329. switch (var->bits_per_pixel) {
  330. case 32:
  331. pcr |= PCR_BPIX_18;
  332. rgb = &def_rgb_18;
  333. break;
  334. case 16:
  335. default:
  336. if (is_imx1_fb(fbi))
  337. pcr |= PCR_BPIX_12;
  338. else
  339. pcr |= PCR_BPIX_16;
  340. if (imxfb_mode->pcr & PCR_TFT)
  341. rgb = &def_rgb_16_tft;
  342. else
  343. rgb = &def_rgb_16_stn;
  344. break;
  345. case 8:
  346. pcr |= PCR_BPIX_8;
  347. rgb = &def_rgb_8;
  348. break;
  349. }
  350. /* add sync polarities */
  351. pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25));
  352. fbi->pcr = pcr;
  353. /*
  354. * The LCDC AUS Mode Control Register does not exist on imx1.
  355. */
  356. if (!is_imx1_fb(fbi) && imxfb_mode->aus_mode)
  357. fbi->lauscr = LAUSCR_AUS_MODE;
  358. /*
  359. * Copy the RGB parameters for this display
  360. * from the machine specific parameters.
  361. */
  362. var->red = rgb->red;
  363. var->green = rgb->green;
  364. var->blue = rgb->blue;
  365. var->transp = rgb->transp;
  366. pr_debug("RGBT length = %d:%d:%d:%d\n",
  367. var->red.length, var->green.length, var->blue.length,
  368. var->transp.length);
  369. pr_debug("RGBT offset = %d:%d:%d:%d\n",
  370. var->red.offset, var->green.offset, var->blue.offset,
  371. var->transp.offset);
  372. return 0;
  373. }
  374. /*
  375. * imxfb_set_par():
  376. * Set the user defined part of the display for the specified console
  377. */
  378. static int imxfb_set_par(struct fb_info *info)
  379. {
  380. struct imxfb_info *fbi = info->par;
  381. struct fb_var_screeninfo *var = &info->var;
  382. if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32)
  383. info->fix.visual = FB_VISUAL_TRUECOLOR;
  384. else if (!fbi->cmap_static)
  385. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  386. else {
  387. /*
  388. * Some people have weird ideas about wanting static
  389. * pseudocolor maps. I suspect their user space
  390. * applications are broken.
  391. */
  392. info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
  393. }
  394. info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
  395. fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
  396. imxfb_activate_var(var, info);
  397. return 0;
  398. }
  399. static int imxfb_enable_controller(struct imxfb_info *fbi)
  400. {
  401. int ret;
  402. if (fbi->enabled)
  403. return 0;
  404. pr_debug("Enabling LCD controller\n");
  405. writel(fbi->map_dma, fbi->regs + LCDC_SSA);
  406. /* panning offset 0 (0 pixel offset) */
  407. writel(0x00000000, fbi->regs + LCDC_POS);
  408. /* disable hardware cursor */
  409. writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
  410. fbi->regs + LCDC_CPOS);
  411. /*
  412. * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt
  413. * on other SoCs
  414. */
  415. writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR);
  416. ret = clk_prepare_enable(fbi->clk_ipg);
  417. if (ret)
  418. goto err_enable_ipg;
  419. ret = clk_prepare_enable(fbi->clk_ahb);
  420. if (ret)
  421. goto err_enable_ahb;
  422. ret = clk_prepare_enable(fbi->clk_per);
  423. if (ret)
  424. goto err_enable_per;
  425. fbi->enabled = true;
  426. return 0;
  427. err_enable_per:
  428. clk_disable_unprepare(fbi->clk_ahb);
  429. err_enable_ahb:
  430. clk_disable_unprepare(fbi->clk_ipg);
  431. err_enable_ipg:
  432. writel(0, fbi->regs + LCDC_RMCR);
  433. return ret;
  434. }
  435. static void imxfb_disable_controller(struct imxfb_info *fbi)
  436. {
  437. if (!fbi->enabled)
  438. return;
  439. pr_debug("Disabling LCD controller\n");
  440. clk_disable_unprepare(fbi->clk_per);
  441. clk_disable_unprepare(fbi->clk_ahb);
  442. clk_disable_unprepare(fbi->clk_ipg);
  443. fbi->enabled = false;
  444. writel(0, fbi->regs + LCDC_RMCR);
  445. }
  446. static int imxfb_blank(int blank, struct fb_info *info)
  447. {
  448. struct imxfb_info *fbi = info->par;
  449. pr_debug("imxfb_blank: blank=%d\n", blank);
  450. switch (blank) {
  451. case FB_BLANK_POWERDOWN:
  452. case FB_BLANK_VSYNC_SUSPEND:
  453. case FB_BLANK_HSYNC_SUSPEND:
  454. case FB_BLANK_NORMAL:
  455. imxfb_disable_controller(fbi);
  456. break;
  457. case FB_BLANK_UNBLANK:
  458. return imxfb_enable_controller(fbi);
  459. }
  460. return 0;
  461. }
  462. static const struct fb_ops imxfb_ops = {
  463. .owner = THIS_MODULE,
  464. .fb_check_var = imxfb_check_var,
  465. .fb_set_par = imxfb_set_par,
  466. .fb_setcolreg = imxfb_setcolreg,
  467. .fb_fillrect = cfb_fillrect,
  468. .fb_copyarea = cfb_copyarea,
  469. .fb_imageblit = cfb_imageblit,
  470. .fb_blank = imxfb_blank,
  471. };
  472. /*
  473. * imxfb_activate_var():
  474. * Configures LCD Controller based on entries in var parameter. Settings are
  475. * only written to the controller if changes were made.
  476. */
  477. static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info)
  478. {
  479. struct imxfb_info *fbi = info->par;
  480. u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21;
  481. pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
  482. var->xres, var->hsync_len,
  483. var->left_margin, var->right_margin);
  484. pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
  485. var->yres, var->vsync_len,
  486. var->upper_margin, var->lower_margin);
  487. #if DEBUG_VAR
  488. if (var->xres < 16 || var->xres > 1024)
  489. printk(KERN_ERR "%s: invalid xres %d\n",
  490. info->fix.id, var->xres);
  491. if (var->hsync_len < 1 || var->hsync_len > 64)
  492. printk(KERN_ERR "%s: invalid hsync_len %d\n",
  493. info->fix.id, var->hsync_len);
  494. if (var->left_margin > 255)
  495. printk(KERN_ERR "%s: invalid left_margin %d\n",
  496. info->fix.id, var->left_margin);
  497. if (var->right_margin > 255)
  498. printk(KERN_ERR "%s: invalid right_margin %d\n",
  499. info->fix.id, var->right_margin);
  500. if (var->yres < 1 || var->yres > ymax_mask)
  501. printk(KERN_ERR "%s: invalid yres %d\n",
  502. info->fix.id, var->yres);
  503. if (var->vsync_len > 100)
  504. printk(KERN_ERR "%s: invalid vsync_len %d\n",
  505. info->fix.id, var->vsync_len);
  506. if (var->upper_margin > 63)
  507. printk(KERN_ERR "%s: invalid upper_margin %d\n",
  508. info->fix.id, var->upper_margin);
  509. if (var->lower_margin > 255)
  510. printk(KERN_ERR "%s: invalid lower_margin %d\n",
  511. info->fix.id, var->lower_margin);
  512. #endif
  513. /* physical screen start address */
  514. writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4),
  515. fbi->regs + LCDC_VPW);
  516. writel(HCR_H_WIDTH(var->hsync_len - 1) |
  517. HCR_H_WAIT_1(var->right_margin - 1) |
  518. HCR_H_WAIT_2(var->left_margin - 3),
  519. fbi->regs + LCDC_HCR);
  520. writel(VCR_V_WIDTH(var->vsync_len) |
  521. VCR_V_WAIT_1(var->lower_margin) |
  522. VCR_V_WAIT_2(var->upper_margin),
  523. fbi->regs + LCDC_VCR);
  524. writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask),
  525. fbi->regs + LCDC_SIZE);
  526. writel(fbi->pcr, fbi->regs + LCDC_PCR);
  527. if (fbi->pwmr)
  528. writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
  529. writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
  530. /* dmacr = 0 is no valid value, as we need DMA control marks. */
  531. if (fbi->dmacr)
  532. writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
  533. if (fbi->lauscr)
  534. writel(fbi->lauscr, fbi->regs + LCDC_LAUSCR);
  535. return 0;
  536. }
  537. static int imxfb_init_fbinfo(struct platform_device *pdev)
  538. {
  539. struct imx_fb_platform_data *pdata = dev_get_platdata(&pdev->dev);
  540. struct fb_info *info = dev_get_drvdata(&pdev->dev);
  541. struct imxfb_info *fbi = info->par;
  542. struct device_node *np;
  543. pr_debug("%s\n",__func__);
  544. info->pseudo_palette = kmalloc_array(16, sizeof(u32), GFP_KERNEL);
  545. if (!info->pseudo_palette)
  546. return -ENOMEM;
  547. memset(fbi, 0, sizeof(struct imxfb_info));
  548. fbi->devtype = pdev->id_entry->driver_data;
  549. strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
  550. info->fix.type = FB_TYPE_PACKED_PIXELS;
  551. info->fix.type_aux = 0;
  552. info->fix.xpanstep = 0;
  553. info->fix.ypanstep = 0;
  554. info->fix.ywrapstep = 0;
  555. info->fix.accel = FB_ACCEL_NONE;
  556. info->var.nonstd = 0;
  557. info->var.activate = FB_ACTIVATE_NOW;
  558. info->var.height = -1;
  559. info->var.width = -1;
  560. info->var.accel_flags = 0;
  561. info->var.vmode = FB_VMODE_NONINTERLACED;
  562. info->fbops = &imxfb_ops;
  563. info->flags = FBINFO_FLAG_DEFAULT |
  564. FBINFO_READS_FAST;
  565. if (pdata) {
  566. fbi->lscr1 = pdata->lscr1;
  567. fbi->dmacr = pdata->dmacr;
  568. fbi->pwmr = pdata->pwmr;
  569. } else {
  570. np = pdev->dev.of_node;
  571. info->var.grayscale = of_property_read_bool(np,
  572. "cmap-greyscale");
  573. fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse");
  574. fbi->cmap_static = of_property_read_bool(np, "cmap-static");
  575. fbi->lscr1 = IMXFB_LSCR1_DEFAULT;
  576. of_property_read_u32(np, "fsl,lpccr", &fbi->pwmr);
  577. of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1);
  578. of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr);
  579. }
  580. return 0;
  581. }
  582. static int imxfb_of_read_mode(struct device *dev, struct device_node *np,
  583. struct imx_fb_videomode *imxfb_mode)
  584. {
  585. int ret;
  586. struct fb_videomode *of_mode = &imxfb_mode->mode;
  587. u32 bpp;
  588. u32 pcr;
  589. ret = of_property_read_string(np, "model", &of_mode->name);
  590. if (ret)
  591. of_mode->name = NULL;
  592. ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE);
  593. if (ret) {
  594. dev_err(dev, "Failed to get videomode from DT\n");
  595. return ret;
  596. }
  597. ret = of_property_read_u32(np, "bits-per-pixel", &bpp);
  598. ret |= of_property_read_u32(np, "fsl,pcr", &pcr);
  599. if (ret) {
  600. dev_err(dev, "Failed to read bpp and pcr from DT\n");
  601. return -EINVAL;
  602. }
  603. if (bpp < 1 || bpp > 255) {
  604. dev_err(dev, "Bits per pixel have to be between 1 and 255\n");
  605. return -EINVAL;
  606. }
  607. imxfb_mode->bpp = bpp;
  608. imxfb_mode->pcr = pcr;
  609. /*
  610. * fsl,aus-mode is optional
  611. */
  612. imxfb_mode->aus_mode = of_property_read_bool(np, "fsl,aus-mode");
  613. return 0;
  614. }
  615. static int imxfb_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi)
  616. {
  617. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  618. if (!fi || fi->par == fbi)
  619. return 1;
  620. return 0;
  621. }
  622. static int imxfb_lcd_get_contrast(struct lcd_device *lcddev)
  623. {
  624. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  625. return fbi->pwmr & 0xff;
  626. }
  627. static int imxfb_lcd_set_contrast(struct lcd_device *lcddev, int contrast)
  628. {
  629. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  630. if (fbi->pwmr && fbi->enabled) {
  631. if (contrast > 255)
  632. contrast = 255;
  633. else if (contrast < 0)
  634. contrast = 0;
  635. fbi->pwmr &= ~0xff;
  636. fbi->pwmr |= contrast;
  637. writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
  638. }
  639. return 0;
  640. }
  641. static int imxfb_lcd_get_power(struct lcd_device *lcddev)
  642. {
  643. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  644. if (!IS_ERR(fbi->lcd_pwr) &&
  645. !regulator_is_enabled(fbi->lcd_pwr))
  646. return FB_BLANK_POWERDOWN;
  647. return FB_BLANK_UNBLANK;
  648. }
  649. static int imxfb_regulator_set(struct imxfb_info *fbi, int enable)
  650. {
  651. int ret;
  652. if (enable == fbi->lcd_pwr_enabled)
  653. return 0;
  654. if (enable)
  655. ret = regulator_enable(fbi->lcd_pwr);
  656. else
  657. ret = regulator_disable(fbi->lcd_pwr);
  658. if (ret == 0)
  659. fbi->lcd_pwr_enabled = enable;
  660. return ret;
  661. }
  662. static int imxfb_lcd_set_power(struct lcd_device *lcddev, int power)
  663. {
  664. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  665. if (!IS_ERR(fbi->lcd_pwr))
  666. return imxfb_regulator_set(fbi, power == FB_BLANK_UNBLANK);
  667. return 0;
  668. }
  669. static struct lcd_ops imxfb_lcd_ops = {
  670. .check_fb = imxfb_lcd_check_fb,
  671. .get_contrast = imxfb_lcd_get_contrast,
  672. .set_contrast = imxfb_lcd_set_contrast,
  673. .get_power = imxfb_lcd_get_power,
  674. .set_power = imxfb_lcd_set_power,
  675. };
  676. static int imxfb_setup(void)
  677. {
  678. char *opt, *options = NULL;
  679. if (fb_get_options("imxfb", &options))
  680. return -ENODEV;
  681. if (!options || !*options)
  682. return 0;
  683. while ((opt = strsep(&options, ",")) != NULL) {
  684. if (!*opt)
  685. continue;
  686. else
  687. fb_mode = opt;
  688. }
  689. return 0;
  690. }
  691. static int imxfb_probe(struct platform_device *pdev)
  692. {
  693. struct imxfb_info *fbi;
  694. struct lcd_device *lcd;
  695. struct fb_info *info;
  696. struct imx_fb_platform_data *pdata;
  697. struct resource *res;
  698. struct imx_fb_videomode *m;
  699. const struct of_device_id *of_id;
  700. int ret, i;
  701. int bytes_per_pixel;
  702. dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
  703. ret = imxfb_setup();
  704. if (ret < 0)
  705. return ret;
  706. of_id = of_match_device(imxfb_of_dev_id, &pdev->dev);
  707. if (of_id)
  708. pdev->id_entry = of_id->data;
  709. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  710. if (!res)
  711. return -ENODEV;
  712. pdata = dev_get_platdata(&pdev->dev);
  713. info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
  714. if (!info)
  715. return -ENOMEM;
  716. fbi = info->par;
  717. platform_set_drvdata(pdev, info);
  718. ret = imxfb_init_fbinfo(pdev);
  719. if (ret < 0)
  720. goto failed_init;
  721. if (pdata) {
  722. if (!fb_mode)
  723. fb_mode = pdata->mode[0].mode.name;
  724. fbi->mode = pdata->mode;
  725. fbi->num_modes = pdata->num_modes;
  726. } else {
  727. struct device_node *display_np;
  728. fb_mode = NULL;
  729. display_np = of_parse_phandle(pdev->dev.of_node, "display", 0);
  730. if (!display_np) {
  731. dev_err(&pdev->dev, "No display defined in devicetree\n");
  732. ret = -EINVAL;
  733. goto failed_of_parse;
  734. }
  735. /*
  736. * imxfb does not support more modes, we choose only the native
  737. * mode.
  738. */
  739. fbi->num_modes = 1;
  740. fbi->mode = devm_kzalloc(&pdev->dev,
  741. sizeof(struct imx_fb_videomode), GFP_KERNEL);
  742. if (!fbi->mode) {
  743. ret = -ENOMEM;
  744. goto failed_of_parse;
  745. }
  746. ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode);
  747. if (ret)
  748. goto failed_of_parse;
  749. }
  750. /* Calculate maximum bytes used per pixel. In most cases this should
  751. * be the same as m->bpp/8 */
  752. m = &fbi->mode[0];
  753. bytes_per_pixel = (m->bpp + 7) / 8;
  754. for (i = 0; i < fbi->num_modes; i++, m++)
  755. info->fix.smem_len = max_t(size_t, info->fix.smem_len,
  756. m->mode.xres * m->mode.yres * bytes_per_pixel);
  757. res = request_mem_region(res->start, resource_size(res),
  758. DRIVER_NAME);
  759. if (!res) {
  760. ret = -EBUSY;
  761. goto failed_req;
  762. }
  763. fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  764. if (IS_ERR(fbi->clk_ipg)) {
  765. ret = PTR_ERR(fbi->clk_ipg);
  766. goto failed_getclock;
  767. }
  768. /*
  769. * The LCDC controller does not have an enable bit. The
  770. * controller starts directly when the clocks are enabled.
  771. * If the clocks are enabled when the controller is not yet
  772. * programmed with proper register values (enabled at the
  773. * bootloader, for example) then it just goes into some undefined
  774. * state.
  775. * To avoid this issue, let's enable and disable LCDC IPG clock
  776. * so that we force some kind of 'reset' to the LCDC block.
  777. */
  778. ret = clk_prepare_enable(fbi->clk_ipg);
  779. if (ret)
  780. goto failed_getclock;
  781. clk_disable_unprepare(fbi->clk_ipg);
  782. fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  783. if (IS_ERR(fbi->clk_ahb)) {
  784. ret = PTR_ERR(fbi->clk_ahb);
  785. goto failed_getclock;
  786. }
  787. fbi->clk_per = devm_clk_get(&pdev->dev, "per");
  788. if (IS_ERR(fbi->clk_per)) {
  789. ret = PTR_ERR(fbi->clk_per);
  790. goto failed_getclock;
  791. }
  792. fbi->regs = ioremap(res->start, resource_size(res));
  793. if (fbi->regs == NULL) {
  794. dev_err(&pdev->dev, "Cannot map frame buffer registers\n");
  795. ret = -ENOMEM;
  796. goto failed_ioremap;
  797. }
  798. fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
  799. info->screen_buffer = dma_alloc_wc(&pdev->dev, fbi->map_size,
  800. &fbi->map_dma, GFP_KERNEL);
  801. if (!info->screen_buffer) {
  802. dev_err(&pdev->dev, "Failed to allocate video RAM\n");
  803. ret = -ENOMEM;
  804. goto failed_map;
  805. }
  806. info->fix.smem_start = fbi->map_dma;
  807. if (pdata && pdata->init) {
  808. ret = pdata->init(fbi->pdev);
  809. if (ret)
  810. goto failed_platform_init;
  811. }
  812. INIT_LIST_HEAD(&info->modelist);
  813. for (i = 0; i < fbi->num_modes; i++)
  814. fb_add_videomode(&fbi->mode[i].mode, &info->modelist);
  815. /*
  816. * This makes sure that our colour bitfield
  817. * descriptors are correctly initialised.
  818. */
  819. imxfb_check_var(&info->var, info);
  820. /*
  821. * For modes > 8bpp, the color map is bypassed.
  822. * Therefore, 256 entries are enough.
  823. */
  824. ret = fb_alloc_cmap(&info->cmap, 256, 0);
  825. if (ret < 0)
  826. goto failed_cmap;
  827. imxfb_set_par(info);
  828. ret = register_framebuffer(info);
  829. if (ret < 0) {
  830. dev_err(&pdev->dev, "failed to register framebuffer\n");
  831. goto failed_register;
  832. }
  833. fbi->lcd_pwr = devm_regulator_get(&pdev->dev, "lcd");
  834. if (PTR_ERR(fbi->lcd_pwr) == -EPROBE_DEFER) {
  835. ret = -EPROBE_DEFER;
  836. goto failed_lcd;
  837. }
  838. lcd = devm_lcd_device_register(&pdev->dev, "imxfb-lcd", &pdev->dev, fbi,
  839. &imxfb_lcd_ops);
  840. if (IS_ERR(lcd)) {
  841. ret = PTR_ERR(lcd);
  842. goto failed_lcd;
  843. }
  844. lcd->props.max_contrast = 0xff;
  845. imxfb_enable_controller(fbi);
  846. fbi->pdev = pdev;
  847. return 0;
  848. failed_lcd:
  849. unregister_framebuffer(info);
  850. failed_register:
  851. fb_dealloc_cmap(&info->cmap);
  852. failed_cmap:
  853. if (pdata && pdata->exit)
  854. pdata->exit(fbi->pdev);
  855. failed_platform_init:
  856. dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer,
  857. fbi->map_dma);
  858. failed_map:
  859. iounmap(fbi->regs);
  860. failed_ioremap:
  861. failed_getclock:
  862. release_mem_region(res->start, resource_size(res));
  863. failed_req:
  864. failed_of_parse:
  865. kfree(info->pseudo_palette);
  866. failed_init:
  867. framebuffer_release(info);
  868. return ret;
  869. }
  870. static int imxfb_remove(struct platform_device *pdev)
  871. {
  872. struct imx_fb_platform_data *pdata;
  873. struct fb_info *info = platform_get_drvdata(pdev);
  874. struct imxfb_info *fbi = info->par;
  875. struct resource *res;
  876. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  877. imxfb_disable_controller(fbi);
  878. unregister_framebuffer(info);
  879. fb_dealloc_cmap(&info->cmap);
  880. pdata = dev_get_platdata(&pdev->dev);
  881. if (pdata && pdata->exit)
  882. pdata->exit(fbi->pdev);
  883. dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer,
  884. fbi->map_dma);
  885. iounmap(fbi->regs);
  886. release_mem_region(res->start, resource_size(res));
  887. kfree(info->pseudo_palette);
  888. framebuffer_release(info);
  889. return 0;
  890. }
  891. static int __maybe_unused imxfb_suspend(struct device *dev)
  892. {
  893. struct fb_info *info = dev_get_drvdata(dev);
  894. struct imxfb_info *fbi = info->par;
  895. imxfb_disable_controller(fbi);
  896. return 0;
  897. }
  898. static int __maybe_unused imxfb_resume(struct device *dev)
  899. {
  900. struct fb_info *info = dev_get_drvdata(dev);
  901. struct imxfb_info *fbi = info->par;
  902. imxfb_enable_controller(fbi);
  903. return 0;
  904. }
  905. static SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume);
  906. static struct platform_driver imxfb_driver = {
  907. .driver = {
  908. .name = DRIVER_NAME,
  909. .of_match_table = imxfb_of_dev_id,
  910. .pm = &imxfb_pm_ops,
  911. },
  912. .probe = imxfb_probe,
  913. .remove = imxfb_remove,
  914. .id_table = imxfb_devtype,
  915. };
  916. module_platform_driver(imxfb_driver);
  917. MODULE_DESCRIPTION("Freescale i.MX framebuffer driver");
  918. MODULE_AUTHOR("Sascha Hauer, Pengutronix");
  919. MODULE_LICENSE("GPL");