i740_reg.h 8.9 KB

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  1. /**************************************************************************
  2. Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
  3. All Rights Reserved.
  4. Permission is hereby granted, free of charge, to any person obtaining a
  5. copy of this software and associated documentation files (the
  6. "Software"), to deal in the Software without restriction, including
  7. without limitation the rights to use, copy, modify, merge, publish,
  8. distribute, sub license, and/or sell copies of the Software, and to
  9. permit persons to whom the Software is furnished to do so, subject to
  10. the following conditions:
  11. The above copyright notice and this permission notice (including the
  12. next paragraph) shall be included in all copies or substantial portions
  13. of the Software.
  14. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15. OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  16. MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  17. IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  18. ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  19. TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  20. SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21. **************************************************************************/
  22. /*
  23. * Authors:
  24. * Kevin E. Martin <kevin@precisioninsight.com>
  25. */
  26. /* I/O register offsets */
  27. #define SRX VGA_SEQ_I
  28. #define GRX VGA_GFX_I
  29. #define ARX VGA_ATT_IW
  30. #define XRX 0x3D6
  31. #define MRX 0x3D2
  32. /* VGA Color Palette Registers */
  33. #define DACMASK 0x3C6
  34. #define DACSTATE 0x3C7
  35. #define DACRX 0x3C7
  36. #define DACWX 0x3C8
  37. #define DACDATA 0x3C9
  38. /* CRT Controller Registers (CRX) */
  39. #define START_ADDR_HI 0x0C
  40. #define START_ADDR_LO 0x0D
  41. #define VERT_SYNC_END 0x11
  42. #define EXT_VERT_TOTAL 0x30
  43. #define EXT_VERT_DISPLAY 0x31
  44. #define EXT_VERT_SYNC_START 0x32
  45. #define EXT_VERT_BLANK_START 0x33
  46. #define EXT_HORIZ_TOTAL 0x35
  47. #define EXT_HORIZ_BLANK 0x39
  48. #define EXT_START_ADDR 0x40
  49. #define EXT_START_ADDR_ENABLE 0x80
  50. #define EXT_OFFSET 0x41
  51. #define EXT_START_ADDR_HI 0x42
  52. #define INTERLACE_CNTL 0x70
  53. #define INTERLACE_ENABLE 0x80
  54. #define INTERLACE_DISABLE 0x00
  55. /* Miscellaneous Output Register */
  56. #define MSR_R 0x3CC
  57. #define MSR_W 0x3C2
  58. #define IO_ADDR_SELECT 0x01
  59. #define MDA_BASE 0x3B0
  60. #define CGA_BASE 0x3D0
  61. /* System Configuration Extension Registers (XRX) */
  62. #define IO_CTNL 0x09
  63. #define EXTENDED_ATTR_CNTL 0x02
  64. #define EXTENDED_CRTC_CNTL 0x01
  65. #define ADDRESS_MAPPING 0x0A
  66. #define PACKED_MODE_ENABLE 0x04
  67. #define LINEAR_MODE_ENABLE 0x02
  68. #define PAGE_MAPPING_ENABLE 0x01
  69. #define BITBLT_CNTL 0x20
  70. #define COLEXP_MODE 0x30
  71. #define COLEXP_8BPP 0x00
  72. #define COLEXP_16BPP 0x10
  73. #define COLEXP_24BPP 0x20
  74. #define COLEXP_RESERVED 0x30
  75. #define CHIP_RESET 0x02
  76. #define BITBLT_STATUS 0x01
  77. #define DISPLAY_CNTL 0x40
  78. #define VGA_WRAP_MODE 0x02
  79. #define VGA_WRAP_AT_256KB 0x00
  80. #define VGA_NO_WRAP 0x02
  81. #define GUI_MODE 0x01
  82. #define STANDARD_VGA_MODE 0x00
  83. #define HIRES_MODE 0x01
  84. #define DRAM_ROW_TYPE 0x50
  85. #define DRAM_ROW_0 0x07
  86. #define DRAM_ROW_0_SDRAM 0x00
  87. #define DRAM_ROW_0_EMPTY 0x07
  88. #define DRAM_ROW_1 0x38
  89. #define DRAM_ROW_1_SDRAM 0x00
  90. #define DRAM_ROW_1_EMPTY 0x38
  91. #define DRAM_ROW_CNTL_LO 0x51
  92. #define DRAM_CAS_LATENCY 0x10
  93. #define DRAM_RAS_TIMING 0x08
  94. #define DRAM_RAS_PRECHARGE 0x04
  95. #define DRAM_ROW_CNTL_HI 0x52
  96. #define DRAM_EXT_CNTL 0x53
  97. #define DRAM_REFRESH_RATE 0x03
  98. #define DRAM_REFRESH_DISABLE 0x00
  99. #define DRAM_REFRESH_60HZ 0x01
  100. #define DRAM_REFRESH_FAST_TEST 0x02
  101. #define DRAM_REFRESH_RESERVED 0x03
  102. #define DRAM_TIMING 0x54
  103. #define DRAM_ROW_BNDRY_0 0x55
  104. #define DRAM_ROW_BNDRY_1 0x56
  105. #define DPMS_SYNC_SELECT 0x61
  106. #define VSYNC_CNTL 0x08
  107. #define VSYNC_ON 0x00
  108. #define VSYNC_OFF 0x08
  109. #define HSYNC_CNTL 0x02
  110. #define HSYNC_ON 0x00
  111. #define HSYNC_OFF 0x02
  112. #define PIXPIPE_CONFIG_0 0x80
  113. #define DAC_8_BIT 0x80
  114. #define DAC_6_BIT 0x00
  115. #define HW_CURSOR_ENABLE 0x10
  116. #define EXTENDED_PALETTE 0x01
  117. #define PIXPIPE_CONFIG_1 0x81
  118. #define DISPLAY_COLOR_MODE 0x0F
  119. #define DISPLAY_VGA_MODE 0x00
  120. #define DISPLAY_8BPP_MODE 0x02
  121. #define DISPLAY_15BPP_MODE 0x04
  122. #define DISPLAY_16BPP_MODE 0x05
  123. #define DISPLAY_24BPP_MODE 0x06
  124. #define DISPLAY_32BPP_MODE 0x07
  125. #define PIXPIPE_CONFIG_2 0x82
  126. #define DISPLAY_GAMMA_ENABLE 0x08
  127. #define DISPLAY_GAMMA_DISABLE 0x00
  128. #define OVERLAY_GAMMA_ENABLE 0x04
  129. #define OVERLAY_GAMMA_DISABLE 0x00
  130. #define CURSOR_CONTROL 0xA0
  131. #define CURSOR_ORIGIN_SCREEN 0x00
  132. #define CURSOR_ORIGIN_DISPLAY 0x10
  133. #define CURSOR_MODE 0x07
  134. #define CURSOR_MODE_DISABLE 0x00
  135. #define CURSOR_MODE_32_4C_AX 0x01
  136. #define CURSOR_MODE_128_2C 0x02
  137. #define CURSOR_MODE_128_1C 0x03
  138. #define CURSOR_MODE_64_3C 0x04
  139. #define CURSOR_MODE_64_4C_AX 0x05
  140. #define CURSOR_MODE_64_4C 0x06
  141. #define CURSOR_MODE_RESERVED 0x07
  142. #define CURSOR_BASEADDR_LO 0xA2
  143. #define CURSOR_BASEADDR_HI 0xA3
  144. #define CURSOR_X_LO 0xA4
  145. #define CURSOR_X_HI 0xA5
  146. #define CURSOR_X_POS 0x00
  147. #define CURSOR_X_NEG 0x80
  148. #define CURSOR_Y_LO 0xA6
  149. #define CURSOR_Y_HI 0xA7
  150. #define CURSOR_Y_POS 0x00
  151. #define CURSOR_Y_NEG 0x80
  152. #define VCLK2_VCO_M 0xC8
  153. #define VCLK2_VCO_N 0xC9
  154. #define VCLK2_VCO_MN_MSBS 0xCA
  155. #define VCO_N_MSBS 0x30
  156. #define VCO_M_MSBS 0x03
  157. #define VCLK2_VCO_DIV_SEL 0xCB
  158. #define POST_DIV_SELECT 0x70
  159. #define POST_DIV_1 0x00
  160. #define POST_DIV_2 0x10
  161. #define POST_DIV_4 0x20
  162. #define POST_DIV_8 0x30
  163. #define POST_DIV_16 0x40
  164. #define POST_DIV_32 0x50
  165. #define VCO_LOOP_DIV_BY_4M 0x00
  166. #define VCO_LOOP_DIV_BY_16M 0x04
  167. #define REF_CLK_DIV_BY_5 0x02
  168. #define REF_DIV_4 0x00
  169. #define REF_DIV_1 0x01
  170. #define PLL_CNTL 0xCE
  171. #define PLL_MEMCLK_SEL 0x03
  172. #define PLL_MEMCLK__66667KHZ 0x00
  173. #define PLL_MEMCLK__75000KHZ 0x01
  174. #define PLL_MEMCLK__88889KHZ 0x02
  175. #define PLL_MEMCLK_100000KHZ 0x03
  176. /* Multimedia Extension Registers (MRX) */
  177. #define ACQ_CNTL_1 0x02
  178. #define ACQ_CNTL_2 0x03
  179. #define FRAME_CAP_MODE 0x01
  180. #define CONT_CAP_MODE 0x00
  181. #define SINGLE_CAP_MODE 0x01
  182. #define ACQ_CNTL_3 0x04
  183. #define COL_KEY_CNTL_1 0x3C
  184. #define BLANK_DISP_OVERLAY 0x20
  185. /* FIFOs */
  186. #define LP_FIFO 0x1000
  187. #define HP_FIFO 0x2000
  188. #define INSTPNT 0x3040
  189. #define LP_FIFO_COUNT 0x3040
  190. #define HP_FIFO_COUNT 0x3041
  191. /* FIFO Commands */
  192. #define CLIENT 0xE0000000
  193. #define CLIENT_2D 0x60000000
  194. /* Command Parser Mode Register */
  195. #define COMPARS 0x3038
  196. #define TWO_D_INST_DISABLE 0x08
  197. #define THREE_D_INST_DISABLE 0x04
  198. #define STATE_VAR_UPDATE_DISABLE 0x02
  199. #define PAL_STIP_DISABLE 0x01
  200. /* Interrupt Control Registers */
  201. #define IER 0x3030
  202. #define IIR 0x3032
  203. #define IMR 0x3034
  204. #define ISR 0x3036
  205. #define VMIINTB_EVENT 0x2000
  206. #define GPIO4_INT 0x1000
  207. #define DISP_FLIP_EVENT 0x0800
  208. #define DVD_PORT_DMA 0x0400
  209. #define DISP_VBLANK 0x0200
  210. #define FIFO_EMPTY_DMA_DONE 0x0100
  211. #define INST_PARSER_ERROR 0x0080
  212. #define USER_DEFINED 0x0040
  213. #define BREAKPOINT 0x0020
  214. #define DISP_HORIZ_COUNT 0x0010
  215. #define DISP_VSYNC 0x0008
  216. #define CAPTURE_HORIZ_COUNT 0x0004
  217. #define CAPTURE_VSYNC 0x0002
  218. #define THREE_D_PIPE_FLUSHED 0x0001
  219. /* FIFO Watermark and Burst Length Control Register */
  220. #define FWATER_BLC 0x00006000
  221. #define LMI_BURST_LENGTH 0x7F000000
  222. #define LMI_FIFO_WATERMARK 0x003F0000
  223. #define AGP_BURST_LENGTH 0x00007F00
  224. #define AGP_FIFO_WATERMARK 0x0000003F
  225. /* BitBLT Registers */
  226. #define SRC_DST_PITCH 0x00040000
  227. #define DST_PITCH 0x1FFF0000
  228. #define SRC_PITCH 0x00001FFF
  229. #define COLEXP_BG_COLOR 0x00040004
  230. #define COLEXP_FG_COLOR 0x00040008
  231. #define MONO_SRC_CNTL 0x0004000C
  232. #define MONO_USE_COLEXP 0x00000000
  233. #define MONO_USE_SRCEXP 0x08000000
  234. #define MONO_DATA_ALIGN 0x07000000
  235. #define MONO_BIT_ALIGN 0x01000000
  236. #define MONO_BYTE_ALIGN 0x02000000
  237. #define MONO_WORD_ALIGN 0x03000000
  238. #define MONO_DWORD_ALIGN 0x04000000
  239. #define MONO_QWORD_ALIGN 0x05000000
  240. #define MONO_SRC_INIT_DSCRD 0x003F0000
  241. #define MONO_SRC_RIGHT_CLIP 0x00003F00
  242. #define MONO_SRC_LEFT_CLIP 0x0000003F
  243. #define BITBLT_CONTROL 0x00040010
  244. #define BLTR_STATUS 0x80000000
  245. #define DYN_DEPTH 0x03000000
  246. #define DYN_DEPTH_8BPP 0x00000000
  247. #define DYN_DEPTH_16BPP 0x01000000
  248. #define DYN_DEPTH_24BPP 0x02000000
  249. #define DYN_DEPTH_32BPP 0x03000000 /* Unimplemented on the i740 */
  250. #define DYN_DEPTH_ENABLE 0x00800000
  251. #define PAT_VERT_ALIGN 0x00700000
  252. #define SOLID_PAT_SELECT 0x00080000
  253. #define PAT_IS_IN_COLOR 0x00000000
  254. #define PAT_IS_MONO 0x00040000
  255. #define MONO_PAT_TRANSP 0x00020000
  256. #define COLOR_TRANSP_ROP 0x00000000
  257. #define COLOR_TRANSP_DST 0x00008000
  258. #define COLOR_TRANSP_EQ 0x00000000
  259. #define COLOR_TRANSP_NOT_EQ 0x00010000
  260. #define COLOR_TRANSP_ENABLE 0x00004000
  261. #define MONO_SRC_TRANSP 0x00002000
  262. #define SRC_IS_IN_COLOR 0x00000000
  263. #define SRC_IS_MONO 0x00001000
  264. #define SRC_USE_SRC_ADDR 0x00000000
  265. #define SRC_USE_BLTDATA 0x00000400
  266. #define BLT_TOP_TO_BOT 0x00000000
  267. #define BLT_BOT_TO_TOP 0x00000200
  268. #define BLT_LEFT_TO_RIGHT 0x00000000
  269. #define BLT_RIGHT_TO_LEFT 0x00000100
  270. #define BLT_ROP 0x000000FF
  271. #define BLT_PAT_ADDR 0x00040014
  272. #define BLT_SRC_ADDR 0x00040018
  273. #define BLT_DST_ADDR 0x0004001C
  274. #define BLT_DST_H_W 0x00040020
  275. #define BLT_DST_HEIGHT 0x1FFF0000
  276. #define BLT_DST_WIDTH 0x00001FFF
  277. #define SRCEXP_BG_COLOR 0x00040024
  278. #define SRCEXP_FG_COLOR 0x00040028
  279. #define BLTDATA 0x00050000