cirrusfb.c 75 KB

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  1. /*
  2. * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
  3. *
  4. * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
  5. *
  6. * Contributors (thanks, all!)
  7. *
  8. * David Eger:
  9. * Overhaul for Linux 2.6
  10. *
  11. * Jeff Rugen:
  12. * Major contributions; Motorola PowerStack (PPC and PCI) support,
  13. * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
  14. *
  15. * Geert Uytterhoeven:
  16. * Excellent code review.
  17. *
  18. * Lars Hecking:
  19. * Amiga updates and testing.
  20. *
  21. * Original cirrusfb author: Frank Neumann
  22. *
  23. * Based on retz3fb.c and cirrusfb.c:
  24. * Copyright (C) 1997 Jes Sorensen
  25. * Copyright (C) 1996 Frank Neumann
  26. *
  27. ***************************************************************
  28. *
  29. * Format this code with GNU indent '-kr -i8 -pcs' options.
  30. *
  31. * This file is subject to the terms and conditions of the GNU General Public
  32. * License. See the file COPYING in the main directory of this archive
  33. * for more details.
  34. *
  35. */
  36. #include <linux/module.h>
  37. #include <linux/kernel.h>
  38. #include <linux/errno.h>
  39. #include <linux/string.h>
  40. #include <linux/mm.h>
  41. #include <linux/delay.h>
  42. #include <linux/fb.h>
  43. #include <linux/init.h>
  44. #ifdef CONFIG_ZORRO
  45. #include <linux/zorro.h>
  46. #endif
  47. #ifdef CONFIG_PCI
  48. #include <linux/pci.h>
  49. #endif
  50. #ifdef CONFIG_AMIGA
  51. #include <asm/amigahw.h>
  52. #endif
  53. #include <video/vga.h>
  54. #include <video/cirrus.h>
  55. /*****************************************************************
  56. *
  57. * debugging and utility macros
  58. *
  59. */
  60. /* disable runtime assertions? */
  61. /* #define CIRRUSFB_NDEBUG */
  62. /* debugging assertions */
  63. #ifndef CIRRUSFB_NDEBUG
  64. #define assert(expr) \
  65. if (!(expr)) { \
  66. printk("Assertion failed! %s,%s,%s,line=%d\n", \
  67. #expr, __FILE__, __func__, __LINE__); \
  68. }
  69. #else
  70. #define assert(expr)
  71. #endif
  72. #define MB_ (1024 * 1024)
  73. /*****************************************************************
  74. *
  75. * chipset information
  76. *
  77. */
  78. /* board types */
  79. enum cirrus_board {
  80. BT_NONE = 0,
  81. BT_SD64, /* GD5434 */
  82. BT_PICCOLO, /* GD5426 */
  83. BT_PICASSO, /* GD5426 or GD5428 */
  84. BT_SPECTRUM, /* GD5426 or GD5428 */
  85. BT_PICASSO4, /* GD5446 */
  86. BT_ALPINE, /* GD543x/4x */
  87. BT_GD5480,
  88. BT_LAGUNA, /* GD5462/64 */
  89. BT_LAGUNAB, /* GD5465 */
  90. };
  91. /*
  92. * per-board-type information, used for enumerating and abstracting
  93. * chip-specific information
  94. * NOTE: MUST be in the same order as enum cirrus_board in order to
  95. * use direct indexing on this array
  96. * NOTE: '__initdata' cannot be used as some of this info
  97. * is required at runtime. Maybe separate into an init-only and
  98. * a run-time table?
  99. */
  100. static const struct cirrusfb_board_info_rec {
  101. char *name; /* ASCII name of chipset */
  102. long maxclock[5]; /* maximum video clock */
  103. /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
  104. bool init_sr07 : 1; /* init SR07 during init_vgachip() */
  105. bool init_sr1f : 1; /* write SR1F during init_vgachip() */
  106. /* construct bit 19 of screen start address */
  107. bool scrn_start_bit19 : 1;
  108. /* initial SR07 value, then for each mode */
  109. unsigned char sr07;
  110. unsigned char sr07_1bpp;
  111. unsigned char sr07_1bpp_mux;
  112. unsigned char sr07_8bpp;
  113. unsigned char sr07_8bpp_mux;
  114. unsigned char sr1f; /* SR1F VGA initial register value */
  115. } cirrusfb_board_info[] = {
  116. [BT_SD64] = {
  117. .name = "CL SD64",
  118. .maxclock = {
  119. /* guess */
  120. /* the SD64/P4 have a higher max. videoclock */
  121. 135100, 135100, 85500, 85500, 0
  122. },
  123. .init_sr07 = true,
  124. .init_sr1f = true,
  125. .scrn_start_bit19 = true,
  126. .sr07 = 0xF0,
  127. .sr07_1bpp = 0xF0,
  128. .sr07_1bpp_mux = 0xF6,
  129. .sr07_8bpp = 0xF1,
  130. .sr07_8bpp_mux = 0xF7,
  131. .sr1f = 0x1E
  132. },
  133. [BT_PICCOLO] = {
  134. .name = "CL Piccolo",
  135. .maxclock = {
  136. /* guess */
  137. 90000, 90000, 90000, 90000, 90000
  138. },
  139. .init_sr07 = true,
  140. .init_sr1f = true,
  141. .scrn_start_bit19 = false,
  142. .sr07 = 0x80,
  143. .sr07_1bpp = 0x80,
  144. .sr07_8bpp = 0x81,
  145. .sr1f = 0x22
  146. },
  147. [BT_PICASSO] = {
  148. .name = "CL Picasso",
  149. .maxclock = {
  150. /* guess */
  151. 90000, 90000, 90000, 90000, 90000
  152. },
  153. .init_sr07 = true,
  154. .init_sr1f = true,
  155. .scrn_start_bit19 = false,
  156. .sr07 = 0x20,
  157. .sr07_1bpp = 0x20,
  158. .sr07_8bpp = 0x21,
  159. .sr1f = 0x22
  160. },
  161. [BT_SPECTRUM] = {
  162. .name = "CL Spectrum",
  163. .maxclock = {
  164. /* guess */
  165. 90000, 90000, 90000, 90000, 90000
  166. },
  167. .init_sr07 = true,
  168. .init_sr1f = true,
  169. .scrn_start_bit19 = false,
  170. .sr07 = 0x80,
  171. .sr07_1bpp = 0x80,
  172. .sr07_8bpp = 0x81,
  173. .sr1f = 0x22
  174. },
  175. [BT_PICASSO4] = {
  176. .name = "CL Picasso4",
  177. .maxclock = {
  178. 135100, 135100, 85500, 85500, 0
  179. },
  180. .init_sr07 = true,
  181. .init_sr1f = false,
  182. .scrn_start_bit19 = true,
  183. .sr07 = 0xA0,
  184. .sr07_1bpp = 0xA0,
  185. .sr07_1bpp_mux = 0xA6,
  186. .sr07_8bpp = 0xA1,
  187. .sr07_8bpp_mux = 0xA7,
  188. .sr1f = 0
  189. },
  190. [BT_ALPINE] = {
  191. .name = "CL Alpine",
  192. .maxclock = {
  193. /* for the GD5430. GD5446 can do more... */
  194. 85500, 85500, 50000, 28500, 0
  195. },
  196. .init_sr07 = true,
  197. .init_sr1f = true,
  198. .scrn_start_bit19 = true,
  199. .sr07 = 0xA0,
  200. .sr07_1bpp = 0xA0,
  201. .sr07_1bpp_mux = 0xA6,
  202. .sr07_8bpp = 0xA1,
  203. .sr07_8bpp_mux = 0xA7,
  204. .sr1f = 0x1C
  205. },
  206. [BT_GD5480] = {
  207. .name = "CL GD5480",
  208. .maxclock = {
  209. 135100, 200000, 200000, 135100, 135100
  210. },
  211. .init_sr07 = true,
  212. .init_sr1f = true,
  213. .scrn_start_bit19 = true,
  214. .sr07 = 0x10,
  215. .sr07_1bpp = 0x11,
  216. .sr07_8bpp = 0x11,
  217. .sr1f = 0x1C
  218. },
  219. [BT_LAGUNA] = {
  220. .name = "CL Laguna",
  221. .maxclock = {
  222. /* taken from X11 code */
  223. 170000, 170000, 170000, 170000, 135100,
  224. },
  225. .init_sr07 = false,
  226. .init_sr1f = false,
  227. .scrn_start_bit19 = true,
  228. },
  229. [BT_LAGUNAB] = {
  230. .name = "CL Laguna AGP",
  231. .maxclock = {
  232. /* taken from X11 code */
  233. 170000, 250000, 170000, 170000, 135100,
  234. },
  235. .init_sr07 = false,
  236. .init_sr1f = false,
  237. .scrn_start_bit19 = true,
  238. }
  239. };
  240. #ifdef CONFIG_PCI
  241. #define CHIP(id, btype) \
  242. { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
  243. static struct pci_device_id cirrusfb_pci_table[] = {
  244. CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
  245. CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
  246. CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
  247. CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
  248. CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
  249. CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
  250. CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
  251. CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
  252. CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
  253. CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
  254. CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
  255. { 0, }
  256. };
  257. MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
  258. #undef CHIP
  259. #endif /* CONFIG_PCI */
  260. #ifdef CONFIG_ZORRO
  261. struct zorrocl {
  262. enum cirrus_board type; /* Board type */
  263. u32 regoffset; /* Offset of registers in first Zorro device */
  264. u32 ramsize; /* Size of video RAM in first Zorro device */
  265. /* If zero, use autoprobe on RAM device */
  266. u32 ramoffset; /* Offset of video RAM in first Zorro device */
  267. zorro_id ramid; /* Zorro ID of RAM device */
  268. zorro_id ramid2; /* Zorro ID of optional second RAM device */
  269. };
  270. static const struct zorrocl zcl_sd64 = {
  271. .type = BT_SD64,
  272. .ramid = ZORRO_PROD_HELFRICH_SD64_RAM,
  273. };
  274. static const struct zorrocl zcl_piccolo = {
  275. .type = BT_PICCOLO,
  276. .ramid = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
  277. };
  278. static const struct zorrocl zcl_picasso = {
  279. .type = BT_PICASSO,
  280. .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
  281. };
  282. static const struct zorrocl zcl_spectrum = {
  283. .type = BT_SPECTRUM,
  284. .ramid = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
  285. };
  286. static const struct zorrocl zcl_picasso4_z3 = {
  287. .type = BT_PICASSO4,
  288. .regoffset = 0x00600000,
  289. .ramsize = 4 * MB_,
  290. .ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */
  291. };
  292. static const struct zorrocl zcl_picasso4_z2 = {
  293. .type = BT_PICASSO4,
  294. .regoffset = 0x10000,
  295. .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
  296. .ramid2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
  297. };
  298. static const struct zorro_device_id cirrusfb_zorro_table[] = {
  299. {
  300. .id = ZORRO_PROD_HELFRICH_SD64_REG,
  301. .driver_data = (unsigned long)&zcl_sd64,
  302. }, {
  303. .id = ZORRO_PROD_HELFRICH_PICCOLO_REG,
  304. .driver_data = (unsigned long)&zcl_piccolo,
  305. }, {
  306. .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
  307. .driver_data = (unsigned long)&zcl_picasso,
  308. }, {
  309. .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
  310. .driver_data = (unsigned long)&zcl_spectrum,
  311. }, {
  312. .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
  313. .driver_data = (unsigned long)&zcl_picasso4_z3,
  314. }, {
  315. .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
  316. .driver_data = (unsigned long)&zcl_picasso4_z2,
  317. },
  318. { 0 }
  319. };
  320. MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
  321. #endif /* CONFIG_ZORRO */
  322. #ifdef CIRRUSFB_DEBUG
  323. enum cirrusfb_dbg_reg_class {
  324. CRT,
  325. SEQ
  326. };
  327. #endif /* CIRRUSFB_DEBUG */
  328. /* info about board */
  329. struct cirrusfb_info {
  330. u8 __iomem *regbase;
  331. u8 __iomem *laguna_mmio;
  332. enum cirrus_board btype;
  333. unsigned char SFR; /* Shadow of special function register */
  334. int multiplexing;
  335. int doubleVCLK;
  336. int blank_mode;
  337. u32 pseudo_palette[16];
  338. void (*unmap)(struct fb_info *info);
  339. };
  340. static bool noaccel;
  341. static char *mode_option = "640x480@60";
  342. /****************************************************************************/
  343. /**** BEGIN PROTOTYPES ******************************************************/
  344. /*--- Interface used by the world ------------------------------------------*/
  345. static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
  346. struct fb_info *info);
  347. /*--- Internal routines ----------------------------------------------------*/
  348. static void init_vgachip(struct fb_info *info);
  349. static void switch_monitor(struct cirrusfb_info *cinfo, int on);
  350. static void WGen(const struct cirrusfb_info *cinfo,
  351. int regnum, unsigned char val);
  352. static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
  353. static void AttrOn(const struct cirrusfb_info *cinfo);
  354. static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
  355. static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
  356. static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
  357. static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
  358. unsigned char red, unsigned char green, unsigned char blue);
  359. #if 0
  360. static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
  361. unsigned char *red, unsigned char *green,
  362. unsigned char *blue);
  363. #endif
  364. static void cirrusfb_WaitBLT(u8 __iomem *regbase);
  365. static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
  366. u_short curx, u_short cury,
  367. u_short destx, u_short desty,
  368. u_short width, u_short height,
  369. u_short line_length);
  370. static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
  371. u_short x, u_short y,
  372. u_short width, u_short height,
  373. u32 fg_color, u32 bg_color,
  374. u_short line_length, u_char blitmode);
  375. static void bestclock(long freq, int *nom, int *den, int *div);
  376. #ifdef CIRRUSFB_DEBUG
  377. static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
  378. static void cirrusfb_dbg_print_regs(struct fb_info *info,
  379. caddr_t regbase,
  380. enum cirrusfb_dbg_reg_class reg_class, ...);
  381. #endif /* CIRRUSFB_DEBUG */
  382. /*** END PROTOTYPES ********************************************************/
  383. /*****************************************************************************/
  384. /*** BEGIN Interface Used by the World ***************************************/
  385. static inline int is_laguna(const struct cirrusfb_info *cinfo)
  386. {
  387. return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
  388. }
  389. static int opencount;
  390. /*--- Open /dev/fbx ---------------------------------------------------------*/
  391. static int cirrusfb_open(struct fb_info *info, int user)
  392. {
  393. if (opencount++ == 0)
  394. switch_monitor(info->par, 1);
  395. return 0;
  396. }
  397. /*--- Close /dev/fbx --------------------------------------------------------*/
  398. static int cirrusfb_release(struct fb_info *info, int user)
  399. {
  400. if (--opencount == 0)
  401. switch_monitor(info->par, 0);
  402. return 0;
  403. }
  404. /**** END Interface used by the World *************************************/
  405. /****************************************************************************/
  406. /**** BEGIN Hardware specific Routines **************************************/
  407. /* Check if the MCLK is not a better clock source */
  408. static int cirrusfb_check_mclk(struct fb_info *info, long freq)
  409. {
  410. struct cirrusfb_info *cinfo = info->par;
  411. long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
  412. /* Read MCLK value */
  413. mclk = (14318 * mclk) >> 3;
  414. dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
  415. /* Determine if we should use MCLK instead of VCLK, and if so, what we
  416. * should divide it by to get VCLK
  417. */
  418. if (abs(freq - mclk) < 250) {
  419. dev_dbg(info->device, "Using VCLK = MCLK\n");
  420. return 1;
  421. } else if (abs(freq - (mclk / 2)) < 250) {
  422. dev_dbg(info->device, "Using VCLK = MCLK/2\n");
  423. return 2;
  424. }
  425. return 0;
  426. }
  427. static int cirrusfb_check_pixclock(struct fb_var_screeninfo *var,
  428. struct fb_info *info)
  429. {
  430. long freq;
  431. long maxclock;
  432. struct cirrusfb_info *cinfo = info->par;
  433. unsigned maxclockidx = var->bits_per_pixel >> 3;
  434. /* convert from ps to kHz */
  435. freq = PICOS2KHZ(var->pixclock ? : 1);
  436. maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
  437. cinfo->multiplexing = 0;
  438. /* If the frequency is greater than we can support, we might be able
  439. * to use multiplexing for the video mode */
  440. if (freq > maxclock) {
  441. var->pixclock = KHZ2PICOS(maxclock);
  442. while ((freq = PICOS2KHZ(var->pixclock)) > maxclock)
  443. var->pixclock++;
  444. }
  445. dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
  446. /*
  447. * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
  448. * pixel clock
  449. */
  450. if (var->bits_per_pixel == 8) {
  451. switch (cinfo->btype) {
  452. case BT_ALPINE:
  453. case BT_SD64:
  454. case BT_PICASSO4:
  455. if (freq > 85500)
  456. cinfo->multiplexing = 1;
  457. break;
  458. case BT_GD5480:
  459. if (freq > 135100)
  460. cinfo->multiplexing = 1;
  461. break;
  462. default:
  463. break;
  464. }
  465. }
  466. /* If we have a 1MB 5434, we need to put ourselves in a mode where
  467. * the VCLK is double the pixel clock. */
  468. cinfo->doubleVCLK = 0;
  469. if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
  470. var->bits_per_pixel == 16) {
  471. cinfo->doubleVCLK = 1;
  472. }
  473. return 0;
  474. }
  475. static int cirrusfb_check_var(struct fb_var_screeninfo *var,
  476. struct fb_info *info)
  477. {
  478. int yres;
  479. /* memory size in pixels */
  480. unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
  481. struct cirrusfb_info *cinfo = info->par;
  482. switch (var->bits_per_pixel) {
  483. case 1:
  484. var->red.offset = 0;
  485. var->red.length = 1;
  486. var->green = var->red;
  487. var->blue = var->red;
  488. break;
  489. case 8:
  490. var->red.offset = 0;
  491. var->red.length = 8;
  492. var->green = var->red;
  493. var->blue = var->red;
  494. break;
  495. case 16:
  496. var->red.offset = 11;
  497. var->green.offset = 5;
  498. var->blue.offset = 0;
  499. var->red.length = 5;
  500. var->green.length = 6;
  501. var->blue.length = 5;
  502. break;
  503. case 24:
  504. var->red.offset = 16;
  505. var->green.offset = 8;
  506. var->blue.offset = 0;
  507. var->red.length = 8;
  508. var->green.length = 8;
  509. var->blue.length = 8;
  510. break;
  511. default:
  512. dev_dbg(info->device,
  513. "Unsupported bpp size: %d\n", var->bits_per_pixel);
  514. return -EINVAL;
  515. }
  516. if (var->xres_virtual < var->xres)
  517. var->xres_virtual = var->xres;
  518. /* use highest possible virtual resolution */
  519. if (var->yres_virtual == -1) {
  520. var->yres_virtual = pixels / var->xres_virtual;
  521. dev_info(info->device,
  522. "virtual resolution set to maximum of %dx%d\n",
  523. var->xres_virtual, var->yres_virtual);
  524. }
  525. if (var->yres_virtual < var->yres)
  526. var->yres_virtual = var->yres;
  527. if (var->xres_virtual * var->yres_virtual > pixels) {
  528. dev_err(info->device, "mode %dx%dx%d rejected... "
  529. "virtual resolution too high to fit into video memory!\n",
  530. var->xres_virtual, var->yres_virtual,
  531. var->bits_per_pixel);
  532. return -EINVAL;
  533. }
  534. /* truncate xoffset and yoffset to maximum if too high */
  535. if (var->xoffset > var->xres_virtual - var->xres)
  536. var->xoffset = var->xres_virtual - var->xres - 1;
  537. if (var->yoffset > var->yres_virtual - var->yres)
  538. var->yoffset = var->yres_virtual - var->yres - 1;
  539. var->red.msb_right =
  540. var->green.msb_right =
  541. var->blue.msb_right =
  542. var->transp.offset =
  543. var->transp.length =
  544. var->transp.msb_right = 0;
  545. yres = var->yres;
  546. if (var->vmode & FB_VMODE_DOUBLE)
  547. yres *= 2;
  548. else if (var->vmode & FB_VMODE_INTERLACED)
  549. yres = (yres + 1) / 2;
  550. if (yres >= 1280) {
  551. dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
  552. "special treatment required! (TODO)\n");
  553. return -EINVAL;
  554. }
  555. if (cirrusfb_check_pixclock(var, info))
  556. return -EINVAL;
  557. if (!is_laguna(cinfo))
  558. var->accel_flags = FB_ACCELF_TEXT;
  559. return 0;
  560. }
  561. static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
  562. {
  563. struct cirrusfb_info *cinfo = info->par;
  564. unsigned char old1f, old1e;
  565. assert(cinfo != NULL);
  566. old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
  567. if (div) {
  568. dev_dbg(info->device, "Set %s as pixclock source.\n",
  569. (div == 2) ? "MCLK/2" : "MCLK");
  570. old1f |= 0x40;
  571. old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
  572. if (div == 2)
  573. old1e |= 1;
  574. vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
  575. }
  576. vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
  577. }
  578. /*************************************************************************
  579. cirrusfb_set_par_foo()
  580. actually writes the values for a new video mode into the hardware,
  581. **************************************************************************/
  582. static int cirrusfb_set_par_foo(struct fb_info *info)
  583. {
  584. struct cirrusfb_info *cinfo = info->par;
  585. struct fb_var_screeninfo *var = &info->var;
  586. u8 __iomem *regbase = cinfo->regbase;
  587. unsigned char tmp;
  588. int pitch;
  589. const struct cirrusfb_board_info_rec *bi;
  590. int hdispend, hsyncstart, hsyncend, htotal;
  591. int yres, vdispend, vsyncstart, vsyncend, vtotal;
  592. long freq;
  593. int nom, den, div;
  594. unsigned int control = 0, format = 0, threshold = 0;
  595. dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
  596. var->xres, var->yres, var->bits_per_pixel);
  597. switch (var->bits_per_pixel) {
  598. case 1:
  599. info->fix.line_length = var->xres_virtual / 8;
  600. info->fix.visual = FB_VISUAL_MONO10;
  601. break;
  602. case 8:
  603. info->fix.line_length = var->xres_virtual;
  604. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  605. break;
  606. case 16:
  607. case 24:
  608. info->fix.line_length = var->xres_virtual *
  609. var->bits_per_pixel >> 3;
  610. info->fix.visual = FB_VISUAL_TRUECOLOR;
  611. break;
  612. }
  613. info->fix.type = FB_TYPE_PACKED_PIXELS;
  614. init_vgachip(info);
  615. bi = &cirrusfb_board_info[cinfo->btype];
  616. hsyncstart = var->xres + var->right_margin;
  617. hsyncend = hsyncstart + var->hsync_len;
  618. htotal = (hsyncend + var->left_margin) / 8;
  619. hdispend = var->xres / 8;
  620. hsyncstart = hsyncstart / 8;
  621. hsyncend = hsyncend / 8;
  622. vdispend = var->yres;
  623. vsyncstart = vdispend + var->lower_margin;
  624. vsyncend = vsyncstart + var->vsync_len;
  625. vtotal = vsyncend + var->upper_margin;
  626. if (var->vmode & FB_VMODE_DOUBLE) {
  627. vdispend *= 2;
  628. vsyncstart *= 2;
  629. vsyncend *= 2;
  630. vtotal *= 2;
  631. } else if (var->vmode & FB_VMODE_INTERLACED) {
  632. vdispend = (vdispend + 1) / 2;
  633. vsyncstart = (vsyncstart + 1) / 2;
  634. vsyncend = (vsyncend + 1) / 2;
  635. vtotal = (vtotal + 1) / 2;
  636. }
  637. yres = vdispend;
  638. if (yres >= 1024) {
  639. vtotal /= 2;
  640. vsyncstart /= 2;
  641. vsyncend /= 2;
  642. vdispend /= 2;
  643. }
  644. vdispend -= 1;
  645. vsyncstart -= 1;
  646. vsyncend -= 1;
  647. vtotal -= 2;
  648. if (cinfo->multiplexing) {
  649. htotal /= 2;
  650. hsyncstart /= 2;
  651. hsyncend /= 2;
  652. hdispend /= 2;
  653. }
  654. htotal -= 5;
  655. hdispend -= 1;
  656. hsyncstart += 1;
  657. hsyncend += 1;
  658. /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
  659. vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
  660. /* if debugging is enabled, all parameters get output before writing */
  661. dev_dbg(info->device, "CRT0: %d\n", htotal);
  662. vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
  663. dev_dbg(info->device, "CRT1: %d\n", hdispend);
  664. vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
  665. dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
  666. vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
  667. /* + 128: Compatible read */
  668. dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
  669. vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
  670. 128 + ((htotal + 5) % 32));
  671. dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
  672. vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
  673. tmp = hsyncend % 32;
  674. if ((htotal + 5) & 32)
  675. tmp += 128;
  676. dev_dbg(info->device, "CRT5: %d\n", tmp);
  677. vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
  678. dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
  679. vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
  680. tmp = 16; /* LineCompare bit #9 */
  681. if (vtotal & 256)
  682. tmp |= 1;
  683. if (vdispend & 256)
  684. tmp |= 2;
  685. if (vsyncstart & 256)
  686. tmp |= 4;
  687. if ((vdispend + 1) & 256)
  688. tmp |= 8;
  689. if (vtotal & 512)
  690. tmp |= 32;
  691. if (vdispend & 512)
  692. tmp |= 64;
  693. if (vsyncstart & 512)
  694. tmp |= 128;
  695. dev_dbg(info->device, "CRT7: %d\n", tmp);
  696. vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
  697. tmp = 0x40; /* LineCompare bit #8 */
  698. if ((vdispend + 1) & 512)
  699. tmp |= 0x20;
  700. if (var->vmode & FB_VMODE_DOUBLE)
  701. tmp |= 0x80;
  702. dev_dbg(info->device, "CRT9: %d\n", tmp);
  703. vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
  704. dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
  705. vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
  706. dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
  707. vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
  708. dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
  709. vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
  710. dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
  711. vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
  712. dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
  713. vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
  714. dev_dbg(info->device, "CRT18: 0xff\n");
  715. vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
  716. tmp = 0;
  717. if (var->vmode & FB_VMODE_INTERLACED)
  718. tmp |= 1;
  719. if ((htotal + 5) & 64)
  720. tmp |= 16;
  721. if ((htotal + 5) & 128)
  722. tmp |= 32;
  723. if (vtotal & 256)
  724. tmp |= 64;
  725. if (vtotal & 512)
  726. tmp |= 128;
  727. dev_dbg(info->device, "CRT1a: %d\n", tmp);
  728. vga_wcrt(regbase, CL_CRT1A, tmp);
  729. freq = PICOS2KHZ(var->pixclock);
  730. if (var->bits_per_pixel == 24)
  731. if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
  732. freq *= 3;
  733. if (cinfo->multiplexing)
  734. freq /= 2;
  735. if (cinfo->doubleVCLK)
  736. freq *= 2;
  737. bestclock(freq, &nom, &den, &div);
  738. dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
  739. freq, nom, den, div);
  740. /* set VCLK0 */
  741. /* hardware RefClock: 14.31818 MHz */
  742. /* formula: VClk = (OSC * N) / (D * (1+P)) */
  743. /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
  744. if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
  745. cinfo->btype == BT_SD64) {
  746. /* if freq is close to mclk or mclk/2 select mclk
  747. * as clock source
  748. */
  749. int divMCLK = cirrusfb_check_mclk(info, freq);
  750. if (divMCLK)
  751. nom = 0;
  752. cirrusfb_set_mclk_as_source(info, divMCLK);
  753. }
  754. if (is_laguna(cinfo)) {
  755. long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
  756. unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
  757. unsigned short tile_control;
  758. if (cinfo->btype == BT_LAGUNAB) {
  759. tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
  760. tile_control &= ~0x80;
  761. fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
  762. }
  763. fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
  764. fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
  765. control = fb_readw(cinfo->laguna_mmio + 0x402);
  766. threshold = fb_readw(cinfo->laguna_mmio + 0xea);
  767. control &= ~0x6800;
  768. format = 0;
  769. threshold &= 0xffc0 & 0x3fbf;
  770. }
  771. if (nom) {
  772. tmp = den << 1;
  773. if (div != 0)
  774. tmp |= 1;
  775. /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
  776. if ((cinfo->btype == BT_SD64) ||
  777. (cinfo->btype == BT_ALPINE) ||
  778. (cinfo->btype == BT_GD5480))
  779. tmp |= 0x80;
  780. /* Laguna chipset has reversed clock registers */
  781. if (is_laguna(cinfo)) {
  782. vga_wseq(regbase, CL_SEQRE, tmp);
  783. vga_wseq(regbase, CL_SEQR1E, nom);
  784. } else {
  785. vga_wseq(regbase, CL_SEQRE, nom);
  786. vga_wseq(regbase, CL_SEQR1E, tmp);
  787. }
  788. }
  789. if (yres >= 1024)
  790. /* 1280x1024 */
  791. vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
  792. else
  793. /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
  794. * address wrap, no compat. */
  795. vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
  796. /* don't know if it would hurt to also program this if no interlaced */
  797. /* mode is used, but I feel better this way.. :-) */
  798. if (var->vmode & FB_VMODE_INTERLACED)
  799. vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
  800. else
  801. vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
  802. /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
  803. /* enable display memory & CRTC I/O address for color mode */
  804. tmp = 0x03 | 0xc;
  805. if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  806. tmp |= 0x40;
  807. if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  808. tmp |= 0x80;
  809. WGen(cinfo, VGA_MIS_W, tmp);
  810. /* text cursor on and start line */
  811. vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
  812. /* text cursor end line */
  813. vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
  814. /******************************************************
  815. *
  816. * 1 bpp
  817. *
  818. */
  819. /* programming for different color depths */
  820. if (var->bits_per_pixel == 1) {
  821. dev_dbg(info->device, "preparing for 1 bit deep display\n");
  822. vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
  823. /* SR07 */
  824. switch (cinfo->btype) {
  825. case BT_SD64:
  826. case BT_PICCOLO:
  827. case BT_PICASSO:
  828. case BT_SPECTRUM:
  829. case BT_PICASSO4:
  830. case BT_ALPINE:
  831. case BT_GD5480:
  832. vga_wseq(regbase, CL_SEQR7,
  833. cinfo->multiplexing ?
  834. bi->sr07_1bpp_mux : bi->sr07_1bpp);
  835. break;
  836. case BT_LAGUNA:
  837. case BT_LAGUNAB:
  838. vga_wseq(regbase, CL_SEQR7,
  839. vga_rseq(regbase, CL_SEQR7) & ~0x01);
  840. break;
  841. default:
  842. dev_warn(info->device, "unknown Board\n");
  843. break;
  844. }
  845. /* Extended Sequencer Mode */
  846. switch (cinfo->btype) {
  847. case BT_PICCOLO:
  848. case BT_SPECTRUM:
  849. /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
  850. vga_wseq(regbase, CL_SEQRF, 0xb0);
  851. break;
  852. case BT_PICASSO:
  853. /* ## vorher d0 avoid FIFO underruns..? */
  854. vga_wseq(regbase, CL_SEQRF, 0xd0);
  855. break;
  856. case BT_SD64:
  857. case BT_PICASSO4:
  858. case BT_ALPINE:
  859. case BT_GD5480:
  860. case BT_LAGUNA:
  861. case BT_LAGUNAB:
  862. /* do nothing */
  863. break;
  864. default:
  865. dev_warn(info->device, "unknown Board\n");
  866. break;
  867. }
  868. /* pixel mask: pass-through for first plane */
  869. WGen(cinfo, VGA_PEL_MSK, 0x01);
  870. if (cinfo->multiplexing)
  871. /* hidden dac reg: 1280x1024 */
  872. WHDR(cinfo, 0x4a);
  873. else
  874. /* hidden dac: nothing */
  875. WHDR(cinfo, 0);
  876. /* memory mode: odd/even, ext. memory */
  877. vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
  878. /* plane mask: only write to first plane */
  879. vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
  880. }
  881. /******************************************************
  882. *
  883. * 8 bpp
  884. *
  885. */
  886. else if (var->bits_per_pixel == 8) {
  887. dev_dbg(info->device, "preparing for 8 bit deep display\n");
  888. switch (cinfo->btype) {
  889. case BT_SD64:
  890. case BT_PICCOLO:
  891. case BT_PICASSO:
  892. case BT_SPECTRUM:
  893. case BT_PICASSO4:
  894. case BT_ALPINE:
  895. case BT_GD5480:
  896. vga_wseq(regbase, CL_SEQR7,
  897. cinfo->multiplexing ?
  898. bi->sr07_8bpp_mux : bi->sr07_8bpp);
  899. break;
  900. case BT_LAGUNA:
  901. case BT_LAGUNAB:
  902. vga_wseq(regbase, CL_SEQR7,
  903. vga_rseq(regbase, CL_SEQR7) | 0x01);
  904. threshold |= 0x10;
  905. break;
  906. default:
  907. dev_warn(info->device, "unknown Board\n");
  908. break;
  909. }
  910. switch (cinfo->btype) {
  911. case BT_PICCOLO:
  912. case BT_PICASSO:
  913. case BT_SPECTRUM:
  914. /* Fast Page-Mode writes */
  915. vga_wseq(regbase, CL_SEQRF, 0xb0);
  916. break;
  917. case BT_PICASSO4:
  918. #ifdef CONFIG_ZORRO
  919. /* ### INCOMPLETE!! */
  920. vga_wseq(regbase, CL_SEQRF, 0xb8);
  921. #endif
  922. case BT_ALPINE:
  923. case BT_SD64:
  924. case BT_GD5480:
  925. case BT_LAGUNA:
  926. case BT_LAGUNAB:
  927. /* do nothing */
  928. break;
  929. default:
  930. dev_warn(info->device, "unknown board\n");
  931. break;
  932. }
  933. /* mode register: 256 color mode */
  934. vga_wgfx(regbase, VGA_GFX_MODE, 64);
  935. if (cinfo->multiplexing)
  936. /* hidden dac reg: 1280x1024 */
  937. WHDR(cinfo, 0x4a);
  938. else
  939. /* hidden dac: nothing */
  940. WHDR(cinfo, 0);
  941. }
  942. /******************************************************
  943. *
  944. * 16 bpp
  945. *
  946. */
  947. else if (var->bits_per_pixel == 16) {
  948. dev_dbg(info->device, "preparing for 16 bit deep display\n");
  949. switch (cinfo->btype) {
  950. case BT_PICCOLO:
  951. case BT_SPECTRUM:
  952. vga_wseq(regbase, CL_SEQR7, 0x87);
  953. /* Fast Page-Mode writes */
  954. vga_wseq(regbase, CL_SEQRF, 0xb0);
  955. break;
  956. case BT_PICASSO:
  957. vga_wseq(regbase, CL_SEQR7, 0x27);
  958. /* Fast Page-Mode writes */
  959. vga_wseq(regbase, CL_SEQRF, 0xb0);
  960. break;
  961. case BT_SD64:
  962. case BT_PICASSO4:
  963. case BT_ALPINE:
  964. /* Extended Sequencer Mode: 256c col. mode */
  965. vga_wseq(regbase, CL_SEQR7,
  966. cinfo->doubleVCLK ? 0xa3 : 0xa7);
  967. break;
  968. case BT_GD5480:
  969. vga_wseq(regbase, CL_SEQR7, 0x17);
  970. /* We already set SRF and SR1F */
  971. break;
  972. case BT_LAGUNA:
  973. case BT_LAGUNAB:
  974. vga_wseq(regbase, CL_SEQR7,
  975. vga_rseq(regbase, CL_SEQR7) & ~0x01);
  976. control |= 0x2000;
  977. format |= 0x1400;
  978. threshold |= 0x10;
  979. break;
  980. default:
  981. dev_warn(info->device, "unknown Board\n");
  982. break;
  983. }
  984. /* mode register: 256 color mode */
  985. vga_wgfx(regbase, VGA_GFX_MODE, 64);
  986. #ifdef CONFIG_PCI
  987. WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
  988. #elif defined(CONFIG_ZORRO)
  989. /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
  990. WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
  991. #endif
  992. }
  993. /******************************************************
  994. *
  995. * 24 bpp
  996. *
  997. */
  998. else if (var->bits_per_pixel == 24) {
  999. dev_dbg(info->device, "preparing for 24 bit deep display\n");
  1000. switch (cinfo->btype) {
  1001. case BT_PICCOLO:
  1002. case BT_SPECTRUM:
  1003. vga_wseq(regbase, CL_SEQR7, 0x85);
  1004. /* Fast Page-Mode writes */
  1005. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1006. break;
  1007. case BT_PICASSO:
  1008. vga_wseq(regbase, CL_SEQR7, 0x25);
  1009. /* Fast Page-Mode writes */
  1010. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1011. break;
  1012. case BT_SD64:
  1013. case BT_PICASSO4:
  1014. case BT_ALPINE:
  1015. /* Extended Sequencer Mode: 256c col. mode */
  1016. vga_wseq(regbase, CL_SEQR7, 0xa5);
  1017. break;
  1018. case BT_GD5480:
  1019. vga_wseq(regbase, CL_SEQR7, 0x15);
  1020. /* We already set SRF and SR1F */
  1021. break;
  1022. case BT_LAGUNA:
  1023. case BT_LAGUNAB:
  1024. vga_wseq(regbase, CL_SEQR7,
  1025. vga_rseq(regbase, CL_SEQR7) & ~0x01);
  1026. control |= 0x4000;
  1027. format |= 0x2400;
  1028. threshold |= 0x20;
  1029. break;
  1030. default:
  1031. dev_warn(info->device, "unknown Board\n");
  1032. break;
  1033. }
  1034. /* mode register: 256 color mode */
  1035. vga_wgfx(regbase, VGA_GFX_MODE, 64);
  1036. /* hidden dac reg: 8-8-8 mode (24 or 32) */
  1037. WHDR(cinfo, 0xc5);
  1038. }
  1039. /******************************************************
  1040. *
  1041. * unknown/unsupported bpp
  1042. *
  1043. */
  1044. else
  1045. dev_err(info->device,
  1046. "What's this? requested color depth == %d.\n",
  1047. var->bits_per_pixel);
  1048. pitch = info->fix.line_length >> 3;
  1049. vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
  1050. tmp = 0x22;
  1051. if (pitch & 0x100)
  1052. tmp |= 0x10; /* offset overflow bit */
  1053. /* screen start addr #16-18, fastpagemode cycles */
  1054. vga_wcrt(regbase, CL_CRT1B, tmp);
  1055. /* screen start address bit 19 */
  1056. if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
  1057. vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
  1058. if (is_laguna(cinfo)) {
  1059. tmp = 0;
  1060. if ((htotal + 5) & 256)
  1061. tmp |= 128;
  1062. if (hdispend & 256)
  1063. tmp |= 64;
  1064. if (hsyncstart & 256)
  1065. tmp |= 48;
  1066. if (vtotal & 1024)
  1067. tmp |= 8;
  1068. if (vdispend & 1024)
  1069. tmp |= 4;
  1070. if (vsyncstart & 1024)
  1071. tmp |= 3;
  1072. vga_wcrt(regbase, CL_CRT1E, tmp);
  1073. dev_dbg(info->device, "CRT1e: %d\n", tmp);
  1074. }
  1075. /* pixel panning */
  1076. vga_wattr(regbase, CL_AR33, 0);
  1077. /* [ EGS: SetOffset(); ] */
  1078. /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
  1079. AttrOn(cinfo);
  1080. if (is_laguna(cinfo)) {
  1081. /* no tiles */
  1082. fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
  1083. fb_writew(format, cinfo->laguna_mmio + 0xc0);
  1084. fb_writew(threshold, cinfo->laguna_mmio + 0xea);
  1085. }
  1086. /* finally, turn on everything - turn off "FullBandwidth" bit */
  1087. /* also, set "DotClock%2" bit where requested */
  1088. tmp = 0x01;
  1089. /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
  1090. if (var->vmode & FB_VMODE_CLOCK_HALVE)
  1091. tmp |= 0x08;
  1092. */
  1093. vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
  1094. dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
  1095. #ifdef CIRRUSFB_DEBUG
  1096. cirrusfb_dbg_reg_dump(info, NULL);
  1097. #endif
  1098. return 0;
  1099. }
  1100. /* for some reason incomprehensible to me, cirrusfb requires that you write
  1101. * the registers twice for the settings to take..grr. -dte */
  1102. static int cirrusfb_set_par(struct fb_info *info)
  1103. {
  1104. cirrusfb_set_par_foo(info);
  1105. return cirrusfb_set_par_foo(info);
  1106. }
  1107. static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
  1108. unsigned blue, unsigned transp,
  1109. struct fb_info *info)
  1110. {
  1111. struct cirrusfb_info *cinfo = info->par;
  1112. if (regno > 255)
  1113. return -EINVAL;
  1114. if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
  1115. u32 v;
  1116. red >>= (16 - info->var.red.length);
  1117. green >>= (16 - info->var.green.length);
  1118. blue >>= (16 - info->var.blue.length);
  1119. if (regno >= 16)
  1120. return 1;
  1121. v = (red << info->var.red.offset) |
  1122. (green << info->var.green.offset) |
  1123. (blue << info->var.blue.offset);
  1124. cinfo->pseudo_palette[regno] = v;
  1125. return 0;
  1126. }
  1127. if (info->var.bits_per_pixel == 8)
  1128. WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
  1129. return 0;
  1130. }
  1131. /*************************************************************************
  1132. cirrusfb_pan_display()
  1133. performs display panning - provided hardware permits this
  1134. **************************************************************************/
  1135. static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
  1136. struct fb_info *info)
  1137. {
  1138. int xoffset;
  1139. unsigned long base;
  1140. unsigned char tmp, xpix;
  1141. struct cirrusfb_info *cinfo = info->par;
  1142. /* no range checks for xoffset and yoffset, */
  1143. /* as fb_pan_display has already done this */
  1144. if (var->vmode & FB_VMODE_YWRAP)
  1145. return -EINVAL;
  1146. xoffset = var->xoffset * info->var.bits_per_pixel / 8;
  1147. base = var->yoffset * info->fix.line_length + xoffset;
  1148. if (info->var.bits_per_pixel == 1) {
  1149. /* base is already correct */
  1150. xpix = (unsigned char) (var->xoffset % 8);
  1151. } else {
  1152. base /= 4;
  1153. xpix = (unsigned char) ((xoffset % 4) * 2);
  1154. }
  1155. if (!is_laguna(cinfo))
  1156. cirrusfb_WaitBLT(cinfo->regbase);
  1157. /* lower 8 + 8 bits of screen start address */
  1158. vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
  1159. vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
  1160. /* 0xf2 is %11110010, exclude tmp bits */
  1161. tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
  1162. /* construct bits 16, 17 and 18 of screen start address */
  1163. if (base & 0x10000)
  1164. tmp |= 0x01;
  1165. if (base & 0x20000)
  1166. tmp |= 0x04;
  1167. if (base & 0x40000)
  1168. tmp |= 0x08;
  1169. vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
  1170. /* construct bit 19 of screen start address */
  1171. if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
  1172. tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
  1173. if (is_laguna(cinfo))
  1174. tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
  1175. else
  1176. tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
  1177. vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
  1178. }
  1179. /* write pixel panning value to AR33; this does not quite work in 8bpp
  1180. *
  1181. * ### Piccolo..? Will this work?
  1182. */
  1183. if (info->var.bits_per_pixel == 1)
  1184. vga_wattr(cinfo->regbase, CL_AR33, xpix);
  1185. return 0;
  1186. }
  1187. static int cirrusfb_blank(int blank_mode, struct fb_info *info)
  1188. {
  1189. /*
  1190. * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
  1191. * then the caller blanks by setting the CLUT (Color Look Up Table)
  1192. * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
  1193. * failed due to e.g. a video mode which doesn't support it.
  1194. * Implements VESA suspend and powerdown modes on hardware that
  1195. * supports disabling hsync/vsync:
  1196. * blank_mode == 2: suspend vsync
  1197. * blank_mode == 3: suspend hsync
  1198. * blank_mode == 4: powerdown
  1199. */
  1200. unsigned char val;
  1201. struct cirrusfb_info *cinfo = info->par;
  1202. int current_mode = cinfo->blank_mode;
  1203. dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
  1204. if (info->state != FBINFO_STATE_RUNNING ||
  1205. current_mode == blank_mode) {
  1206. dev_dbg(info->device, "EXIT, returning 0\n");
  1207. return 0;
  1208. }
  1209. /* Undo current */
  1210. if (current_mode == FB_BLANK_NORMAL ||
  1211. current_mode == FB_BLANK_UNBLANK)
  1212. /* clear "FullBandwidth" bit */
  1213. val = 0;
  1214. else
  1215. /* set "FullBandwidth" bit */
  1216. val = 0x20;
  1217. val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
  1218. vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
  1219. switch (blank_mode) {
  1220. case FB_BLANK_UNBLANK:
  1221. case FB_BLANK_NORMAL:
  1222. val = 0x00;
  1223. break;
  1224. case FB_BLANK_VSYNC_SUSPEND:
  1225. val = 0x04;
  1226. break;
  1227. case FB_BLANK_HSYNC_SUSPEND:
  1228. val = 0x02;
  1229. break;
  1230. case FB_BLANK_POWERDOWN:
  1231. val = 0x06;
  1232. break;
  1233. default:
  1234. dev_dbg(info->device, "EXIT, returning 1\n");
  1235. return 1;
  1236. }
  1237. vga_wgfx(cinfo->regbase, CL_GRE, val);
  1238. cinfo->blank_mode = blank_mode;
  1239. dev_dbg(info->device, "EXIT, returning 0\n");
  1240. /* Let fbcon do a soft blank for us */
  1241. return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
  1242. }
  1243. /**** END Hardware specific Routines **************************************/
  1244. /****************************************************************************/
  1245. /**** BEGIN Internal Routines ***********************************************/
  1246. static void init_vgachip(struct fb_info *info)
  1247. {
  1248. struct cirrusfb_info *cinfo = info->par;
  1249. const struct cirrusfb_board_info_rec *bi;
  1250. assert(cinfo != NULL);
  1251. bi = &cirrusfb_board_info[cinfo->btype];
  1252. /* reset board globally */
  1253. switch (cinfo->btype) {
  1254. case BT_PICCOLO:
  1255. WSFR(cinfo, 0x01);
  1256. udelay(500);
  1257. WSFR(cinfo, 0x51);
  1258. udelay(500);
  1259. break;
  1260. case BT_PICASSO:
  1261. WSFR2(cinfo, 0xff);
  1262. udelay(500);
  1263. break;
  1264. case BT_SD64:
  1265. case BT_SPECTRUM:
  1266. WSFR(cinfo, 0x1f);
  1267. udelay(500);
  1268. WSFR(cinfo, 0x4f);
  1269. udelay(500);
  1270. break;
  1271. case BT_PICASSO4:
  1272. /* disable flickerfixer */
  1273. vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
  1274. mdelay(100);
  1275. /* mode */
  1276. vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
  1277. fallthrough;
  1278. case BT_GD5480:
  1279. /* from Klaus' NetBSD driver: */
  1280. vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
  1281. fallthrough;
  1282. case BT_ALPINE:
  1283. /* put blitter into 542x compat */
  1284. vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
  1285. break;
  1286. case BT_LAGUNA:
  1287. case BT_LAGUNAB:
  1288. /* Nothing to do to reset the board. */
  1289. break;
  1290. default:
  1291. dev_err(info->device, "Warning: Unknown board type\n");
  1292. break;
  1293. }
  1294. /* make sure RAM size set by this point */
  1295. assert(info->screen_size > 0);
  1296. /* the P4 is not fully initialized here; I rely on it having been */
  1297. /* inited under AmigaOS already, which seems to work just fine */
  1298. /* (Klaus advised to do it this way) */
  1299. if (cinfo->btype != BT_PICASSO4) {
  1300. WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
  1301. WGen(cinfo, CL_POS102, 0x01);
  1302. WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
  1303. if (cinfo->btype != BT_SD64)
  1304. WGen(cinfo, CL_VSSM2, 0x01);
  1305. /* reset sequencer logic */
  1306. vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
  1307. /* FullBandwidth (video off) and 8/9 dot clock */
  1308. vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
  1309. /* "magic cookie" - doesn't make any sense to me.. */
  1310. /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
  1311. /* unlock all extension registers */
  1312. vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
  1313. switch (cinfo->btype) {
  1314. case BT_GD5480:
  1315. vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
  1316. break;
  1317. case BT_ALPINE:
  1318. case BT_LAGUNA:
  1319. case BT_LAGUNAB:
  1320. break;
  1321. case BT_SD64:
  1322. #ifdef CONFIG_ZORRO
  1323. vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
  1324. #endif
  1325. break;
  1326. default:
  1327. vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
  1328. vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
  1329. break;
  1330. }
  1331. }
  1332. /* plane mask: nothing */
  1333. vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
  1334. /* character map select: doesn't even matter in gx mode */
  1335. vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
  1336. /* memory mode: chain4, ext. memory */
  1337. vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
  1338. /* controller-internal base address of video memory */
  1339. if (bi->init_sr07)
  1340. vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
  1341. /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
  1342. /* EEPROM control: shouldn't be necessary to write to this at all.. */
  1343. /* graphics cursor X position (incomplete; position gives rem. 3 bits */
  1344. vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
  1345. /* graphics cursor Y position (..."... ) */
  1346. vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
  1347. /* graphics cursor attributes */
  1348. vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
  1349. /* graphics cursor pattern address */
  1350. vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
  1351. /* writing these on a P4 might give problems.. */
  1352. if (cinfo->btype != BT_PICASSO4) {
  1353. /* configuration readback and ext. color */
  1354. vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
  1355. /* signature generator */
  1356. vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
  1357. }
  1358. /* Screen A preset row scan: none */
  1359. vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
  1360. /* Text cursor start: disable text cursor */
  1361. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
  1362. /* Text cursor end: - */
  1363. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
  1364. /* text cursor location high: 0 */
  1365. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
  1366. /* text cursor location low: 0 */
  1367. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
  1368. /* Underline Row scanline: - */
  1369. vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
  1370. /* ### add 0x40 for text modes with > 30 MHz pixclock */
  1371. /* ext. display controls: ext.adr. wrap */
  1372. vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
  1373. /* Set/Reset registers: - */
  1374. vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
  1375. /* Set/Reset enable: - */
  1376. vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
  1377. /* Color Compare: - */
  1378. vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
  1379. /* Data Rotate: - */
  1380. vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
  1381. /* Read Map Select: - */
  1382. vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
  1383. /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
  1384. vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
  1385. /* Miscellaneous: memory map base address, graphics mode */
  1386. vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
  1387. /* Color Don't care: involve all planes */
  1388. vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
  1389. /* Bit Mask: no mask at all */
  1390. vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
  1391. if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
  1392. is_laguna(cinfo))
  1393. /* (5434 can't have bit 3 set for bitblt) */
  1394. vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
  1395. else
  1396. /* Graphics controller mode extensions: finer granularity,
  1397. * 8byte data latches
  1398. */
  1399. vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
  1400. vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
  1401. vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
  1402. vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
  1403. /* Background color byte 1: - */
  1404. /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
  1405. /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
  1406. /* Attribute Controller palette registers: "identity mapping" */
  1407. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
  1408. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
  1409. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
  1410. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
  1411. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
  1412. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
  1413. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
  1414. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
  1415. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
  1416. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
  1417. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
  1418. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
  1419. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
  1420. vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
  1421. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
  1422. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
  1423. /* Attribute Controller mode: graphics mode */
  1424. vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
  1425. /* Overscan color reg.: reg. 0 */
  1426. vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
  1427. /* Color Plane enable: Enable all 4 planes */
  1428. vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
  1429. /* Color Select: - */
  1430. vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
  1431. WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
  1432. /* BLT Start/status: Blitter reset */
  1433. vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
  1434. /* - " - : "end-of-reset" */
  1435. vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
  1436. /* misc... */
  1437. WHDR(cinfo, 0); /* Hidden DAC register: - */
  1438. return;
  1439. }
  1440. static void switch_monitor(struct cirrusfb_info *cinfo, int on)
  1441. {
  1442. #ifdef CONFIG_ZORRO /* only works on Zorro boards */
  1443. static int IsOn = 0; /* XXX not ok for multiple boards */
  1444. if (cinfo->btype == BT_PICASSO4)
  1445. return; /* nothing to switch */
  1446. if (cinfo->btype == BT_ALPINE)
  1447. return; /* nothing to switch */
  1448. if (cinfo->btype == BT_GD5480)
  1449. return; /* nothing to switch */
  1450. if (cinfo->btype == BT_PICASSO) {
  1451. if ((on && !IsOn) || (!on && IsOn))
  1452. WSFR(cinfo, 0xff);
  1453. return;
  1454. }
  1455. if (on) {
  1456. switch (cinfo->btype) {
  1457. case BT_SD64:
  1458. WSFR(cinfo, cinfo->SFR | 0x21);
  1459. break;
  1460. case BT_PICCOLO:
  1461. WSFR(cinfo, cinfo->SFR | 0x28);
  1462. break;
  1463. case BT_SPECTRUM:
  1464. WSFR(cinfo, 0x6f);
  1465. break;
  1466. default: /* do nothing */ break;
  1467. }
  1468. } else {
  1469. switch (cinfo->btype) {
  1470. case BT_SD64:
  1471. WSFR(cinfo, cinfo->SFR & 0xde);
  1472. break;
  1473. case BT_PICCOLO:
  1474. WSFR(cinfo, cinfo->SFR & 0xd7);
  1475. break;
  1476. case BT_SPECTRUM:
  1477. WSFR(cinfo, 0x4f);
  1478. break;
  1479. default: /* do nothing */
  1480. break;
  1481. }
  1482. }
  1483. #endif /* CONFIG_ZORRO */
  1484. }
  1485. /******************************************/
  1486. /* Linux 2.6-style accelerated functions */
  1487. /******************************************/
  1488. static int cirrusfb_sync(struct fb_info *info)
  1489. {
  1490. struct cirrusfb_info *cinfo = info->par;
  1491. if (!is_laguna(cinfo)) {
  1492. while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
  1493. cpu_relax();
  1494. }
  1495. return 0;
  1496. }
  1497. static void cirrusfb_fillrect(struct fb_info *info,
  1498. const struct fb_fillrect *region)
  1499. {
  1500. struct fb_fillrect modded;
  1501. int vxres, vyres;
  1502. struct cirrusfb_info *cinfo = info->par;
  1503. int m = info->var.bits_per_pixel;
  1504. u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
  1505. cinfo->pseudo_palette[region->color] : region->color;
  1506. if (info->state != FBINFO_STATE_RUNNING)
  1507. return;
  1508. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  1509. cfb_fillrect(info, region);
  1510. return;
  1511. }
  1512. vxres = info->var.xres_virtual;
  1513. vyres = info->var.yres_virtual;
  1514. memcpy(&modded, region, sizeof(struct fb_fillrect));
  1515. if (!modded.width || !modded.height ||
  1516. modded.dx >= vxres || modded.dy >= vyres)
  1517. return;
  1518. if (modded.dx + modded.width > vxres)
  1519. modded.width = vxres - modded.dx;
  1520. if (modded.dy + modded.height > vyres)
  1521. modded.height = vyres - modded.dy;
  1522. cirrusfb_RectFill(cinfo->regbase,
  1523. info->var.bits_per_pixel,
  1524. (region->dx * m) / 8, region->dy,
  1525. (region->width * m) / 8, region->height,
  1526. color, color,
  1527. info->fix.line_length, 0x40);
  1528. }
  1529. static void cirrusfb_copyarea(struct fb_info *info,
  1530. const struct fb_copyarea *area)
  1531. {
  1532. struct fb_copyarea modded;
  1533. u32 vxres, vyres;
  1534. struct cirrusfb_info *cinfo = info->par;
  1535. int m = info->var.bits_per_pixel;
  1536. if (info->state != FBINFO_STATE_RUNNING)
  1537. return;
  1538. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  1539. cfb_copyarea(info, area);
  1540. return;
  1541. }
  1542. vxres = info->var.xres_virtual;
  1543. vyres = info->var.yres_virtual;
  1544. memcpy(&modded, area, sizeof(struct fb_copyarea));
  1545. if (!modded.width || !modded.height ||
  1546. modded.sx >= vxres || modded.sy >= vyres ||
  1547. modded.dx >= vxres || modded.dy >= vyres)
  1548. return;
  1549. if (modded.sx + modded.width > vxres)
  1550. modded.width = vxres - modded.sx;
  1551. if (modded.dx + modded.width > vxres)
  1552. modded.width = vxres - modded.dx;
  1553. if (modded.sy + modded.height > vyres)
  1554. modded.height = vyres - modded.sy;
  1555. if (modded.dy + modded.height > vyres)
  1556. modded.height = vyres - modded.dy;
  1557. cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
  1558. (area->sx * m) / 8, area->sy,
  1559. (area->dx * m) / 8, area->dy,
  1560. (area->width * m) / 8, area->height,
  1561. info->fix.line_length);
  1562. }
  1563. static void cirrusfb_imageblit(struct fb_info *info,
  1564. const struct fb_image *image)
  1565. {
  1566. struct cirrusfb_info *cinfo = info->par;
  1567. unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
  1568. if (info->state != FBINFO_STATE_RUNNING)
  1569. return;
  1570. /* Alpine/SD64 does not work at 24bpp ??? */
  1571. if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
  1572. cfb_imageblit(info, image);
  1573. else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
  1574. op == 0xc)
  1575. cfb_imageblit(info, image);
  1576. else {
  1577. unsigned size = ((image->width + 7) >> 3) * image->height;
  1578. int m = info->var.bits_per_pixel;
  1579. u32 fg, bg;
  1580. if (info->var.bits_per_pixel == 8) {
  1581. fg = image->fg_color;
  1582. bg = image->bg_color;
  1583. } else {
  1584. fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
  1585. bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
  1586. }
  1587. if (info->var.bits_per_pixel == 24) {
  1588. /* clear background first */
  1589. cirrusfb_RectFill(cinfo->regbase,
  1590. info->var.bits_per_pixel,
  1591. (image->dx * m) / 8, image->dy,
  1592. (image->width * m) / 8,
  1593. image->height,
  1594. bg, bg,
  1595. info->fix.line_length, 0x40);
  1596. }
  1597. cirrusfb_RectFill(cinfo->regbase,
  1598. info->var.bits_per_pixel,
  1599. (image->dx * m) / 8, image->dy,
  1600. (image->width * m) / 8, image->height,
  1601. fg, bg,
  1602. info->fix.line_length, op);
  1603. memcpy(info->screen_base, image->data, size);
  1604. }
  1605. }
  1606. #ifdef CONFIG_PCI
  1607. static int release_io_ports;
  1608. /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
  1609. * based on the DRAM bandwidth bit and DRAM bank switching bit. This
  1610. * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
  1611. * seem to have. */
  1612. static unsigned int cirrusfb_get_memsize(struct fb_info *info,
  1613. u8 __iomem *regbase)
  1614. {
  1615. unsigned long mem;
  1616. struct cirrusfb_info *cinfo = info->par;
  1617. if (is_laguna(cinfo)) {
  1618. unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
  1619. mem = ((SR14 & 7) + 1) << 20;
  1620. } else {
  1621. unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
  1622. switch ((SRF & 0x18)) {
  1623. case 0x08:
  1624. mem = 512 * 1024;
  1625. break;
  1626. case 0x10:
  1627. mem = 1024 * 1024;
  1628. break;
  1629. /* 64-bit DRAM data bus width; assume 2MB.
  1630. * Also indicates 2MB memory on the 5430.
  1631. */
  1632. case 0x18:
  1633. mem = 2048 * 1024;
  1634. break;
  1635. default:
  1636. dev_warn(info->device, "Unknown memory size!\n");
  1637. mem = 1024 * 1024;
  1638. }
  1639. /* If DRAM bank switching is enabled, there must be
  1640. * twice as much memory installed. (4MB on the 5434)
  1641. */
  1642. if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
  1643. mem *= 2;
  1644. }
  1645. /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
  1646. return mem;
  1647. }
  1648. static void get_pci_addrs(const struct pci_dev *pdev,
  1649. unsigned long *display, unsigned long *registers)
  1650. {
  1651. assert(pdev != NULL);
  1652. assert(display != NULL);
  1653. assert(registers != NULL);
  1654. *display = 0;
  1655. *registers = 0;
  1656. /* This is a best-guess for now */
  1657. if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
  1658. *display = pci_resource_start(pdev, 1);
  1659. *registers = pci_resource_start(pdev, 0);
  1660. } else {
  1661. *display = pci_resource_start(pdev, 0);
  1662. *registers = pci_resource_start(pdev, 1);
  1663. }
  1664. assert(*display != 0);
  1665. }
  1666. static void cirrusfb_pci_unmap(struct fb_info *info)
  1667. {
  1668. struct pci_dev *pdev = to_pci_dev(info->device);
  1669. struct cirrusfb_info *cinfo = info->par;
  1670. if (cinfo->laguna_mmio == NULL)
  1671. iounmap(cinfo->laguna_mmio);
  1672. iounmap(info->screen_base);
  1673. #if 0 /* if system didn't claim this region, we would... */
  1674. release_mem_region(0xA0000, 65535);
  1675. #endif
  1676. if (release_io_ports)
  1677. release_region(0x3C0, 32);
  1678. pci_release_regions(pdev);
  1679. }
  1680. #endif /* CONFIG_PCI */
  1681. #ifdef CONFIG_ZORRO
  1682. static void cirrusfb_zorro_unmap(struct fb_info *info)
  1683. {
  1684. struct cirrusfb_info *cinfo = info->par;
  1685. struct zorro_dev *zdev = to_zorro_dev(info->device);
  1686. if (info->fix.smem_start > 16 * MB_)
  1687. iounmap(info->screen_base);
  1688. if (info->fix.mmio_start > 16 * MB_)
  1689. iounmap(cinfo->regbase);
  1690. zorro_release_device(zdev);
  1691. }
  1692. #endif /* CONFIG_ZORRO */
  1693. /* function table of the above functions */
  1694. static const struct fb_ops cirrusfb_ops = {
  1695. .owner = THIS_MODULE,
  1696. .fb_open = cirrusfb_open,
  1697. .fb_release = cirrusfb_release,
  1698. .fb_setcolreg = cirrusfb_setcolreg,
  1699. .fb_check_var = cirrusfb_check_var,
  1700. .fb_set_par = cirrusfb_set_par,
  1701. .fb_pan_display = cirrusfb_pan_display,
  1702. .fb_blank = cirrusfb_blank,
  1703. .fb_fillrect = cirrusfb_fillrect,
  1704. .fb_copyarea = cirrusfb_copyarea,
  1705. .fb_sync = cirrusfb_sync,
  1706. .fb_imageblit = cirrusfb_imageblit,
  1707. };
  1708. static int cirrusfb_set_fbinfo(struct fb_info *info)
  1709. {
  1710. struct cirrusfb_info *cinfo = info->par;
  1711. struct fb_var_screeninfo *var = &info->var;
  1712. info->pseudo_palette = cinfo->pseudo_palette;
  1713. info->flags = FBINFO_DEFAULT
  1714. | FBINFO_HWACCEL_XPAN
  1715. | FBINFO_HWACCEL_YPAN
  1716. | FBINFO_HWACCEL_FILLRECT
  1717. | FBINFO_HWACCEL_IMAGEBLIT
  1718. | FBINFO_HWACCEL_COPYAREA;
  1719. if (noaccel || is_laguna(cinfo)) {
  1720. info->flags |= FBINFO_HWACCEL_DISABLED;
  1721. info->fix.accel = FB_ACCEL_NONE;
  1722. } else
  1723. info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
  1724. info->fbops = &cirrusfb_ops;
  1725. if (cinfo->btype == BT_GD5480) {
  1726. if (var->bits_per_pixel == 16)
  1727. info->screen_base += 1 * MB_;
  1728. if (var->bits_per_pixel == 32)
  1729. info->screen_base += 2 * MB_;
  1730. }
  1731. /* Fill fix common fields */
  1732. strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
  1733. sizeof(info->fix.id));
  1734. /* monochrome: only 1 memory plane */
  1735. /* 8 bit and above: Use whole memory area */
  1736. info->fix.smem_len = info->screen_size;
  1737. if (var->bits_per_pixel == 1)
  1738. info->fix.smem_len /= 4;
  1739. info->fix.type_aux = 0;
  1740. info->fix.xpanstep = 1;
  1741. info->fix.ypanstep = 1;
  1742. info->fix.ywrapstep = 0;
  1743. /* FIXME: map region at 0xB8000 if available, fill in here */
  1744. info->fix.mmio_len = 0;
  1745. fb_alloc_cmap(&info->cmap, 256, 0);
  1746. return 0;
  1747. }
  1748. static int cirrusfb_register(struct fb_info *info)
  1749. {
  1750. struct cirrusfb_info *cinfo = info->par;
  1751. int err;
  1752. /* sanity checks */
  1753. assert(cinfo->btype != BT_NONE);
  1754. /* set all the vital stuff */
  1755. cirrusfb_set_fbinfo(info);
  1756. dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
  1757. err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
  1758. if (!err) {
  1759. dev_dbg(info->device, "wrong initial video mode\n");
  1760. err = -EINVAL;
  1761. goto err_dealloc_cmap;
  1762. }
  1763. info->var.activate = FB_ACTIVATE_NOW;
  1764. err = cirrusfb_check_var(&info->var, info);
  1765. if (err < 0) {
  1766. /* should never happen */
  1767. dev_dbg(info->device,
  1768. "choking on default var... umm, no good.\n");
  1769. goto err_dealloc_cmap;
  1770. }
  1771. err = register_framebuffer(info);
  1772. if (err < 0) {
  1773. dev_err(info->device,
  1774. "could not register fb device; err = %d!\n", err);
  1775. goto err_dealloc_cmap;
  1776. }
  1777. return 0;
  1778. err_dealloc_cmap:
  1779. fb_dealloc_cmap(&info->cmap);
  1780. return err;
  1781. }
  1782. static void cirrusfb_cleanup(struct fb_info *info)
  1783. {
  1784. struct cirrusfb_info *cinfo = info->par;
  1785. switch_monitor(cinfo, 0);
  1786. unregister_framebuffer(info);
  1787. fb_dealloc_cmap(&info->cmap);
  1788. dev_dbg(info->device, "Framebuffer unregistered\n");
  1789. cinfo->unmap(info);
  1790. framebuffer_release(info);
  1791. }
  1792. #ifdef CONFIG_PCI
  1793. static int cirrusfb_pci_register(struct pci_dev *pdev,
  1794. const struct pci_device_id *ent)
  1795. {
  1796. struct cirrusfb_info *cinfo;
  1797. struct fb_info *info;
  1798. unsigned long board_addr, board_size;
  1799. int ret;
  1800. ret = pci_enable_device(pdev);
  1801. if (ret < 0) {
  1802. printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
  1803. goto err_out;
  1804. }
  1805. info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
  1806. if (!info) {
  1807. ret = -ENOMEM;
  1808. goto err_out;
  1809. }
  1810. cinfo = info->par;
  1811. cinfo->btype = (enum cirrus_board) ent->driver_data;
  1812. dev_dbg(info->device,
  1813. " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
  1814. (unsigned long long)pdev->resource[0].start, cinfo->btype);
  1815. dev_dbg(info->device, " base address 1 is 0x%Lx\n",
  1816. (unsigned long long)pdev->resource[1].start);
  1817. dev_dbg(info->device,
  1818. "Attempt to get PCI info for Cirrus Graphics Card\n");
  1819. get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
  1820. /* FIXME: this forces VGA. alternatives? */
  1821. cinfo->regbase = NULL;
  1822. cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
  1823. dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
  1824. board_addr, info->fix.mmio_start);
  1825. board_size = (cinfo->btype == BT_GD5480) ?
  1826. 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
  1827. ret = pci_request_regions(pdev, "cirrusfb");
  1828. if (ret < 0) {
  1829. dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
  1830. board_addr);
  1831. goto err_release_fb;
  1832. }
  1833. #if 0 /* if the system didn't claim this region, we would... */
  1834. if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
  1835. dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
  1836. 0xA0000L);
  1837. ret = -EBUSY;
  1838. goto err_release_regions;
  1839. }
  1840. #endif
  1841. if (request_region(0x3C0, 32, "cirrusfb"))
  1842. release_io_ports = 1;
  1843. info->screen_base = ioremap(board_addr, board_size);
  1844. if (!info->screen_base) {
  1845. ret = -EIO;
  1846. goto err_release_legacy;
  1847. }
  1848. info->fix.smem_start = board_addr;
  1849. info->screen_size = board_size;
  1850. cinfo->unmap = cirrusfb_pci_unmap;
  1851. dev_info(info->device,
  1852. "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
  1853. info->screen_size >> 10, board_addr);
  1854. pci_set_drvdata(pdev, info);
  1855. ret = cirrusfb_register(info);
  1856. if (!ret)
  1857. return 0;
  1858. iounmap(info->screen_base);
  1859. err_release_legacy:
  1860. if (release_io_ports)
  1861. release_region(0x3C0, 32);
  1862. #if 0
  1863. release_mem_region(0xA0000, 65535);
  1864. err_release_regions:
  1865. #endif
  1866. pci_release_regions(pdev);
  1867. err_release_fb:
  1868. if (cinfo->laguna_mmio != NULL)
  1869. iounmap(cinfo->laguna_mmio);
  1870. framebuffer_release(info);
  1871. err_out:
  1872. return ret;
  1873. }
  1874. static void cirrusfb_pci_unregister(struct pci_dev *pdev)
  1875. {
  1876. struct fb_info *info = pci_get_drvdata(pdev);
  1877. cirrusfb_cleanup(info);
  1878. }
  1879. static struct pci_driver cirrusfb_pci_driver = {
  1880. .name = "cirrusfb",
  1881. .id_table = cirrusfb_pci_table,
  1882. .probe = cirrusfb_pci_register,
  1883. .remove = cirrusfb_pci_unregister,
  1884. #ifdef CONFIG_PM
  1885. #if 0
  1886. .suspend = cirrusfb_pci_suspend,
  1887. .resume = cirrusfb_pci_resume,
  1888. #endif
  1889. #endif
  1890. };
  1891. #endif /* CONFIG_PCI */
  1892. #ifdef CONFIG_ZORRO
  1893. static int cirrusfb_zorro_register(struct zorro_dev *z,
  1894. const struct zorro_device_id *ent)
  1895. {
  1896. struct fb_info *info;
  1897. int error;
  1898. const struct zorrocl *zcl;
  1899. enum cirrus_board btype;
  1900. unsigned long regbase, ramsize, rambase;
  1901. struct cirrusfb_info *cinfo;
  1902. info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
  1903. if (!info)
  1904. return -ENOMEM;
  1905. zcl = (const struct zorrocl *)ent->driver_data;
  1906. btype = zcl->type;
  1907. regbase = zorro_resource_start(z) + zcl->regoffset;
  1908. ramsize = zcl->ramsize;
  1909. if (ramsize) {
  1910. rambase = zorro_resource_start(z) + zcl->ramoffset;
  1911. if (zorro_resource_len(z) == 64 * MB_) {
  1912. /* Quirk for 64 MiB Picasso IV */
  1913. rambase += zcl->ramoffset;
  1914. }
  1915. } else {
  1916. struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL);
  1917. if (!ram || !zorro_resource_len(ram)) {
  1918. dev_err(info->device, "No video RAM found\n");
  1919. error = -ENODEV;
  1920. goto err_release_fb;
  1921. }
  1922. rambase = zorro_resource_start(ram);
  1923. ramsize = zorro_resource_len(ram);
  1924. if (zcl->ramid2 &&
  1925. (ram = zorro_find_device(zcl->ramid2, NULL))) {
  1926. if (zorro_resource_start(ram) != rambase + ramsize) {
  1927. dev_warn(info->device,
  1928. "Skipping non-contiguous RAM at %pR\n",
  1929. &ram->resource);
  1930. } else {
  1931. ramsize += zorro_resource_len(ram);
  1932. }
  1933. }
  1934. }
  1935. dev_info(info->device,
  1936. "%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n",
  1937. cirrusfb_board_info[btype].name, regbase, ramsize / MB_,
  1938. rambase);
  1939. if (!zorro_request_device(z, "cirrusfb")) {
  1940. dev_err(info->device, "Cannot reserve %pR\n", &z->resource);
  1941. error = -EBUSY;
  1942. goto err_release_fb;
  1943. }
  1944. cinfo = info->par;
  1945. cinfo->btype = btype;
  1946. info->fix.mmio_start = regbase;
  1947. cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
  1948. : ZTWO_VADDR(regbase);
  1949. if (!cinfo->regbase) {
  1950. dev_err(info->device, "Cannot map registers\n");
  1951. error = -EIO;
  1952. goto err_release_dev;
  1953. }
  1954. info->fix.smem_start = rambase;
  1955. info->screen_size = ramsize;
  1956. info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize)
  1957. : ZTWO_VADDR(rambase);
  1958. if (!info->screen_base) {
  1959. dev_err(info->device, "Cannot map video RAM\n");
  1960. error = -EIO;
  1961. goto err_unmap_reg;
  1962. }
  1963. cinfo->unmap = cirrusfb_zorro_unmap;
  1964. dev_info(info->device,
  1965. "Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n",
  1966. ramsize / MB_, rambase);
  1967. /* MCLK select etc. */
  1968. if (cirrusfb_board_info[btype].init_sr1f)
  1969. vga_wseq(cinfo->regbase, CL_SEQR1F,
  1970. cirrusfb_board_info[btype].sr1f);
  1971. error = cirrusfb_register(info);
  1972. if (error) {
  1973. dev_err(info->device, "Failed to register device, error %d\n",
  1974. error);
  1975. goto err_unmap_ram;
  1976. }
  1977. zorro_set_drvdata(z, info);
  1978. return 0;
  1979. err_unmap_ram:
  1980. if (rambase > 16 * MB_)
  1981. iounmap(info->screen_base);
  1982. err_unmap_reg:
  1983. if (regbase > 16 * MB_)
  1984. iounmap(cinfo->regbase);
  1985. err_release_dev:
  1986. zorro_release_device(z);
  1987. err_release_fb:
  1988. framebuffer_release(info);
  1989. return error;
  1990. }
  1991. void cirrusfb_zorro_unregister(struct zorro_dev *z)
  1992. {
  1993. struct fb_info *info = zorro_get_drvdata(z);
  1994. cirrusfb_cleanup(info);
  1995. zorro_set_drvdata(z, NULL);
  1996. }
  1997. static struct zorro_driver cirrusfb_zorro_driver = {
  1998. .name = "cirrusfb",
  1999. .id_table = cirrusfb_zorro_table,
  2000. .probe = cirrusfb_zorro_register,
  2001. .remove = cirrusfb_zorro_unregister,
  2002. };
  2003. #endif /* CONFIG_ZORRO */
  2004. #ifndef MODULE
  2005. static int __init cirrusfb_setup(char *options)
  2006. {
  2007. char *this_opt;
  2008. if (!options || !*options)
  2009. return 0;
  2010. while ((this_opt = strsep(&options, ",")) != NULL) {
  2011. if (!*this_opt)
  2012. continue;
  2013. if (!strcmp(this_opt, "noaccel"))
  2014. noaccel = 1;
  2015. else if (!strncmp(this_opt, "mode:", 5))
  2016. mode_option = this_opt + 5;
  2017. else
  2018. mode_option = this_opt;
  2019. }
  2020. return 0;
  2021. }
  2022. #endif
  2023. /*
  2024. * Modularization
  2025. */
  2026. MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
  2027. MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
  2028. MODULE_LICENSE("GPL");
  2029. static int __init cirrusfb_init(void)
  2030. {
  2031. int error = 0;
  2032. #ifndef MODULE
  2033. char *option = NULL;
  2034. if (fb_get_options("cirrusfb", &option))
  2035. return -ENODEV;
  2036. cirrusfb_setup(option);
  2037. #endif
  2038. #ifdef CONFIG_ZORRO
  2039. error |= zorro_register_driver(&cirrusfb_zorro_driver);
  2040. #endif
  2041. #ifdef CONFIG_PCI
  2042. error |= pci_register_driver(&cirrusfb_pci_driver);
  2043. #endif
  2044. return error;
  2045. }
  2046. static void __exit cirrusfb_exit(void)
  2047. {
  2048. #ifdef CONFIG_PCI
  2049. pci_unregister_driver(&cirrusfb_pci_driver);
  2050. #endif
  2051. #ifdef CONFIG_ZORRO
  2052. zorro_unregister_driver(&cirrusfb_zorro_driver);
  2053. #endif
  2054. }
  2055. module_init(cirrusfb_init);
  2056. module_param(mode_option, charp, 0);
  2057. MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
  2058. module_param(noaccel, bool, 0);
  2059. MODULE_PARM_DESC(noaccel, "Disable acceleration");
  2060. #ifdef MODULE
  2061. module_exit(cirrusfb_exit);
  2062. #endif
  2063. /**********************************************************************/
  2064. /* about the following functions - I have used the same names for the */
  2065. /* functions as Markus Wild did in his Retina driver for NetBSD as */
  2066. /* they just made sense for this purpose. Apart from that, I wrote */
  2067. /* these functions myself. */
  2068. /**********************************************************************/
  2069. /*** WGen() - write into one of the external/general registers ***/
  2070. static void WGen(const struct cirrusfb_info *cinfo,
  2071. int regnum, unsigned char val)
  2072. {
  2073. unsigned long regofs = 0;
  2074. if (cinfo->btype == BT_PICASSO) {
  2075. /* Picasso II specific hack */
  2076. /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
  2077. regnum == CL_VSSM2) */
  2078. if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
  2079. regofs = 0xfff;
  2080. }
  2081. vga_w(cinfo->regbase, regofs + regnum, val);
  2082. }
  2083. /*** RGen() - read out one of the external/general registers ***/
  2084. static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
  2085. {
  2086. unsigned long regofs = 0;
  2087. if (cinfo->btype == BT_PICASSO) {
  2088. /* Picasso II specific hack */
  2089. /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
  2090. regnum == CL_VSSM2) */
  2091. if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
  2092. regofs = 0xfff;
  2093. }
  2094. return vga_r(cinfo->regbase, regofs + regnum);
  2095. }
  2096. /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
  2097. static void AttrOn(const struct cirrusfb_info *cinfo)
  2098. {
  2099. assert(cinfo != NULL);
  2100. if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
  2101. /* if we're just in "write value" mode, write back the */
  2102. /* same value as before to not modify anything */
  2103. vga_w(cinfo->regbase, VGA_ATT_IW,
  2104. vga_r(cinfo->regbase, VGA_ATT_R));
  2105. }
  2106. /* turn on video bit */
  2107. /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
  2108. vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
  2109. /* dummy write on Reg0 to be on "write index" mode next time */
  2110. vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
  2111. }
  2112. /*** WHDR() - write into the Hidden DAC register ***/
  2113. /* as the HDR is the only extension register that requires special treatment
  2114. * (the other extension registers are accessible just like the "ordinary"
  2115. * registers of their functional group) here is a specialized routine for
  2116. * accessing the HDR
  2117. */
  2118. static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
  2119. {
  2120. unsigned char dummy;
  2121. if (is_laguna(cinfo))
  2122. return;
  2123. if (cinfo->btype == BT_PICASSO) {
  2124. /* Klaus' hint for correct access to HDR on some boards */
  2125. /* first write 0 to pixel mask (3c6) */
  2126. WGen(cinfo, VGA_PEL_MSK, 0x00);
  2127. udelay(200);
  2128. /* next read dummy from pixel address (3c8) */
  2129. dummy = RGen(cinfo, VGA_PEL_IW);
  2130. udelay(200);
  2131. }
  2132. /* now do the usual stuff to access the HDR */
  2133. dummy = RGen(cinfo, VGA_PEL_MSK);
  2134. udelay(200);
  2135. dummy = RGen(cinfo, VGA_PEL_MSK);
  2136. udelay(200);
  2137. dummy = RGen(cinfo, VGA_PEL_MSK);
  2138. udelay(200);
  2139. dummy = RGen(cinfo, VGA_PEL_MSK);
  2140. udelay(200);
  2141. WGen(cinfo, VGA_PEL_MSK, val);
  2142. udelay(200);
  2143. if (cinfo->btype == BT_PICASSO) {
  2144. /* now first reset HDR access counter */
  2145. dummy = RGen(cinfo, VGA_PEL_IW);
  2146. udelay(200);
  2147. /* and at the end, restore the mask value */
  2148. /* ## is this mask always 0xff? */
  2149. WGen(cinfo, VGA_PEL_MSK, 0xff);
  2150. udelay(200);
  2151. }
  2152. }
  2153. /*** WSFR() - write to the "special function register" (SFR) ***/
  2154. static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
  2155. {
  2156. #ifdef CONFIG_ZORRO
  2157. assert(cinfo->regbase != NULL);
  2158. cinfo->SFR = val;
  2159. z_writeb(val, cinfo->regbase + 0x8000);
  2160. #endif
  2161. }
  2162. /* The Picasso has a second register for switching the monitor bit */
  2163. static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
  2164. {
  2165. #ifdef CONFIG_ZORRO
  2166. /* writing an arbitrary value to this one causes the monitor switcher */
  2167. /* to flip to Amiga display */
  2168. assert(cinfo->regbase != NULL);
  2169. cinfo->SFR = val;
  2170. z_writeb(val, cinfo->regbase + 0x9000);
  2171. #endif
  2172. }
  2173. /*** WClut - set CLUT entry (range: 0..63) ***/
  2174. static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
  2175. unsigned char green, unsigned char blue)
  2176. {
  2177. unsigned int data = VGA_PEL_D;
  2178. /* address write mode register is not translated.. */
  2179. vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
  2180. if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
  2181. cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
  2182. cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
  2183. /* but DAC data register IS, at least for Picasso II */
  2184. if (cinfo->btype == BT_PICASSO)
  2185. data += 0xfff;
  2186. vga_w(cinfo->regbase, data, red);
  2187. vga_w(cinfo->regbase, data, green);
  2188. vga_w(cinfo->regbase, data, blue);
  2189. } else {
  2190. vga_w(cinfo->regbase, data, blue);
  2191. vga_w(cinfo->regbase, data, green);
  2192. vga_w(cinfo->regbase, data, red);
  2193. }
  2194. }
  2195. #if 0
  2196. /*** RClut - read CLUT entry (range 0..63) ***/
  2197. static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
  2198. unsigned char *green, unsigned char *blue)
  2199. {
  2200. unsigned int data = VGA_PEL_D;
  2201. vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
  2202. if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
  2203. cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
  2204. if (cinfo->btype == BT_PICASSO)
  2205. data += 0xfff;
  2206. *red = vga_r(cinfo->regbase, data);
  2207. *green = vga_r(cinfo->regbase, data);
  2208. *blue = vga_r(cinfo->regbase, data);
  2209. } else {
  2210. *blue = vga_r(cinfo->regbase, data);
  2211. *green = vga_r(cinfo->regbase, data);
  2212. *red = vga_r(cinfo->regbase, data);
  2213. }
  2214. }
  2215. #endif
  2216. /*******************************************************************
  2217. cirrusfb_WaitBLT()
  2218. Wait for the BitBLT engine to complete a possible earlier job
  2219. *********************************************************************/
  2220. /* FIXME: use interrupts instead */
  2221. static void cirrusfb_WaitBLT(u8 __iomem *regbase)
  2222. {
  2223. while (vga_rgfx(regbase, CL_GR31) & 0x08)
  2224. cpu_relax();
  2225. }
  2226. /*******************************************************************
  2227. cirrusfb_BitBLT()
  2228. perform accelerated "scrolling"
  2229. ********************************************************************/
  2230. static void cirrusfb_set_blitter(u8 __iomem *regbase,
  2231. u_short nwidth, u_short nheight,
  2232. u_long nsrc, u_long ndest,
  2233. u_short bltmode, u_short line_length)
  2234. {
  2235. /* pitch: set to line_length */
  2236. /* dest pitch low */
  2237. vga_wgfx(regbase, CL_GR24, line_length & 0xff);
  2238. /* dest pitch hi */
  2239. vga_wgfx(regbase, CL_GR25, line_length >> 8);
  2240. /* source pitch low */
  2241. vga_wgfx(regbase, CL_GR26, line_length & 0xff);
  2242. /* source pitch hi */
  2243. vga_wgfx(regbase, CL_GR27, line_length >> 8);
  2244. /* BLT width: actual number of pixels - 1 */
  2245. /* BLT width low */
  2246. vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
  2247. /* BLT width hi */
  2248. vga_wgfx(regbase, CL_GR21, nwidth >> 8);
  2249. /* BLT height: actual number of lines -1 */
  2250. /* BLT height low */
  2251. vga_wgfx(regbase, CL_GR22, nheight & 0xff);
  2252. /* BLT width hi */
  2253. vga_wgfx(regbase, CL_GR23, nheight >> 8);
  2254. /* BLT destination */
  2255. /* BLT dest low */
  2256. vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
  2257. /* BLT dest mid */
  2258. vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
  2259. /* BLT dest hi */
  2260. vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
  2261. /* BLT source */
  2262. /* BLT src low */
  2263. vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
  2264. /* BLT src mid */
  2265. vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
  2266. /* BLT src hi */
  2267. vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
  2268. /* BLT mode */
  2269. vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
  2270. /* BLT ROP: SrcCopy */
  2271. vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
  2272. /* and finally: GO! */
  2273. vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
  2274. }
  2275. /*******************************************************************
  2276. cirrusfb_BitBLT()
  2277. perform accelerated "scrolling"
  2278. ********************************************************************/
  2279. static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
  2280. u_short curx, u_short cury,
  2281. u_short destx, u_short desty,
  2282. u_short width, u_short height,
  2283. u_short line_length)
  2284. {
  2285. u_short nwidth = width - 1;
  2286. u_short nheight = height - 1;
  2287. u_long nsrc, ndest;
  2288. u_char bltmode;
  2289. bltmode = 0x00;
  2290. /* if source adr < dest addr, do the Blt backwards */
  2291. if (cury <= desty) {
  2292. if (cury == desty) {
  2293. /* if src and dest are on the same line, check x */
  2294. if (curx < destx)
  2295. bltmode |= 0x01;
  2296. } else
  2297. bltmode |= 0x01;
  2298. }
  2299. /* standard case: forward blitting */
  2300. nsrc = (cury * line_length) + curx;
  2301. ndest = (desty * line_length) + destx;
  2302. if (bltmode) {
  2303. /* this means start addresses are at the end,
  2304. * counting backwards
  2305. */
  2306. nsrc += nheight * line_length + nwidth;
  2307. ndest += nheight * line_length + nwidth;
  2308. }
  2309. cirrusfb_WaitBLT(regbase);
  2310. cirrusfb_set_blitter(regbase, nwidth, nheight,
  2311. nsrc, ndest, bltmode, line_length);
  2312. }
  2313. /*******************************************************************
  2314. cirrusfb_RectFill()
  2315. perform accelerated rectangle fill
  2316. ********************************************************************/
  2317. static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
  2318. u_short x, u_short y, u_short width, u_short height,
  2319. u32 fg_color, u32 bg_color, u_short line_length,
  2320. u_char blitmode)
  2321. {
  2322. u_long ndest = (y * line_length) + x;
  2323. u_char op;
  2324. cirrusfb_WaitBLT(regbase);
  2325. /* This is a ColorExpand Blt, using the */
  2326. /* same color for foreground and background */
  2327. vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
  2328. vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
  2329. op = 0x80;
  2330. if (bits_per_pixel >= 16) {
  2331. vga_wgfx(regbase, CL_GR10, bg_color >> 8);
  2332. vga_wgfx(regbase, CL_GR11, fg_color >> 8);
  2333. op = 0x90;
  2334. }
  2335. if (bits_per_pixel >= 24) {
  2336. vga_wgfx(regbase, CL_GR12, bg_color >> 16);
  2337. vga_wgfx(regbase, CL_GR13, fg_color >> 16);
  2338. op = 0xa0;
  2339. }
  2340. if (bits_per_pixel == 32) {
  2341. vga_wgfx(regbase, CL_GR14, bg_color >> 24);
  2342. vga_wgfx(regbase, CL_GR15, fg_color >> 24);
  2343. op = 0xb0;
  2344. }
  2345. cirrusfb_set_blitter(regbase, width - 1, height - 1,
  2346. 0, ndest, op | blitmode, line_length);
  2347. }
  2348. /**************************************************************************
  2349. * bestclock() - determine closest possible clock lower(?) than the
  2350. * desired pixel clock
  2351. **************************************************************************/
  2352. static void bestclock(long freq, int *nom, int *den, int *div)
  2353. {
  2354. int n, d;
  2355. long h, diff;
  2356. assert(nom != NULL);
  2357. assert(den != NULL);
  2358. assert(div != NULL);
  2359. *nom = 0;
  2360. *den = 0;
  2361. *div = 0;
  2362. if (freq < 8000)
  2363. freq = 8000;
  2364. diff = freq;
  2365. for (n = 32; n < 128; n++) {
  2366. int s = 0;
  2367. d = (14318 * n) / freq;
  2368. if ((d >= 7) && (d <= 63)) {
  2369. int temp = d;
  2370. if (temp > 31) {
  2371. s = 1;
  2372. temp >>= 1;
  2373. }
  2374. h = ((14318 * n) / temp) >> s;
  2375. h = h > freq ? h - freq : freq - h;
  2376. if (h < diff) {
  2377. diff = h;
  2378. *nom = n;
  2379. *den = temp;
  2380. *div = s;
  2381. }
  2382. }
  2383. d++;
  2384. if ((d >= 7) && (d <= 63)) {
  2385. if (d > 31) {
  2386. s = 1;
  2387. d >>= 1;
  2388. }
  2389. h = ((14318 * n) / d) >> s;
  2390. h = h > freq ? h - freq : freq - h;
  2391. if (h < diff) {
  2392. diff = h;
  2393. *nom = n;
  2394. *den = d;
  2395. *div = s;
  2396. }
  2397. }
  2398. }
  2399. }
  2400. /* -------------------------------------------------------------------------
  2401. *
  2402. * debugging functions
  2403. *
  2404. * -------------------------------------------------------------------------
  2405. */
  2406. #ifdef CIRRUSFB_DEBUG
  2407. /**
  2408. * cirrusfb_dbg_print_regs
  2409. * @base: If using newmmio, the newmmio base address, otherwise %NULL
  2410. * @reg_class: type of registers to read: %CRT, or %SEQ
  2411. *
  2412. * DESCRIPTION:
  2413. * Dumps the given list of VGA CRTC registers. If @base is %NULL,
  2414. * old-style I/O ports are queried for information, otherwise MMIO is
  2415. * used at the given @base address to query the information.
  2416. */
  2417. static void cirrusfb_dbg_print_regs(struct fb_info *info,
  2418. caddr_t regbase,
  2419. enum cirrusfb_dbg_reg_class reg_class, ...)
  2420. {
  2421. va_list list;
  2422. unsigned char val = 0;
  2423. unsigned reg;
  2424. char *name;
  2425. va_start(list, reg_class);
  2426. name = va_arg(list, char *);
  2427. while (name != NULL) {
  2428. reg = va_arg(list, int);
  2429. switch (reg_class) {
  2430. case CRT:
  2431. val = vga_rcrt(regbase, (unsigned char) reg);
  2432. break;
  2433. case SEQ:
  2434. val = vga_rseq(regbase, (unsigned char) reg);
  2435. break;
  2436. default:
  2437. /* should never occur */
  2438. assert(false);
  2439. break;
  2440. }
  2441. dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
  2442. name = va_arg(list, char *);
  2443. }
  2444. va_end(list);
  2445. }
  2446. /**
  2447. * cirrusfb_dbg_reg_dump
  2448. * @base: If using newmmio, the newmmio base address, otherwise %NULL
  2449. *
  2450. * DESCRIPTION:
  2451. * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
  2452. * old-style I/O ports are queried for information, otherwise MMIO is
  2453. * used at the given @base address to query the information.
  2454. */
  2455. static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
  2456. {
  2457. dev_dbg(info->device, "VGA CRTC register dump:\n");
  2458. cirrusfb_dbg_print_regs(info, regbase, CRT,
  2459. "CR00", 0x00,
  2460. "CR01", 0x01,
  2461. "CR02", 0x02,
  2462. "CR03", 0x03,
  2463. "CR04", 0x04,
  2464. "CR05", 0x05,
  2465. "CR06", 0x06,
  2466. "CR07", 0x07,
  2467. "CR08", 0x08,
  2468. "CR09", 0x09,
  2469. "CR0A", 0x0A,
  2470. "CR0B", 0x0B,
  2471. "CR0C", 0x0C,
  2472. "CR0D", 0x0D,
  2473. "CR0E", 0x0E,
  2474. "CR0F", 0x0F,
  2475. "CR10", 0x10,
  2476. "CR11", 0x11,
  2477. "CR12", 0x12,
  2478. "CR13", 0x13,
  2479. "CR14", 0x14,
  2480. "CR15", 0x15,
  2481. "CR16", 0x16,
  2482. "CR17", 0x17,
  2483. "CR18", 0x18,
  2484. "CR22", 0x22,
  2485. "CR24", 0x24,
  2486. "CR26", 0x26,
  2487. "CR2D", 0x2D,
  2488. "CR2E", 0x2E,
  2489. "CR2F", 0x2F,
  2490. "CR30", 0x30,
  2491. "CR31", 0x31,
  2492. "CR32", 0x32,
  2493. "CR33", 0x33,
  2494. "CR34", 0x34,
  2495. "CR35", 0x35,
  2496. "CR36", 0x36,
  2497. "CR37", 0x37,
  2498. "CR38", 0x38,
  2499. "CR39", 0x39,
  2500. "CR3A", 0x3A,
  2501. "CR3B", 0x3B,
  2502. "CR3C", 0x3C,
  2503. "CR3D", 0x3D,
  2504. "CR3E", 0x3E,
  2505. "CR3F", 0x3F,
  2506. NULL);
  2507. dev_dbg(info->device, "\n");
  2508. dev_dbg(info->device, "VGA SEQ register dump:\n");
  2509. cirrusfb_dbg_print_regs(info, regbase, SEQ,
  2510. "SR00", 0x00,
  2511. "SR01", 0x01,
  2512. "SR02", 0x02,
  2513. "SR03", 0x03,
  2514. "SR04", 0x04,
  2515. "SR08", 0x08,
  2516. "SR09", 0x09,
  2517. "SR0A", 0x0A,
  2518. "SR0B", 0x0B,
  2519. "SR0D", 0x0D,
  2520. "SR10", 0x10,
  2521. "SR11", 0x11,
  2522. "SR12", 0x12,
  2523. "SR13", 0x13,
  2524. "SR14", 0x14,
  2525. "SR15", 0x15,
  2526. "SR16", 0x16,
  2527. "SR17", 0x17,
  2528. "SR18", 0x18,
  2529. "SR19", 0x19,
  2530. "SR1A", 0x1A,
  2531. "SR1B", 0x1B,
  2532. "SR1C", 0x1C,
  2533. "SR1D", 0x1D,
  2534. "SR1E", 0x1E,
  2535. "SR1F", 0x1F,
  2536. NULL);
  2537. dev_dbg(info->device, "\n");
  2538. }
  2539. #endif /* CIRRUSFB_DEBUG */