cg3.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* cg3.c: CGTHREE frame buffer driver
  3. *
  4. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  5. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  6. * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  7. * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
  8. *
  9. * Driver layout based loosely on tgafb.c, see that file for credits.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/errno.h>
  14. #include <linux/string.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/fb.h>
  18. #include <linux/mm.h>
  19. #include <linux/of_device.h>
  20. #include <asm/io.h>
  21. #include <asm/fbio.h>
  22. #include "sbuslib.h"
  23. /*
  24. * Local functions.
  25. */
  26. static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
  27. unsigned, struct fb_info *);
  28. static int cg3_blank(int, struct fb_info *);
  29. static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
  30. static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
  31. /*
  32. * Frame buffer operations
  33. */
  34. static const struct fb_ops cg3_ops = {
  35. .owner = THIS_MODULE,
  36. .fb_setcolreg = cg3_setcolreg,
  37. .fb_blank = cg3_blank,
  38. .fb_fillrect = cfb_fillrect,
  39. .fb_copyarea = cfb_copyarea,
  40. .fb_imageblit = cfb_imageblit,
  41. .fb_mmap = cg3_mmap,
  42. .fb_ioctl = cg3_ioctl,
  43. #ifdef CONFIG_COMPAT
  44. .fb_compat_ioctl = sbusfb_compat_ioctl,
  45. #endif
  46. };
  47. /* Control Register Constants */
  48. #define CG3_CR_ENABLE_INTS 0x80
  49. #define CG3_CR_ENABLE_VIDEO 0x40
  50. #define CG3_CR_ENABLE_TIMING 0x20
  51. #define CG3_CR_ENABLE_CURCMP 0x10
  52. #define CG3_CR_XTAL_MASK 0x0c
  53. #define CG3_CR_DIVISOR_MASK 0x03
  54. /* Status Register Constants */
  55. #define CG3_SR_PENDING_INT 0x80
  56. #define CG3_SR_RES_MASK 0x70
  57. #define CG3_SR_1152_900_76_A 0x40
  58. #define CG3_SR_1152_900_76_B 0x60
  59. #define CG3_SR_ID_MASK 0x0f
  60. #define CG3_SR_ID_COLOR 0x01
  61. #define CG3_SR_ID_MONO 0x02
  62. #define CG3_SR_ID_MONO_ECL 0x03
  63. enum cg3_type {
  64. CG3_AT_66HZ = 0,
  65. CG3_AT_76HZ,
  66. CG3_RDI
  67. };
  68. struct bt_regs {
  69. u32 addr;
  70. u32 color_map;
  71. u32 control;
  72. u32 cursor;
  73. };
  74. struct cg3_regs {
  75. struct bt_regs cmap;
  76. u8 control;
  77. u8 status;
  78. u8 cursor_start;
  79. u8 cursor_end;
  80. u8 h_blank_start;
  81. u8 h_blank_end;
  82. u8 h_sync_start;
  83. u8 h_sync_end;
  84. u8 comp_sync_end;
  85. u8 v_blank_start_high;
  86. u8 v_blank_start_low;
  87. u8 v_blank_end;
  88. u8 v_sync_start;
  89. u8 v_sync_end;
  90. u8 xfer_holdoff_start;
  91. u8 xfer_holdoff_end;
  92. };
  93. /* Offset of interesting structures in the OBIO space */
  94. #define CG3_REGS_OFFSET 0x400000UL
  95. #define CG3_RAM_OFFSET 0x800000UL
  96. struct cg3_par {
  97. spinlock_t lock;
  98. struct cg3_regs __iomem *regs;
  99. u32 sw_cmap[((256 * 3) + 3) / 4];
  100. u32 flags;
  101. #define CG3_FLAG_BLANKED 0x00000001
  102. #define CG3_FLAG_RDI 0x00000002
  103. unsigned long which_io;
  104. };
  105. /**
  106. * cg3_setcolreg - Optional function. Sets a color register.
  107. * @regno: boolean, 0 copy local, 1 get_user() function
  108. * @red: frame buffer colormap structure
  109. * @green: The green value which can be up to 16 bits wide
  110. * @blue: The blue value which can be up to 16 bits wide.
  111. * @transp: If supported the alpha value which can be up to 16 bits wide.
  112. * @info: frame buffer info structure
  113. *
  114. * The cg3 palette is loaded with 4 color values at each time
  115. * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
  116. * We keep a sw copy of the hw cmap to assist us in this esoteric
  117. * loading procedure.
  118. */
  119. static int cg3_setcolreg(unsigned regno,
  120. unsigned red, unsigned green, unsigned blue,
  121. unsigned transp, struct fb_info *info)
  122. {
  123. struct cg3_par *par = (struct cg3_par *) info->par;
  124. struct bt_regs __iomem *bt = &par->regs->cmap;
  125. unsigned long flags;
  126. u32 *p32;
  127. u8 *p8;
  128. int count;
  129. if (regno >= 256)
  130. return 1;
  131. red >>= 8;
  132. green >>= 8;
  133. blue >>= 8;
  134. spin_lock_irqsave(&par->lock, flags);
  135. p8 = (u8 *)par->sw_cmap + (regno * 3);
  136. p8[0] = red;
  137. p8[1] = green;
  138. p8[2] = blue;
  139. #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */
  140. #define D4M4(x) ((x)&~0x3) /* (x/4)*4 */
  141. count = 3;
  142. p32 = &par->sw_cmap[D4M3(regno)];
  143. sbus_writel(D4M4(regno), &bt->addr);
  144. while (count--)
  145. sbus_writel(*p32++, &bt->color_map);
  146. #undef D4M3
  147. #undef D4M4
  148. spin_unlock_irqrestore(&par->lock, flags);
  149. return 0;
  150. }
  151. /**
  152. * cg3_blank - Optional function. Blanks the display.
  153. * @blank_mode: the blank mode we want.
  154. * @info: frame buffer structure that represents a single frame buffer
  155. */
  156. static int cg3_blank(int blank, struct fb_info *info)
  157. {
  158. struct cg3_par *par = (struct cg3_par *) info->par;
  159. struct cg3_regs __iomem *regs = par->regs;
  160. unsigned long flags;
  161. u8 val;
  162. spin_lock_irqsave(&par->lock, flags);
  163. switch (blank) {
  164. case FB_BLANK_UNBLANK: /* Unblanking */
  165. val = sbus_readb(&regs->control);
  166. val |= CG3_CR_ENABLE_VIDEO;
  167. sbus_writeb(val, &regs->control);
  168. par->flags &= ~CG3_FLAG_BLANKED;
  169. break;
  170. case FB_BLANK_NORMAL: /* Normal blanking */
  171. case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
  172. case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
  173. case FB_BLANK_POWERDOWN: /* Poweroff */
  174. val = sbus_readb(&regs->control);
  175. val &= ~CG3_CR_ENABLE_VIDEO;
  176. sbus_writeb(val, &regs->control);
  177. par->flags |= CG3_FLAG_BLANKED;
  178. break;
  179. }
  180. spin_unlock_irqrestore(&par->lock, flags);
  181. return 0;
  182. }
  183. static struct sbus_mmap_map cg3_mmap_map[] = {
  184. {
  185. .voff = CG3_MMAP_OFFSET,
  186. .poff = CG3_RAM_OFFSET,
  187. .size = SBUS_MMAP_FBSIZE(1)
  188. },
  189. { .size = 0 }
  190. };
  191. static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
  192. {
  193. struct cg3_par *par = (struct cg3_par *)info->par;
  194. return sbusfb_mmap_helper(cg3_mmap_map,
  195. info->fix.smem_start, info->fix.smem_len,
  196. par->which_io,
  197. vma);
  198. }
  199. static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  200. {
  201. return sbusfb_ioctl_helper(cmd, arg, info,
  202. FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
  203. }
  204. /*
  205. * Initialisation
  206. */
  207. static void cg3_init_fix(struct fb_info *info, int linebytes,
  208. struct device_node *dp)
  209. {
  210. snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
  211. info->fix.type = FB_TYPE_PACKED_PIXELS;
  212. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  213. info->fix.line_length = linebytes;
  214. info->fix.accel = FB_ACCEL_SUN_CGTHREE;
  215. }
  216. static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
  217. struct device_node *dp)
  218. {
  219. const char *params;
  220. char *p;
  221. int ww, hh;
  222. params = of_get_property(dp, "params", NULL);
  223. if (params) {
  224. ww = simple_strtoul(params, &p, 10);
  225. if (ww && *p == 'x') {
  226. hh = simple_strtoul(p + 1, &p, 10);
  227. if (hh && *p == '-') {
  228. if (var->xres != ww ||
  229. var->yres != hh) {
  230. var->xres = var->xres_virtual = ww;
  231. var->yres = var->yres_virtual = hh;
  232. }
  233. }
  234. }
  235. }
  236. }
  237. static u8 cg3regvals_66hz[] = { /* 1152 x 900, 66 Hz */
  238. 0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
  239. 0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
  240. 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
  241. 0x10, 0x20, 0
  242. };
  243. static u8 cg3regvals_76hz[] = { /* 1152 x 900, 76 Hz */
  244. 0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
  245. 0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
  246. 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
  247. 0x10, 0x24, 0
  248. };
  249. static u8 cg3regvals_rdi[] = { /* 640 x 480, cgRDI */
  250. 0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
  251. 0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
  252. 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
  253. 0x10, 0x22, 0
  254. };
  255. static u8 *cg3_regvals[] = {
  256. cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
  257. };
  258. static u_char cg3_dacvals[] = {
  259. 4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
  260. };
  261. static int cg3_do_default_mode(struct cg3_par *par)
  262. {
  263. enum cg3_type type;
  264. u8 *p;
  265. if (par->flags & CG3_FLAG_RDI)
  266. type = CG3_RDI;
  267. else {
  268. u8 status = sbus_readb(&par->regs->status), mon;
  269. if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
  270. mon = status & CG3_SR_RES_MASK;
  271. if (mon == CG3_SR_1152_900_76_A ||
  272. mon == CG3_SR_1152_900_76_B)
  273. type = CG3_AT_76HZ;
  274. else
  275. type = CG3_AT_66HZ;
  276. } else {
  277. printk(KERN_ERR "cgthree: can't handle SR %02x\n",
  278. status);
  279. return -EINVAL;
  280. }
  281. }
  282. for (p = cg3_regvals[type]; *p; p += 2) {
  283. u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
  284. sbus_writeb(p[1], regp);
  285. }
  286. for (p = cg3_dacvals; *p; p += 2) {
  287. u8 __iomem *regp;
  288. regp = (u8 __iomem *)&par->regs->cmap.addr;
  289. sbus_writeb(p[0], regp);
  290. regp = (u8 __iomem *)&par->regs->cmap.control;
  291. sbus_writeb(p[1], regp);
  292. }
  293. return 0;
  294. }
  295. static int cg3_probe(struct platform_device *op)
  296. {
  297. struct device_node *dp = op->dev.of_node;
  298. struct fb_info *info;
  299. struct cg3_par *par;
  300. int linebytes, err;
  301. info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);
  302. err = -ENOMEM;
  303. if (!info)
  304. goto out_err;
  305. par = info->par;
  306. spin_lock_init(&par->lock);
  307. info->fix.smem_start = op->resource[0].start;
  308. par->which_io = op->resource[0].flags & IORESOURCE_BITS;
  309. sbusfb_fill_var(&info->var, dp, 8);
  310. info->var.red.length = 8;
  311. info->var.green.length = 8;
  312. info->var.blue.length = 8;
  313. if (of_node_name_eq(dp, "cgRDI"))
  314. par->flags |= CG3_FLAG_RDI;
  315. if (par->flags & CG3_FLAG_RDI)
  316. cg3_rdi_maybe_fixup_var(&info->var, dp);
  317. linebytes = of_getintprop_default(dp, "linebytes",
  318. info->var.xres);
  319. info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
  320. par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
  321. sizeof(struct cg3_regs), "cg3 regs");
  322. if (!par->regs)
  323. goto out_release_fb;
  324. info->flags = FBINFO_DEFAULT;
  325. info->fbops = &cg3_ops;
  326. info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
  327. info->fix.smem_len, "cg3 ram");
  328. if (!info->screen_base)
  329. goto out_unmap_regs;
  330. cg3_blank(FB_BLANK_UNBLANK, info);
  331. if (!of_find_property(dp, "width", NULL)) {
  332. err = cg3_do_default_mode(par);
  333. if (err)
  334. goto out_unmap_screen;
  335. }
  336. err = fb_alloc_cmap(&info->cmap, 256, 0);
  337. if (err)
  338. goto out_unmap_screen;
  339. fb_set_cmap(&info->cmap, info);
  340. cg3_init_fix(info, linebytes, dp);
  341. err = register_framebuffer(info);
  342. if (err < 0)
  343. goto out_dealloc_cmap;
  344. dev_set_drvdata(&op->dev, info);
  345. printk(KERN_INFO "%pOF: cg3 at %lx:%lx\n",
  346. dp, par->which_io, info->fix.smem_start);
  347. return 0;
  348. out_dealloc_cmap:
  349. fb_dealloc_cmap(&info->cmap);
  350. out_unmap_screen:
  351. of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
  352. out_unmap_regs:
  353. of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
  354. out_release_fb:
  355. framebuffer_release(info);
  356. out_err:
  357. return err;
  358. }
  359. static int cg3_remove(struct platform_device *op)
  360. {
  361. struct fb_info *info = dev_get_drvdata(&op->dev);
  362. struct cg3_par *par = info->par;
  363. unregister_framebuffer(info);
  364. fb_dealloc_cmap(&info->cmap);
  365. of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
  366. of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
  367. framebuffer_release(info);
  368. return 0;
  369. }
  370. static const struct of_device_id cg3_match[] = {
  371. {
  372. .name = "cgthree",
  373. },
  374. {
  375. .name = "cgRDI",
  376. },
  377. {},
  378. };
  379. MODULE_DEVICE_TABLE(of, cg3_match);
  380. static struct platform_driver cg3_driver = {
  381. .driver = {
  382. .name = "cg3",
  383. .of_match_table = cg3_match,
  384. },
  385. .probe = cg3_probe,
  386. .remove = cg3_remove,
  387. };
  388. static int __init cg3_init(void)
  389. {
  390. if (fb_get_options("cg3fb", NULL))
  391. return -ENODEV;
  392. return platform_driver_register(&cg3_driver);
  393. }
  394. static void __exit cg3_exit(void)
  395. {
  396. platform_driver_unregister(&cg3_driver);
  397. }
  398. module_init(cg3_init);
  399. module_exit(cg3_exit);
  400. MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
  401. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  402. MODULE_VERSION("2.0");
  403. MODULE_LICENSE("GPL");