otm3225a.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Driver for ORISE Technology OTM3225A SOC for TFT LCD
  3. * Copyright (C) 2017, EETS GmbH, Felix Brack <fb@ltec.ch>
  4. *
  5. * This driver implements a lcd device for the ORISE OTM3225A display
  6. * controller. The control interface to the display is SPI and the display's
  7. * memory is updated over the 16-bit RGB interface.
  8. * The main source of information for writing this driver was provided by the
  9. * OTM3225A datasheet from ORISE Technology. Some information arise from the
  10. * ILI9328 datasheet from ILITEK as well as from the datasheets and sample code
  11. * provided by Crystalfontz America Inc. who sells the CFAF240320A-032T, a 3.2"
  12. * TFT LC display using the OTM3225A controller.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/kernel.h>
  17. #include <linux/lcd.h>
  18. #include <linux/module.h>
  19. #include <linux/spi/spi.h>
  20. #define OTM3225A_INDEX_REG 0x70
  21. #define OTM3225A_DATA_REG 0x72
  22. /* instruction register list */
  23. #define DRIVER_OUTPUT_CTRL_1 0x01
  24. #define DRIVER_WAVEFORM_CTRL 0x02
  25. #define ENTRY_MODE 0x03
  26. #define SCALING_CTRL 0x04
  27. #define DISPLAY_CTRL_1 0x07
  28. #define DISPLAY_CTRL_2 0x08
  29. #define DISPLAY_CTRL_3 0x09
  30. #define FRAME_CYCLE_CTRL 0x0A
  31. #define EXT_DISP_IFACE_CTRL_1 0x0C
  32. #define FRAME_MAKER_POS 0x0D
  33. #define EXT_DISP_IFACE_CTRL_2 0x0F
  34. #define POWER_CTRL_1 0x10
  35. #define POWER_CTRL_2 0x11
  36. #define POWER_CTRL_3 0x12
  37. #define POWER_CTRL_4 0x13
  38. #define GRAM_ADDR_HORIZ_SET 0x20
  39. #define GRAM_ADDR_VERT_SET 0x21
  40. #define GRAM_READ_WRITE 0x22
  41. #define POWER_CTRL_7 0x29
  42. #define FRAME_RATE_CTRL 0x2B
  43. #define GAMMA_CTRL_1 0x30
  44. #define GAMMA_CTRL_2 0x31
  45. #define GAMMA_CTRL_3 0x32
  46. #define GAMMA_CTRL_4 0x35
  47. #define GAMMA_CTRL_5 0x36
  48. #define GAMMA_CTRL_6 0x37
  49. #define GAMMA_CTRL_7 0x38
  50. #define GAMMA_CTRL_8 0x39
  51. #define GAMMA_CTRL_9 0x3C
  52. #define GAMMA_CTRL_10 0x3D
  53. #define WINDOW_HORIZ_RAM_START 0x50
  54. #define WINDOW_HORIZ_RAM_END 0x51
  55. #define WINDOW_VERT_RAM_START 0x52
  56. #define WINDOW_VERT_RAM_END 0x53
  57. #define DRIVER_OUTPUT_CTRL_2 0x60
  58. #define BASE_IMG_DISPLAY_CTRL 0x61
  59. #define VERT_SCROLL_CTRL 0x6A
  60. #define PD1_DISPLAY_POS 0x80
  61. #define PD1_RAM_START 0x81
  62. #define PD1_RAM_END 0x82
  63. #define PD2_DISPLAY_POS 0x83
  64. #define PD2_RAM_START 0x84
  65. #define PD2_RAM_END 0x85
  66. #define PANEL_IFACE_CTRL_1 0x90
  67. #define PANEL_IFACE_CTRL_2 0x92
  68. #define PANEL_IFACE_CTRL_4 0x95
  69. #define PANEL_IFACE_CTRL_5 0x97
  70. struct otm3225a_data {
  71. struct spi_device *spi;
  72. struct lcd_device *ld;
  73. int power;
  74. };
  75. struct otm3225a_spi_instruction {
  76. unsigned char reg; /* register to write */
  77. unsigned short value; /* data to write to 'reg' */
  78. unsigned short delay; /* delay in ms after write */
  79. };
  80. static struct otm3225a_spi_instruction display_init[] = {
  81. { DRIVER_OUTPUT_CTRL_1, 0x0000, 0 },
  82. { DRIVER_WAVEFORM_CTRL, 0x0700, 0 },
  83. { ENTRY_MODE, 0x50A0, 0 },
  84. { SCALING_CTRL, 0x0000, 0 },
  85. { DISPLAY_CTRL_2, 0x0606, 0 },
  86. { DISPLAY_CTRL_3, 0x0000, 0 },
  87. { FRAME_CYCLE_CTRL, 0x0000, 0 },
  88. { EXT_DISP_IFACE_CTRL_1, 0x0000, 0 },
  89. { FRAME_MAKER_POS, 0x0000, 0 },
  90. { EXT_DISP_IFACE_CTRL_2, 0x0002, 0 },
  91. { POWER_CTRL_2, 0x0007, 0 },
  92. { POWER_CTRL_3, 0x0000, 0 },
  93. { POWER_CTRL_4, 0x0000, 200 },
  94. { DISPLAY_CTRL_1, 0x0101, 0 },
  95. { POWER_CTRL_1, 0x12B0, 0 },
  96. { POWER_CTRL_2, 0x0007, 0 },
  97. { POWER_CTRL_3, 0x01BB, 50 },
  98. { POWER_CTRL_4, 0x0013, 0 },
  99. { POWER_CTRL_7, 0x0010, 50 },
  100. { GAMMA_CTRL_1, 0x000A, 0 },
  101. { GAMMA_CTRL_2, 0x1326, 0 },
  102. { GAMMA_CTRL_3, 0x0A29, 0 },
  103. { GAMMA_CTRL_4, 0x0A0A, 0 },
  104. { GAMMA_CTRL_5, 0x1E03, 0 },
  105. { GAMMA_CTRL_6, 0x031E, 0 },
  106. { GAMMA_CTRL_7, 0x0706, 0 },
  107. { GAMMA_CTRL_8, 0x0303, 0 },
  108. { GAMMA_CTRL_9, 0x010E, 0 },
  109. { GAMMA_CTRL_10, 0x040E, 0 },
  110. { WINDOW_HORIZ_RAM_START, 0x0000, 0 },
  111. { WINDOW_HORIZ_RAM_END, 0x00EF, 0 },
  112. { WINDOW_VERT_RAM_START, 0x0000, 0 },
  113. { WINDOW_VERT_RAM_END, 0x013F, 0 },
  114. { DRIVER_OUTPUT_CTRL_2, 0x2700, 0 },
  115. { BASE_IMG_DISPLAY_CTRL, 0x0001, 0 },
  116. { VERT_SCROLL_CTRL, 0x0000, 0 },
  117. { PD1_DISPLAY_POS, 0x0000, 0 },
  118. { PD1_RAM_START, 0x0000, 0 },
  119. { PD1_RAM_END, 0x0000, 0 },
  120. { PD2_DISPLAY_POS, 0x0000, 0 },
  121. { PD2_RAM_START, 0x0000, 0 },
  122. { PD2_RAM_END, 0x0000, 0 },
  123. { PANEL_IFACE_CTRL_1, 0x0010, 0 },
  124. { PANEL_IFACE_CTRL_2, 0x0000, 0 },
  125. { PANEL_IFACE_CTRL_4, 0x0210, 0 },
  126. { PANEL_IFACE_CTRL_5, 0x0000, 0 },
  127. { DISPLAY_CTRL_1, 0x0133, 0 },
  128. };
  129. static struct otm3225a_spi_instruction display_enable_rgb_interface[] = {
  130. { ENTRY_MODE, 0x1080, 0 },
  131. { GRAM_ADDR_HORIZ_SET, 0x0000, 0 },
  132. { GRAM_ADDR_VERT_SET, 0x0000, 0 },
  133. { EXT_DISP_IFACE_CTRL_1, 0x0111, 500 },
  134. };
  135. static struct otm3225a_spi_instruction display_off[] = {
  136. { DISPLAY_CTRL_1, 0x0131, 100 },
  137. { DISPLAY_CTRL_1, 0x0130, 100 },
  138. { DISPLAY_CTRL_1, 0x0100, 0 },
  139. { POWER_CTRL_1, 0x0280, 0 },
  140. { POWER_CTRL_3, 0x018B, 0 },
  141. };
  142. static struct otm3225a_spi_instruction display_on[] = {
  143. { POWER_CTRL_1, 0x1280, 0 },
  144. { DISPLAY_CTRL_1, 0x0101, 100 },
  145. { DISPLAY_CTRL_1, 0x0121, 0 },
  146. { DISPLAY_CTRL_1, 0x0123, 100 },
  147. { DISPLAY_CTRL_1, 0x0133, 10 },
  148. };
  149. static void otm3225a_write(struct spi_device *spi,
  150. struct otm3225a_spi_instruction *instruction,
  151. unsigned int count)
  152. {
  153. unsigned char buf[3];
  154. while (count--) {
  155. /* address register using index register */
  156. buf[0] = OTM3225A_INDEX_REG;
  157. buf[1] = 0x00;
  158. buf[2] = instruction->reg;
  159. spi_write(spi, buf, 3);
  160. /* write data to addressed register */
  161. buf[0] = OTM3225A_DATA_REG;
  162. buf[1] = (instruction->value >> 8) & 0xff;
  163. buf[2] = instruction->value & 0xff;
  164. spi_write(spi, buf, 3);
  165. /* execute delay if any */
  166. if (instruction->delay)
  167. msleep(instruction->delay);
  168. instruction++;
  169. }
  170. }
  171. static int otm3225a_set_power(struct lcd_device *ld, int power)
  172. {
  173. struct otm3225a_data *dd = lcd_get_data(ld);
  174. if (power == dd->power)
  175. return 0;
  176. if (power > FB_BLANK_UNBLANK)
  177. otm3225a_write(dd->spi, display_off, ARRAY_SIZE(display_off));
  178. else
  179. otm3225a_write(dd->spi, display_on, ARRAY_SIZE(display_on));
  180. dd->power = power;
  181. return 0;
  182. }
  183. static int otm3225a_get_power(struct lcd_device *ld)
  184. {
  185. struct otm3225a_data *dd = lcd_get_data(ld);
  186. return dd->power;
  187. }
  188. static struct lcd_ops otm3225a_ops = {
  189. .set_power = otm3225a_set_power,
  190. .get_power = otm3225a_get_power,
  191. };
  192. static int otm3225a_probe(struct spi_device *spi)
  193. {
  194. struct otm3225a_data *dd;
  195. struct lcd_device *ld;
  196. struct device *dev = &spi->dev;
  197. dd = devm_kzalloc(dev, sizeof(struct otm3225a_data), GFP_KERNEL);
  198. if (dd == NULL)
  199. return -ENOMEM;
  200. ld = devm_lcd_device_register(dev, dev_name(dev), dev, dd,
  201. &otm3225a_ops);
  202. if (IS_ERR(ld))
  203. return PTR_ERR(ld);
  204. dd->spi = spi;
  205. dd->ld = ld;
  206. dev_set_drvdata(dev, dd);
  207. dev_info(dev, "Initializing and switching to RGB interface");
  208. otm3225a_write(spi, display_init, ARRAY_SIZE(display_init));
  209. otm3225a_write(spi, display_enable_rgb_interface,
  210. ARRAY_SIZE(display_enable_rgb_interface));
  211. return 0;
  212. }
  213. static struct spi_driver otm3225a_driver = {
  214. .driver = {
  215. .name = "otm3225a",
  216. .owner = THIS_MODULE,
  217. },
  218. .probe = otm3225a_probe,
  219. };
  220. module_spi_driver(otm3225a_driver);
  221. MODULE_AUTHOR("Felix Brack <fb@ltec.ch>");
  222. MODULE_DESCRIPTION("OTM3225A TFT LCD driver");
  223. MODULE_VERSION("1.0.0");
  224. MODULE_LICENSE("GPL v2");