hd3ss3220.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI HD3SS3220 Type-C DRP Port Controller Driver
  4. *
  5. * Copyright (C) 2019 Renesas Electronics Corp.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/i2c.h>
  9. #include <linux/usb/role.h>
  10. #include <linux/irqreturn.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/regmap.h>
  13. #include <linux/slab.h>
  14. #include <linux/usb/typec.h>
  15. #include <linux/delay.h>
  16. #define HD3SS3220_REG_CN_STAT_CTRL 0x09
  17. #define HD3SS3220_REG_GEN_CTRL 0x0A
  18. #define HD3SS3220_REG_DEV_REV 0xA0
  19. /* Register HD3SS3220_REG_CN_STAT_CTRL*/
  20. #define HD3SS3220_REG_CN_STAT_CTRL_ATTACHED_STATE_MASK (BIT(7) | BIT(6))
  21. #define HD3SS3220_REG_CN_STAT_CTRL_AS_DFP BIT(6)
  22. #define HD3SS3220_REG_CN_STAT_CTRL_AS_UFP BIT(7)
  23. #define HD3SS3220_REG_CN_STAT_CTRL_TO_ACCESSORY (BIT(7) | BIT(6))
  24. #define HD3SS3220_REG_CN_STAT_CTRL_INT_STATUS BIT(4)
  25. /* Register HD3SS3220_REG_GEN_CTRL*/
  26. #define HD3SS3220_REG_GEN_CTRL_SRC_PREF_MASK (BIT(2) | BIT(1))
  27. #define HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_DEFAULT 0x00
  28. #define HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_TRY_SNK BIT(1)
  29. #define HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_TRY_SRC (BIT(2) | BIT(1))
  30. struct hd3ss3220 {
  31. struct device *dev;
  32. struct regmap *regmap;
  33. struct usb_role_switch *role_sw;
  34. struct typec_port *port;
  35. };
  36. static int hd3ss3220_set_source_pref(struct hd3ss3220 *hd3ss3220, int src_pref)
  37. {
  38. return regmap_update_bits(hd3ss3220->regmap, HD3SS3220_REG_GEN_CTRL,
  39. HD3SS3220_REG_GEN_CTRL_SRC_PREF_MASK,
  40. src_pref);
  41. }
  42. static enum usb_role hd3ss3220_get_attached_state(struct hd3ss3220 *hd3ss3220)
  43. {
  44. unsigned int reg_val;
  45. enum usb_role attached_state;
  46. int ret;
  47. ret = regmap_read(hd3ss3220->regmap, HD3SS3220_REG_CN_STAT_CTRL,
  48. &reg_val);
  49. if (ret < 0)
  50. return ret;
  51. switch (reg_val & HD3SS3220_REG_CN_STAT_CTRL_ATTACHED_STATE_MASK) {
  52. case HD3SS3220_REG_CN_STAT_CTRL_AS_DFP:
  53. attached_state = USB_ROLE_HOST;
  54. break;
  55. case HD3SS3220_REG_CN_STAT_CTRL_AS_UFP:
  56. attached_state = USB_ROLE_DEVICE;
  57. break;
  58. default:
  59. attached_state = USB_ROLE_NONE;
  60. break;
  61. }
  62. return attached_state;
  63. }
  64. static int hd3ss3220_dr_set(struct typec_port *port, enum typec_data_role role)
  65. {
  66. struct hd3ss3220 *hd3ss3220 = typec_get_drvdata(port);
  67. enum usb_role role_val;
  68. int pref, ret = 0;
  69. if (role == TYPEC_HOST) {
  70. role_val = USB_ROLE_HOST;
  71. pref = HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_TRY_SRC;
  72. } else {
  73. role_val = USB_ROLE_DEVICE;
  74. pref = HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_TRY_SNK;
  75. }
  76. ret = hd3ss3220_set_source_pref(hd3ss3220, pref);
  77. usleep_range(10, 100);
  78. usb_role_switch_set_role(hd3ss3220->role_sw, role_val);
  79. typec_set_data_role(hd3ss3220->port, role);
  80. return ret;
  81. }
  82. static const struct typec_operations hd3ss3220_ops = {
  83. .dr_set = hd3ss3220_dr_set
  84. };
  85. static void hd3ss3220_set_role(struct hd3ss3220 *hd3ss3220)
  86. {
  87. enum usb_role role_state = hd3ss3220_get_attached_state(hd3ss3220);
  88. usb_role_switch_set_role(hd3ss3220->role_sw, role_state);
  89. if (role_state == USB_ROLE_NONE)
  90. hd3ss3220_set_source_pref(hd3ss3220,
  91. HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_DEFAULT);
  92. switch (role_state) {
  93. case USB_ROLE_HOST:
  94. typec_set_data_role(hd3ss3220->port, TYPEC_HOST);
  95. break;
  96. case USB_ROLE_DEVICE:
  97. typec_set_data_role(hd3ss3220->port, TYPEC_DEVICE);
  98. break;
  99. default:
  100. break;
  101. }
  102. }
  103. static irqreturn_t hd3ss3220_irq(struct hd3ss3220 *hd3ss3220)
  104. {
  105. int err;
  106. hd3ss3220_set_role(hd3ss3220);
  107. err = regmap_update_bits_base(hd3ss3220->regmap,
  108. HD3SS3220_REG_CN_STAT_CTRL,
  109. HD3SS3220_REG_CN_STAT_CTRL_INT_STATUS,
  110. HD3SS3220_REG_CN_STAT_CTRL_INT_STATUS,
  111. NULL, false, true);
  112. if (err < 0)
  113. return IRQ_NONE;
  114. return IRQ_HANDLED;
  115. }
  116. static irqreturn_t hd3ss3220_irq_handler(int irq, void *data)
  117. {
  118. struct i2c_client *client = to_i2c_client(data);
  119. struct hd3ss3220 *hd3ss3220 = i2c_get_clientdata(client);
  120. return hd3ss3220_irq(hd3ss3220);
  121. }
  122. static const struct regmap_config config = {
  123. .reg_bits = 8,
  124. .val_bits = 8,
  125. .max_register = 0x0A,
  126. };
  127. static int hd3ss3220_probe(struct i2c_client *client,
  128. const struct i2c_device_id *id)
  129. {
  130. struct typec_capability typec_cap = { };
  131. struct hd3ss3220 *hd3ss3220;
  132. struct fwnode_handle *connector, *ep;
  133. int ret;
  134. unsigned int data;
  135. hd3ss3220 = devm_kzalloc(&client->dev, sizeof(struct hd3ss3220),
  136. GFP_KERNEL);
  137. if (!hd3ss3220)
  138. return -ENOMEM;
  139. i2c_set_clientdata(client, hd3ss3220);
  140. hd3ss3220->dev = &client->dev;
  141. hd3ss3220->regmap = devm_regmap_init_i2c(client, &config);
  142. if (IS_ERR(hd3ss3220->regmap))
  143. return PTR_ERR(hd3ss3220->regmap);
  144. hd3ss3220_set_source_pref(hd3ss3220,
  145. HD3SS3220_REG_GEN_CTRL_SRC_PREF_DRP_DEFAULT);
  146. /* For backward compatibility check the connector child node first */
  147. connector = device_get_named_child_node(hd3ss3220->dev, "connector");
  148. if (connector) {
  149. hd3ss3220->role_sw = fwnode_usb_role_switch_get(connector);
  150. } else {
  151. ep = fwnode_graph_get_next_endpoint(dev_fwnode(hd3ss3220->dev), NULL);
  152. if (!ep)
  153. return -ENODEV;
  154. connector = fwnode_graph_get_remote_port_parent(ep);
  155. fwnode_handle_put(ep);
  156. if (!connector)
  157. return -ENODEV;
  158. hd3ss3220->role_sw = usb_role_switch_get(hd3ss3220->dev);
  159. }
  160. if (IS_ERR(hd3ss3220->role_sw)) {
  161. ret = PTR_ERR(hd3ss3220->role_sw);
  162. goto err_put_fwnode;
  163. }
  164. typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE;
  165. typec_cap.driver_data = hd3ss3220;
  166. typec_cap.type = TYPEC_PORT_DRP;
  167. typec_cap.data = TYPEC_PORT_DRD;
  168. typec_cap.ops = &hd3ss3220_ops;
  169. typec_cap.fwnode = connector;
  170. hd3ss3220->port = typec_register_port(&client->dev, &typec_cap);
  171. if (IS_ERR(hd3ss3220->port)) {
  172. ret = PTR_ERR(hd3ss3220->port);
  173. goto err_put_role;
  174. }
  175. hd3ss3220_set_role(hd3ss3220);
  176. ret = regmap_read(hd3ss3220->regmap, HD3SS3220_REG_CN_STAT_CTRL, &data);
  177. if (ret < 0)
  178. goto err_unreg_port;
  179. if (data & HD3SS3220_REG_CN_STAT_CTRL_INT_STATUS) {
  180. ret = regmap_write(hd3ss3220->regmap,
  181. HD3SS3220_REG_CN_STAT_CTRL,
  182. data | HD3SS3220_REG_CN_STAT_CTRL_INT_STATUS);
  183. if (ret < 0)
  184. goto err_unreg_port;
  185. }
  186. if (client->irq > 0) {
  187. ret = devm_request_threaded_irq(&client->dev, client->irq, NULL,
  188. hd3ss3220_irq_handler,
  189. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  190. "hd3ss3220", &client->dev);
  191. if (ret)
  192. goto err_unreg_port;
  193. }
  194. ret = i2c_smbus_read_byte_data(client, HD3SS3220_REG_DEV_REV);
  195. if (ret < 0)
  196. goto err_unreg_port;
  197. fwnode_handle_put(connector);
  198. dev_info(&client->dev, "probed revision=0x%x\n", ret);
  199. return 0;
  200. err_unreg_port:
  201. typec_unregister_port(hd3ss3220->port);
  202. err_put_role:
  203. usb_role_switch_put(hd3ss3220->role_sw);
  204. err_put_fwnode:
  205. fwnode_handle_put(connector);
  206. return ret;
  207. }
  208. static int hd3ss3220_remove(struct i2c_client *client)
  209. {
  210. struct hd3ss3220 *hd3ss3220 = i2c_get_clientdata(client);
  211. typec_unregister_port(hd3ss3220->port);
  212. usb_role_switch_put(hd3ss3220->role_sw);
  213. return 0;
  214. }
  215. static const struct of_device_id dev_ids[] = {
  216. { .compatible = "ti,hd3ss3220"},
  217. {}
  218. };
  219. MODULE_DEVICE_TABLE(of, dev_ids);
  220. static struct i2c_driver hd3ss3220_driver = {
  221. .driver = {
  222. .name = "hd3ss3220",
  223. .of_match_table = of_match_ptr(dev_ids),
  224. },
  225. .probe = hd3ss3220_probe,
  226. .remove = hd3ss3220_remove,
  227. };
  228. module_i2c_driver(hd3ss3220_driver);
  229. MODULE_AUTHOR("Biju Das <biju.das@bp.renesas.com>");
  230. MODULE_DESCRIPTION("TI HD3SS3220 DRP Port Controller Driver");
  231. MODULE_LICENSE("GPL");