phy-mv-usb.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
  4. * Author: Chao Xie <chao.xie@marvell.com>
  5. * Neil Zhang <zhangwm@marvell.com>
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/io.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/uaccess.h>
  12. #include <linux/device.h>
  13. #include <linux/proc_fs.h>
  14. #include <linux/clk.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/usb.h>
  18. #include <linux/usb/ch9.h>
  19. #include <linux/usb/otg.h>
  20. #include <linux/usb/gadget.h>
  21. #include <linux/usb/hcd.h>
  22. #include <linux/platform_data/mv_usb.h>
  23. #include "phy-mv-usb.h"
  24. #define DRIVER_DESC "Marvell USB OTG transceiver driver"
  25. MODULE_DESCRIPTION(DRIVER_DESC);
  26. MODULE_LICENSE("GPL");
  27. static const char driver_name[] = "mv-otg";
  28. static char *state_string[] = {
  29. "undefined",
  30. "b_idle",
  31. "b_srp_init",
  32. "b_peripheral",
  33. "b_wait_acon",
  34. "b_host",
  35. "a_idle",
  36. "a_wait_vrise",
  37. "a_wait_bcon",
  38. "a_host",
  39. "a_suspend",
  40. "a_peripheral",
  41. "a_wait_vfall",
  42. "a_vbus_err"
  43. };
  44. static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
  45. {
  46. struct mv_otg *mvotg = container_of(otg->usb_phy, struct mv_otg, phy);
  47. if (mvotg->pdata->set_vbus == NULL)
  48. return -ENODEV;
  49. return mvotg->pdata->set_vbus(on);
  50. }
  51. static int mv_otg_set_host(struct usb_otg *otg,
  52. struct usb_bus *host)
  53. {
  54. otg->host = host;
  55. return 0;
  56. }
  57. static int mv_otg_set_peripheral(struct usb_otg *otg,
  58. struct usb_gadget *gadget)
  59. {
  60. otg->gadget = gadget;
  61. return 0;
  62. }
  63. static void mv_otg_run_state_machine(struct mv_otg *mvotg,
  64. unsigned long delay)
  65. {
  66. dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
  67. if (!mvotg->qwork)
  68. return;
  69. queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
  70. }
  71. static void mv_otg_timer_await_bcon(struct timer_list *t)
  72. {
  73. struct mv_otg *mvotg = from_timer(mvotg, t,
  74. otg_ctrl.timer[A_WAIT_BCON_TIMER]);
  75. mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
  76. dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
  77. if (spin_trylock(&mvotg->wq_lock)) {
  78. mv_otg_run_state_machine(mvotg, 0);
  79. spin_unlock(&mvotg->wq_lock);
  80. }
  81. }
  82. static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
  83. {
  84. struct timer_list *timer;
  85. if (id >= OTG_TIMER_NUM)
  86. return -EINVAL;
  87. timer = &mvotg->otg_ctrl.timer[id];
  88. if (timer_pending(timer))
  89. del_timer(timer);
  90. return 0;
  91. }
  92. static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
  93. unsigned long interval)
  94. {
  95. struct timer_list *timer;
  96. if (id >= OTG_TIMER_NUM)
  97. return -EINVAL;
  98. timer = &mvotg->otg_ctrl.timer[id];
  99. if (timer_pending(timer)) {
  100. dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
  101. return -EBUSY;
  102. }
  103. timer->expires = jiffies + interval;
  104. add_timer(timer);
  105. return 0;
  106. }
  107. static int mv_otg_reset(struct mv_otg *mvotg)
  108. {
  109. u32 tmp;
  110. int ret;
  111. /* Stop the controller */
  112. tmp = readl(&mvotg->op_regs->usbcmd);
  113. tmp &= ~USBCMD_RUN_STOP;
  114. writel(tmp, &mvotg->op_regs->usbcmd);
  115. /* Reset the controller to get default values */
  116. writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
  117. ret = readl_poll_timeout_atomic(&mvotg->op_regs->usbcmd, tmp,
  118. (tmp & USBCMD_CTRL_RESET), 10, 10000);
  119. if (ret < 0) {
  120. dev_err(&mvotg->pdev->dev,
  121. "Wait for RESET completed TIMEOUT\n");
  122. return ret;
  123. }
  124. writel(0x0, &mvotg->op_regs->usbintr);
  125. tmp = readl(&mvotg->op_regs->usbsts);
  126. writel(tmp, &mvotg->op_regs->usbsts);
  127. return 0;
  128. }
  129. static void mv_otg_init_irq(struct mv_otg *mvotg)
  130. {
  131. u32 otgsc;
  132. mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
  133. | OTGSC_INTR_A_VBUS_VALID;
  134. mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
  135. | OTGSC_INTSTS_A_VBUS_VALID;
  136. if (mvotg->pdata->vbus == NULL) {
  137. mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
  138. | OTGSC_INTR_B_SESSION_END;
  139. mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
  140. | OTGSC_INTSTS_B_SESSION_END;
  141. }
  142. if (mvotg->pdata->id == NULL) {
  143. mvotg->irq_en |= OTGSC_INTR_USB_ID;
  144. mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
  145. }
  146. otgsc = readl(&mvotg->op_regs->otgsc);
  147. otgsc |= mvotg->irq_en;
  148. writel(otgsc, &mvotg->op_regs->otgsc);
  149. }
  150. static void mv_otg_start_host(struct mv_otg *mvotg, int on)
  151. {
  152. #ifdef CONFIG_USB
  153. struct usb_otg *otg = mvotg->phy.otg;
  154. struct usb_hcd *hcd;
  155. if (!otg->host)
  156. return;
  157. dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
  158. hcd = bus_to_hcd(otg->host);
  159. if (on) {
  160. usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
  161. device_wakeup_enable(hcd->self.controller);
  162. } else {
  163. usb_remove_hcd(hcd);
  164. }
  165. #endif /* CONFIG_USB */
  166. }
  167. static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
  168. {
  169. struct usb_otg *otg = mvotg->phy.otg;
  170. if (!otg->gadget)
  171. return;
  172. dev_info(mvotg->phy.dev, "gadget %s\n", on ? "on" : "off");
  173. if (on)
  174. usb_gadget_vbus_connect(otg->gadget);
  175. else
  176. usb_gadget_vbus_disconnect(otg->gadget);
  177. }
  178. static void otg_clock_enable(struct mv_otg *mvotg)
  179. {
  180. clk_prepare_enable(mvotg->clk);
  181. }
  182. static void otg_clock_disable(struct mv_otg *mvotg)
  183. {
  184. clk_disable_unprepare(mvotg->clk);
  185. }
  186. static int mv_otg_enable_internal(struct mv_otg *mvotg)
  187. {
  188. int retval = 0;
  189. if (mvotg->active)
  190. return 0;
  191. dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
  192. otg_clock_enable(mvotg);
  193. if (mvotg->pdata->phy_init) {
  194. retval = mvotg->pdata->phy_init(mvotg->phy_regs);
  195. if (retval) {
  196. dev_err(&mvotg->pdev->dev,
  197. "init phy error %d\n", retval);
  198. otg_clock_disable(mvotg);
  199. return retval;
  200. }
  201. }
  202. mvotg->active = 1;
  203. return 0;
  204. }
  205. static int mv_otg_enable(struct mv_otg *mvotg)
  206. {
  207. if (mvotg->clock_gating)
  208. return mv_otg_enable_internal(mvotg);
  209. return 0;
  210. }
  211. static void mv_otg_disable_internal(struct mv_otg *mvotg)
  212. {
  213. if (mvotg->active) {
  214. dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
  215. if (mvotg->pdata->phy_deinit)
  216. mvotg->pdata->phy_deinit(mvotg->phy_regs);
  217. otg_clock_disable(mvotg);
  218. mvotg->active = 0;
  219. }
  220. }
  221. static void mv_otg_disable(struct mv_otg *mvotg)
  222. {
  223. if (mvotg->clock_gating)
  224. mv_otg_disable_internal(mvotg);
  225. }
  226. static void mv_otg_update_inputs(struct mv_otg *mvotg)
  227. {
  228. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  229. u32 otgsc;
  230. otgsc = readl(&mvotg->op_regs->otgsc);
  231. if (mvotg->pdata->vbus) {
  232. if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
  233. otg_ctrl->b_sess_vld = 1;
  234. otg_ctrl->b_sess_end = 0;
  235. } else {
  236. otg_ctrl->b_sess_vld = 0;
  237. otg_ctrl->b_sess_end = 1;
  238. }
  239. } else {
  240. otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
  241. otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
  242. }
  243. if (mvotg->pdata->id)
  244. otg_ctrl->id = !!mvotg->pdata->id->poll();
  245. else
  246. otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
  247. if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
  248. otg_ctrl->a_bus_req = 1;
  249. otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
  250. otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
  251. dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
  252. dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
  253. dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
  254. dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
  255. dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
  256. dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
  257. }
  258. static void mv_otg_update_state(struct mv_otg *mvotg)
  259. {
  260. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  261. int old_state = mvotg->phy.otg->state;
  262. switch (old_state) {
  263. case OTG_STATE_UNDEFINED:
  264. mvotg->phy.otg->state = OTG_STATE_B_IDLE;
  265. fallthrough;
  266. case OTG_STATE_B_IDLE:
  267. if (otg_ctrl->id == 0)
  268. mvotg->phy.otg->state = OTG_STATE_A_IDLE;
  269. else if (otg_ctrl->b_sess_vld)
  270. mvotg->phy.otg->state = OTG_STATE_B_PERIPHERAL;
  271. break;
  272. case OTG_STATE_B_PERIPHERAL:
  273. if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
  274. mvotg->phy.otg->state = OTG_STATE_B_IDLE;
  275. break;
  276. case OTG_STATE_A_IDLE:
  277. if (otg_ctrl->id)
  278. mvotg->phy.otg->state = OTG_STATE_B_IDLE;
  279. else if (!(otg_ctrl->a_bus_drop) &&
  280. (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
  281. mvotg->phy.otg->state = OTG_STATE_A_WAIT_VRISE;
  282. break;
  283. case OTG_STATE_A_WAIT_VRISE:
  284. if (otg_ctrl->a_vbus_vld)
  285. mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
  286. break;
  287. case OTG_STATE_A_WAIT_BCON:
  288. if (otg_ctrl->id || otg_ctrl->a_bus_drop
  289. || otg_ctrl->a_wait_bcon_timeout) {
  290. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  291. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  292. mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
  293. otg_ctrl->a_bus_req = 0;
  294. } else if (!otg_ctrl->a_vbus_vld) {
  295. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  296. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  297. mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
  298. } else if (otg_ctrl->b_conn) {
  299. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  300. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  301. mvotg->phy.otg->state = OTG_STATE_A_HOST;
  302. }
  303. break;
  304. case OTG_STATE_A_HOST:
  305. if (otg_ctrl->id || !otg_ctrl->b_conn
  306. || otg_ctrl->a_bus_drop)
  307. mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
  308. else if (!otg_ctrl->a_vbus_vld)
  309. mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
  310. break;
  311. case OTG_STATE_A_WAIT_VFALL:
  312. if (otg_ctrl->id
  313. || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
  314. || otg_ctrl->a_bus_req)
  315. mvotg->phy.otg->state = OTG_STATE_A_IDLE;
  316. break;
  317. case OTG_STATE_A_VBUS_ERR:
  318. if (otg_ctrl->id || otg_ctrl->a_clr_err
  319. || otg_ctrl->a_bus_drop) {
  320. otg_ctrl->a_clr_err = 0;
  321. mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
  322. }
  323. break;
  324. default:
  325. break;
  326. }
  327. }
  328. static void mv_otg_work(struct work_struct *work)
  329. {
  330. struct mv_otg *mvotg;
  331. struct usb_otg *otg;
  332. int old_state;
  333. mvotg = container_of(to_delayed_work(work), struct mv_otg, work);
  334. run:
  335. /* work queue is single thread, or we need spin_lock to protect */
  336. otg = mvotg->phy.otg;
  337. old_state = otg->state;
  338. if (!mvotg->active)
  339. return;
  340. mv_otg_update_inputs(mvotg);
  341. mv_otg_update_state(mvotg);
  342. if (old_state != mvotg->phy.otg->state) {
  343. dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
  344. state_string[old_state],
  345. state_string[mvotg->phy.otg->state]);
  346. switch (mvotg->phy.otg->state) {
  347. case OTG_STATE_B_IDLE:
  348. otg->default_a = 0;
  349. if (old_state == OTG_STATE_B_PERIPHERAL)
  350. mv_otg_start_periphrals(mvotg, 0);
  351. mv_otg_reset(mvotg);
  352. mv_otg_disable(mvotg);
  353. usb_phy_set_event(&mvotg->phy, USB_EVENT_NONE);
  354. break;
  355. case OTG_STATE_B_PERIPHERAL:
  356. mv_otg_enable(mvotg);
  357. mv_otg_start_periphrals(mvotg, 1);
  358. usb_phy_set_event(&mvotg->phy, USB_EVENT_ENUMERATED);
  359. break;
  360. case OTG_STATE_A_IDLE:
  361. otg->default_a = 1;
  362. mv_otg_enable(mvotg);
  363. if (old_state == OTG_STATE_A_WAIT_VFALL)
  364. mv_otg_start_host(mvotg, 0);
  365. mv_otg_reset(mvotg);
  366. break;
  367. case OTG_STATE_A_WAIT_VRISE:
  368. mv_otg_set_vbus(otg, 1);
  369. break;
  370. case OTG_STATE_A_WAIT_BCON:
  371. if (old_state != OTG_STATE_A_HOST)
  372. mv_otg_start_host(mvotg, 1);
  373. mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
  374. T_A_WAIT_BCON);
  375. /*
  376. * Now, we directly enter A_HOST. So set b_conn = 1
  377. * here. In fact, it need host driver to notify us.
  378. */
  379. mvotg->otg_ctrl.b_conn = 1;
  380. break;
  381. case OTG_STATE_A_HOST:
  382. break;
  383. case OTG_STATE_A_WAIT_VFALL:
  384. /*
  385. * Now, we has exited A_HOST. So set b_conn = 0
  386. * here. In fact, it need host driver to notify us.
  387. */
  388. mvotg->otg_ctrl.b_conn = 0;
  389. mv_otg_set_vbus(otg, 0);
  390. break;
  391. case OTG_STATE_A_VBUS_ERR:
  392. break;
  393. default:
  394. break;
  395. }
  396. goto run;
  397. }
  398. }
  399. static irqreturn_t mv_otg_irq(int irq, void *dev)
  400. {
  401. struct mv_otg *mvotg = dev;
  402. u32 otgsc;
  403. otgsc = readl(&mvotg->op_regs->otgsc);
  404. writel(otgsc, &mvotg->op_regs->otgsc);
  405. /*
  406. * if we have vbus, then the vbus detection for B-device
  407. * will be done by mv_otg_inputs_irq().
  408. */
  409. if (mvotg->pdata->vbus)
  410. if ((otgsc & OTGSC_STS_USB_ID) &&
  411. !(otgsc & OTGSC_INTSTS_USB_ID))
  412. return IRQ_NONE;
  413. if ((otgsc & mvotg->irq_status) == 0)
  414. return IRQ_NONE;
  415. mv_otg_run_state_machine(mvotg, 0);
  416. return IRQ_HANDLED;
  417. }
  418. static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
  419. {
  420. struct mv_otg *mvotg = dev;
  421. /* The clock may disabled at this time */
  422. if (!mvotg->active) {
  423. mv_otg_enable(mvotg);
  424. mv_otg_init_irq(mvotg);
  425. }
  426. mv_otg_run_state_machine(mvotg, 0);
  427. return IRQ_HANDLED;
  428. }
  429. static ssize_t
  430. a_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
  431. {
  432. struct mv_otg *mvotg = dev_get_drvdata(dev);
  433. return scnprintf(buf, PAGE_SIZE, "%d\n",
  434. mvotg->otg_ctrl.a_bus_req);
  435. }
  436. static ssize_t
  437. a_bus_req_store(struct device *dev, struct device_attribute *attr,
  438. const char *buf, size_t count)
  439. {
  440. struct mv_otg *mvotg = dev_get_drvdata(dev);
  441. if (count > 2)
  442. return -1;
  443. /* We will use this interface to change to A device */
  444. if (mvotg->phy.otg->state != OTG_STATE_B_IDLE
  445. && mvotg->phy.otg->state != OTG_STATE_A_IDLE)
  446. return -1;
  447. /* The clock may disabled and we need to set irq for ID detected */
  448. mv_otg_enable(mvotg);
  449. mv_otg_init_irq(mvotg);
  450. if (buf[0] == '1') {
  451. mvotg->otg_ctrl.a_bus_req = 1;
  452. mvotg->otg_ctrl.a_bus_drop = 0;
  453. dev_dbg(&mvotg->pdev->dev,
  454. "User request: a_bus_req = 1\n");
  455. if (spin_trylock(&mvotg->wq_lock)) {
  456. mv_otg_run_state_machine(mvotg, 0);
  457. spin_unlock(&mvotg->wq_lock);
  458. }
  459. }
  460. return count;
  461. }
  462. static DEVICE_ATTR_RW(a_bus_req);
  463. static ssize_t
  464. a_clr_err_store(struct device *dev, struct device_attribute *attr,
  465. const char *buf, size_t count)
  466. {
  467. struct mv_otg *mvotg = dev_get_drvdata(dev);
  468. if (!mvotg->phy.otg->default_a)
  469. return -1;
  470. if (count > 2)
  471. return -1;
  472. if (buf[0] == '1') {
  473. mvotg->otg_ctrl.a_clr_err = 1;
  474. dev_dbg(&mvotg->pdev->dev,
  475. "User request: a_clr_err = 1\n");
  476. }
  477. if (spin_trylock(&mvotg->wq_lock)) {
  478. mv_otg_run_state_machine(mvotg, 0);
  479. spin_unlock(&mvotg->wq_lock);
  480. }
  481. return count;
  482. }
  483. static DEVICE_ATTR_WO(a_clr_err);
  484. static ssize_t
  485. a_bus_drop_show(struct device *dev, struct device_attribute *attr,
  486. char *buf)
  487. {
  488. struct mv_otg *mvotg = dev_get_drvdata(dev);
  489. return scnprintf(buf, PAGE_SIZE, "%d\n",
  490. mvotg->otg_ctrl.a_bus_drop);
  491. }
  492. static ssize_t
  493. a_bus_drop_store(struct device *dev, struct device_attribute *attr,
  494. const char *buf, size_t count)
  495. {
  496. struct mv_otg *mvotg = dev_get_drvdata(dev);
  497. if (!mvotg->phy.otg->default_a)
  498. return -1;
  499. if (count > 2)
  500. return -1;
  501. if (buf[0] == '0') {
  502. mvotg->otg_ctrl.a_bus_drop = 0;
  503. dev_dbg(&mvotg->pdev->dev,
  504. "User request: a_bus_drop = 0\n");
  505. } else if (buf[0] == '1') {
  506. mvotg->otg_ctrl.a_bus_drop = 1;
  507. mvotg->otg_ctrl.a_bus_req = 0;
  508. dev_dbg(&mvotg->pdev->dev,
  509. "User request: a_bus_drop = 1\n");
  510. dev_dbg(&mvotg->pdev->dev,
  511. "User request: and a_bus_req = 0\n");
  512. }
  513. if (spin_trylock(&mvotg->wq_lock)) {
  514. mv_otg_run_state_machine(mvotg, 0);
  515. spin_unlock(&mvotg->wq_lock);
  516. }
  517. return count;
  518. }
  519. static DEVICE_ATTR_RW(a_bus_drop);
  520. static struct attribute *inputs_attrs[] = {
  521. &dev_attr_a_bus_req.attr,
  522. &dev_attr_a_clr_err.attr,
  523. &dev_attr_a_bus_drop.attr,
  524. NULL,
  525. };
  526. static const struct attribute_group inputs_attr_group = {
  527. .name = "inputs",
  528. .attrs = inputs_attrs,
  529. };
  530. static const struct attribute_group *mv_otg_groups[] = {
  531. &inputs_attr_group,
  532. NULL,
  533. };
  534. static int mv_otg_remove(struct platform_device *pdev)
  535. {
  536. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  537. if (mvotg->qwork) {
  538. flush_workqueue(mvotg->qwork);
  539. destroy_workqueue(mvotg->qwork);
  540. }
  541. mv_otg_disable(mvotg);
  542. usb_remove_phy(&mvotg->phy);
  543. return 0;
  544. }
  545. static int mv_otg_probe(struct platform_device *pdev)
  546. {
  547. struct mv_usb_platform_data *pdata = dev_get_platdata(&pdev->dev);
  548. struct mv_otg *mvotg;
  549. struct usb_otg *otg;
  550. struct resource *r;
  551. int retval = 0, i;
  552. if (pdata == NULL) {
  553. dev_err(&pdev->dev, "failed to get platform data\n");
  554. return -ENODEV;
  555. }
  556. mvotg = devm_kzalloc(&pdev->dev, sizeof(*mvotg), GFP_KERNEL);
  557. if (!mvotg)
  558. return -ENOMEM;
  559. otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
  560. if (!otg)
  561. return -ENOMEM;
  562. platform_set_drvdata(pdev, mvotg);
  563. mvotg->pdev = pdev;
  564. mvotg->pdata = pdata;
  565. mvotg->clk = devm_clk_get(&pdev->dev, NULL);
  566. if (IS_ERR(mvotg->clk))
  567. return PTR_ERR(mvotg->clk);
  568. mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
  569. if (!mvotg->qwork) {
  570. dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
  571. return -ENOMEM;
  572. }
  573. INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
  574. /* OTG common part */
  575. mvotg->pdev = pdev;
  576. mvotg->phy.dev = &pdev->dev;
  577. mvotg->phy.otg = otg;
  578. mvotg->phy.label = driver_name;
  579. otg->state = OTG_STATE_UNDEFINED;
  580. otg->usb_phy = &mvotg->phy;
  581. otg->set_host = mv_otg_set_host;
  582. otg->set_peripheral = mv_otg_set_peripheral;
  583. otg->set_vbus = mv_otg_set_vbus;
  584. for (i = 0; i < OTG_TIMER_NUM; i++)
  585. timer_setup(&mvotg->otg_ctrl.timer[i],
  586. mv_otg_timer_await_bcon, 0);
  587. r = platform_get_resource_byname(mvotg->pdev,
  588. IORESOURCE_MEM, "phyregs");
  589. if (r == NULL) {
  590. dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
  591. retval = -ENODEV;
  592. goto err_destroy_workqueue;
  593. }
  594. mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  595. if (mvotg->phy_regs == NULL) {
  596. dev_err(&pdev->dev, "failed to map phy I/O memory\n");
  597. retval = -EFAULT;
  598. goto err_destroy_workqueue;
  599. }
  600. r = platform_get_resource_byname(mvotg->pdev,
  601. IORESOURCE_MEM, "capregs");
  602. if (r == NULL) {
  603. dev_err(&pdev->dev, "no I/O memory resource defined\n");
  604. retval = -ENODEV;
  605. goto err_destroy_workqueue;
  606. }
  607. mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  608. if (mvotg->cap_regs == NULL) {
  609. dev_err(&pdev->dev, "failed to map I/O memory\n");
  610. retval = -EFAULT;
  611. goto err_destroy_workqueue;
  612. }
  613. /* we will acces controller register, so enable the udc controller */
  614. retval = mv_otg_enable_internal(mvotg);
  615. if (retval) {
  616. dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
  617. goto err_destroy_workqueue;
  618. }
  619. mvotg->op_regs =
  620. (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
  621. + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
  622. if (pdata->id) {
  623. retval = devm_request_threaded_irq(&pdev->dev, pdata->id->irq,
  624. NULL, mv_otg_inputs_irq,
  625. IRQF_ONESHOT, "id", mvotg);
  626. if (retval) {
  627. dev_info(&pdev->dev,
  628. "Failed to request irq for ID\n");
  629. pdata->id = NULL;
  630. }
  631. }
  632. if (pdata->vbus) {
  633. mvotg->clock_gating = 1;
  634. retval = devm_request_threaded_irq(&pdev->dev, pdata->vbus->irq,
  635. NULL, mv_otg_inputs_irq,
  636. IRQF_ONESHOT, "vbus", mvotg);
  637. if (retval) {
  638. dev_info(&pdev->dev,
  639. "Failed to request irq for VBUS, "
  640. "disable clock gating\n");
  641. mvotg->clock_gating = 0;
  642. pdata->vbus = NULL;
  643. }
  644. }
  645. if (pdata->disable_otg_clock_gating)
  646. mvotg->clock_gating = 0;
  647. mv_otg_reset(mvotg);
  648. mv_otg_init_irq(mvotg);
  649. r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
  650. if (r == NULL) {
  651. dev_err(&pdev->dev, "no IRQ resource defined\n");
  652. retval = -ENODEV;
  653. goto err_disable_clk;
  654. }
  655. mvotg->irq = r->start;
  656. if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED,
  657. driver_name, mvotg)) {
  658. dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
  659. mvotg->irq);
  660. mvotg->irq = 0;
  661. retval = -ENODEV;
  662. goto err_disable_clk;
  663. }
  664. retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
  665. if (retval < 0) {
  666. dev_err(&pdev->dev, "can't register transceiver, %d\n",
  667. retval);
  668. goto err_disable_clk;
  669. }
  670. spin_lock_init(&mvotg->wq_lock);
  671. if (spin_trylock(&mvotg->wq_lock)) {
  672. mv_otg_run_state_machine(mvotg, 2 * HZ);
  673. spin_unlock(&mvotg->wq_lock);
  674. }
  675. dev_info(&pdev->dev,
  676. "successful probe OTG device %s clock gating.\n",
  677. mvotg->clock_gating ? "with" : "without");
  678. return 0;
  679. err_disable_clk:
  680. mv_otg_disable_internal(mvotg);
  681. err_destroy_workqueue:
  682. flush_workqueue(mvotg->qwork);
  683. destroy_workqueue(mvotg->qwork);
  684. return retval;
  685. }
  686. #ifdef CONFIG_PM
  687. static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
  688. {
  689. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  690. if (mvotg->phy.otg->state != OTG_STATE_B_IDLE) {
  691. dev_info(&pdev->dev,
  692. "OTG state is not B_IDLE, it is %d!\n",
  693. mvotg->phy.otg->state);
  694. return -EAGAIN;
  695. }
  696. if (!mvotg->clock_gating)
  697. mv_otg_disable_internal(mvotg);
  698. return 0;
  699. }
  700. static int mv_otg_resume(struct platform_device *pdev)
  701. {
  702. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  703. u32 otgsc;
  704. if (!mvotg->clock_gating) {
  705. mv_otg_enable_internal(mvotg);
  706. otgsc = readl(&mvotg->op_regs->otgsc);
  707. otgsc |= mvotg->irq_en;
  708. writel(otgsc, &mvotg->op_regs->otgsc);
  709. if (spin_trylock(&mvotg->wq_lock)) {
  710. mv_otg_run_state_machine(mvotg, 0);
  711. spin_unlock(&mvotg->wq_lock);
  712. }
  713. }
  714. return 0;
  715. }
  716. #endif
  717. static struct platform_driver mv_otg_driver = {
  718. .probe = mv_otg_probe,
  719. .remove = mv_otg_remove,
  720. .driver = {
  721. .name = driver_name,
  722. .dev_groups = mv_otg_groups,
  723. },
  724. #ifdef CONFIG_PM
  725. .suspend = mv_otg_suspend,
  726. .resume = mv_otg_resume,
  727. #endif
  728. };
  729. module_platform_driver(mv_otg_driver);