ux500_dma.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/usb/musb/ux500_dma.c
  4. *
  5. * U8500 DMA support code
  6. *
  7. * Copyright (C) 2009 STMicroelectronics
  8. * Copyright (C) 2011 ST-Ericsson SA
  9. * Authors:
  10. * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
  11. * Praveena Nadahally <praveen.nadahally@stericsson.com>
  12. * Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
  13. */
  14. #include <linux/device.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/dmaengine.h>
  19. #include <linux/pfn.h>
  20. #include <linux/sizes.h>
  21. #include <linux/platform_data/usb-musb-ux500.h>
  22. #include "musb_core.h"
  23. static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
  24. "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
  25. static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
  26. "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
  27. struct ux500_dma_channel {
  28. struct dma_channel channel;
  29. struct ux500_dma_controller *controller;
  30. struct musb_hw_ep *hw_ep;
  31. struct dma_chan *dma_chan;
  32. unsigned int cur_len;
  33. dma_cookie_t cookie;
  34. u8 ch_num;
  35. u8 is_tx;
  36. u8 is_allocated;
  37. };
  38. struct ux500_dma_controller {
  39. struct dma_controller controller;
  40. struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
  41. struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
  42. void *private_data;
  43. dma_addr_t phy_base;
  44. };
  45. /* Work function invoked from DMA callback to handle rx transfers. */
  46. static void ux500_dma_callback(void *private_data)
  47. {
  48. struct dma_channel *channel = private_data;
  49. struct ux500_dma_channel *ux500_channel = channel->private_data;
  50. struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
  51. struct musb *musb = hw_ep->musb;
  52. unsigned long flags;
  53. dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
  54. hw_ep->epnum);
  55. spin_lock_irqsave(&musb->lock, flags);
  56. ux500_channel->channel.actual_len = ux500_channel->cur_len;
  57. ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
  58. musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
  59. spin_unlock_irqrestore(&musb->lock, flags);
  60. }
  61. static bool ux500_configure_channel(struct dma_channel *channel,
  62. u16 packet_sz, u8 mode,
  63. dma_addr_t dma_addr, u32 len)
  64. {
  65. struct ux500_dma_channel *ux500_channel = channel->private_data;
  66. struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
  67. struct dma_chan *dma_chan = ux500_channel->dma_chan;
  68. struct dma_async_tx_descriptor *dma_desc;
  69. enum dma_transfer_direction direction;
  70. struct scatterlist sg;
  71. struct dma_slave_config slave_conf;
  72. enum dma_slave_buswidth addr_width;
  73. struct musb *musb = ux500_channel->controller->private_data;
  74. dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
  75. ux500_channel->controller->phy_base);
  76. dev_dbg(musb->controller,
  77. "packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
  78. packet_sz, mode, (unsigned long long) dma_addr,
  79. len, ux500_channel->is_tx);
  80. ux500_channel->cur_len = len;
  81. sg_init_table(&sg, 1);
  82. sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
  83. offset_in_page(dma_addr));
  84. sg_dma_address(&sg) = dma_addr;
  85. sg_dma_len(&sg) = len;
  86. direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
  87. addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
  88. DMA_SLAVE_BUSWIDTH_4_BYTES;
  89. slave_conf.direction = direction;
  90. slave_conf.src_addr = usb_fifo_addr;
  91. slave_conf.src_addr_width = addr_width;
  92. slave_conf.src_maxburst = 16;
  93. slave_conf.dst_addr = usb_fifo_addr;
  94. slave_conf.dst_addr_width = addr_width;
  95. slave_conf.dst_maxburst = 16;
  96. slave_conf.device_fc = false;
  97. dmaengine_slave_config(dma_chan, &slave_conf);
  98. dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
  99. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  100. if (!dma_desc)
  101. return false;
  102. dma_desc->callback = ux500_dma_callback;
  103. dma_desc->callback_param = channel;
  104. ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
  105. dma_async_issue_pending(dma_chan);
  106. return true;
  107. }
  108. static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
  109. struct musb_hw_ep *hw_ep, u8 is_tx)
  110. {
  111. struct ux500_dma_controller *controller = container_of(c,
  112. struct ux500_dma_controller, controller);
  113. struct ux500_dma_channel *ux500_channel = NULL;
  114. struct musb *musb = controller->private_data;
  115. u8 ch_num = hw_ep->epnum - 1;
  116. /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
  117. * to specified hw_ep. For example DMA channel 0 can only be allocated
  118. * to hw_ep 1 and 9.
  119. */
  120. if (ch_num > 7)
  121. ch_num -= 8;
  122. if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
  123. return NULL;
  124. ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
  125. &(controller->rx_channel[ch_num]) ;
  126. /* Check if channel is already used. */
  127. if (ux500_channel->is_allocated)
  128. return NULL;
  129. ux500_channel->hw_ep = hw_ep;
  130. ux500_channel->is_allocated = 1;
  131. dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
  132. hw_ep->epnum, is_tx, ch_num);
  133. return &(ux500_channel->channel);
  134. }
  135. static void ux500_dma_channel_release(struct dma_channel *channel)
  136. {
  137. struct ux500_dma_channel *ux500_channel = channel->private_data;
  138. struct musb *musb = ux500_channel->controller->private_data;
  139. dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
  140. if (ux500_channel->is_allocated) {
  141. ux500_channel->is_allocated = 0;
  142. channel->status = MUSB_DMA_STATUS_FREE;
  143. channel->actual_len = 0;
  144. }
  145. }
  146. static int ux500_dma_is_compatible(struct dma_channel *channel,
  147. u16 maxpacket, void *buf, u32 length)
  148. {
  149. if ((maxpacket & 0x3) ||
  150. ((unsigned long int) buf & 0x3) ||
  151. (length < 512) ||
  152. (length & 0x3))
  153. return false;
  154. else
  155. return true;
  156. }
  157. static int ux500_dma_channel_program(struct dma_channel *channel,
  158. u16 packet_sz, u8 mode,
  159. dma_addr_t dma_addr, u32 len)
  160. {
  161. int ret;
  162. BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
  163. channel->status == MUSB_DMA_STATUS_BUSY);
  164. channel->status = MUSB_DMA_STATUS_BUSY;
  165. channel->actual_len = 0;
  166. ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
  167. if (!ret)
  168. channel->status = MUSB_DMA_STATUS_FREE;
  169. return ret;
  170. }
  171. static int ux500_dma_channel_abort(struct dma_channel *channel)
  172. {
  173. struct ux500_dma_channel *ux500_channel = channel->private_data;
  174. struct ux500_dma_controller *controller = ux500_channel->controller;
  175. struct musb *musb = controller->private_data;
  176. void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
  177. u16 csr;
  178. dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
  179. ux500_channel->ch_num, ux500_channel->is_tx);
  180. if (channel->status == MUSB_DMA_STATUS_BUSY) {
  181. if (ux500_channel->is_tx) {
  182. csr = musb_readw(epio, MUSB_TXCSR);
  183. csr &= ~(MUSB_TXCSR_AUTOSET |
  184. MUSB_TXCSR_DMAENAB |
  185. MUSB_TXCSR_DMAMODE);
  186. musb_writew(epio, MUSB_TXCSR, csr);
  187. } else {
  188. csr = musb_readw(epio, MUSB_RXCSR);
  189. csr &= ~(MUSB_RXCSR_AUTOCLEAR |
  190. MUSB_RXCSR_DMAENAB |
  191. MUSB_RXCSR_DMAMODE);
  192. musb_writew(epio, MUSB_RXCSR, csr);
  193. }
  194. dmaengine_terminate_all(ux500_channel->dma_chan);
  195. channel->status = MUSB_DMA_STATUS_FREE;
  196. }
  197. return 0;
  198. }
  199. static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
  200. {
  201. struct ux500_dma_channel *ux500_channel;
  202. struct dma_channel *channel;
  203. u8 ch_num;
  204. for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
  205. channel = &controller->rx_channel[ch_num].channel;
  206. ux500_channel = channel->private_data;
  207. ux500_dma_channel_release(channel);
  208. if (ux500_channel->dma_chan)
  209. dma_release_channel(ux500_channel->dma_chan);
  210. }
  211. for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
  212. channel = &controller->tx_channel[ch_num].channel;
  213. ux500_channel = channel->private_data;
  214. ux500_dma_channel_release(channel);
  215. if (ux500_channel->dma_chan)
  216. dma_release_channel(ux500_channel->dma_chan);
  217. }
  218. }
  219. static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
  220. {
  221. struct ux500_dma_channel *ux500_channel = NULL;
  222. struct musb *musb = controller->private_data;
  223. struct device *dev = musb->controller;
  224. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  225. struct ux500_musb_board_data *data;
  226. struct dma_channel *dma_channel = NULL;
  227. char **chan_names;
  228. u32 ch_num;
  229. u8 dir;
  230. u8 is_tx = 0;
  231. void **param_array;
  232. struct ux500_dma_channel *channel_array;
  233. dma_cap_mask_t mask;
  234. if (!plat) {
  235. dev_err(musb->controller, "No platform data\n");
  236. return -EINVAL;
  237. }
  238. data = plat->board_data;
  239. dma_cap_zero(mask);
  240. dma_cap_set(DMA_SLAVE, mask);
  241. /* Prepare the loop for RX channels */
  242. channel_array = controller->rx_channel;
  243. param_array = data ? data->dma_rx_param_array : NULL;
  244. chan_names = (char **)iep_chan_names;
  245. for (dir = 0; dir < 2; dir++) {
  246. for (ch_num = 0;
  247. ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
  248. ch_num++) {
  249. ux500_channel = &channel_array[ch_num];
  250. ux500_channel->controller = controller;
  251. ux500_channel->ch_num = ch_num;
  252. ux500_channel->is_tx = is_tx;
  253. dma_channel = &(ux500_channel->channel);
  254. dma_channel->private_data = ux500_channel;
  255. dma_channel->status = MUSB_DMA_STATUS_FREE;
  256. dma_channel->max_len = SZ_16M;
  257. ux500_channel->dma_chan =
  258. dma_request_chan(dev, chan_names[ch_num]);
  259. if (IS_ERR(ux500_channel->dma_chan))
  260. ux500_channel->dma_chan =
  261. dma_request_channel(mask,
  262. data ?
  263. data->dma_filter :
  264. NULL,
  265. param_array ?
  266. param_array[ch_num] :
  267. NULL);
  268. if (!ux500_channel->dma_chan) {
  269. ERR("Dma pipe allocation error dir=%d ch=%d\n",
  270. dir, ch_num);
  271. /* Release already allocated channels */
  272. ux500_dma_controller_stop(controller);
  273. return -EBUSY;
  274. }
  275. }
  276. /* Prepare the loop for TX channels */
  277. channel_array = controller->tx_channel;
  278. param_array = data ? data->dma_tx_param_array : NULL;
  279. chan_names = (char **)oep_chan_names;
  280. is_tx = 1;
  281. }
  282. return 0;
  283. }
  284. void ux500_dma_controller_destroy(struct dma_controller *c)
  285. {
  286. struct ux500_dma_controller *controller = container_of(c,
  287. struct ux500_dma_controller, controller);
  288. ux500_dma_controller_stop(controller);
  289. kfree(controller);
  290. }
  291. EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
  292. struct dma_controller *
  293. ux500_dma_controller_create(struct musb *musb, void __iomem *base)
  294. {
  295. struct ux500_dma_controller *controller;
  296. struct platform_device *pdev = to_platform_device(musb->controller);
  297. struct resource *iomem;
  298. int ret;
  299. controller = kzalloc(sizeof(*controller), GFP_KERNEL);
  300. if (!controller)
  301. goto kzalloc_fail;
  302. controller->private_data = musb;
  303. /* Save physical address for DMA controller. */
  304. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  305. if (!iomem) {
  306. dev_err(musb->controller, "no memory resource defined\n");
  307. goto plat_get_fail;
  308. }
  309. controller->phy_base = (dma_addr_t) iomem->start;
  310. controller->controller.channel_alloc = ux500_dma_channel_allocate;
  311. controller->controller.channel_release = ux500_dma_channel_release;
  312. controller->controller.channel_program = ux500_dma_channel_program;
  313. controller->controller.channel_abort = ux500_dma_channel_abort;
  314. controller->controller.is_compatible = ux500_dma_is_compatible;
  315. ret = ux500_dma_controller_start(controller);
  316. if (ret)
  317. goto plat_get_fail;
  318. return &controller->controller;
  319. plat_get_fail:
  320. kfree(controller);
  321. kzalloc_fail:
  322. return NULL;
  323. }
  324. EXPORT_SYMBOL_GPL(ux500_dma_controller_create);