tusb6010_omap.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
  4. *
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/errno.h>
  11. #include <linux/usb.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/slab.h>
  15. #include <linux/dmaengine.h>
  16. #include "musb_core.h"
  17. #include "tusb6010.h"
  18. #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
  19. #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
  20. struct tusb_dma_data {
  21. s8 dmareq;
  22. struct dma_chan *chan;
  23. };
  24. struct tusb_omap_dma_ch {
  25. struct musb *musb;
  26. void __iomem *tbase;
  27. unsigned long phys_offset;
  28. int epnum;
  29. u8 tx;
  30. struct musb_hw_ep *hw_ep;
  31. struct tusb_dma_data *dma_data;
  32. struct tusb_omap_dma *tusb_dma;
  33. dma_addr_t dma_addr;
  34. u32 len;
  35. u16 packet_sz;
  36. u16 transfer_packet_sz;
  37. u32 transfer_len;
  38. u32 completed_len;
  39. };
  40. struct tusb_omap_dma {
  41. struct dma_controller controller;
  42. void __iomem *tbase;
  43. struct tusb_dma_data dma_pool[MAX_DMAREQ];
  44. unsigned multichannel:1;
  45. };
  46. /*
  47. * Allocate dmareq0 to the current channel unless it's already taken
  48. */
  49. static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
  50. {
  51. u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
  52. if (reg != 0) {
  53. dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
  54. chdat->epnum, reg & 0xf);
  55. return -EAGAIN;
  56. }
  57. if (chdat->tx)
  58. reg = (1 << 4) | chdat->epnum;
  59. else
  60. reg = chdat->epnum;
  61. musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
  62. return 0;
  63. }
  64. static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
  65. {
  66. u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
  67. if ((reg & 0xf) != chdat->epnum) {
  68. printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
  69. chdat->epnum, reg & 0xf);
  70. return;
  71. }
  72. musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
  73. }
  74. /*
  75. * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
  76. * musb_gadget.c.
  77. */
  78. static void tusb_omap_dma_cb(void *data)
  79. {
  80. struct dma_channel *channel = (struct dma_channel *)data;
  81. struct tusb_omap_dma_ch *chdat = to_chdat(channel);
  82. struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
  83. struct musb *musb = chdat->musb;
  84. struct device *dev = musb->controller;
  85. struct musb_hw_ep *hw_ep = chdat->hw_ep;
  86. void __iomem *ep_conf = hw_ep->conf;
  87. void __iomem *mbase = musb->mregs;
  88. unsigned long remaining, flags, pio;
  89. spin_lock_irqsave(&musb->lock, flags);
  90. dev_dbg(musb->controller, "ep%i %s dma callback\n",
  91. chdat->epnum, chdat->tx ? "tx" : "rx");
  92. if (chdat->tx)
  93. remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
  94. else
  95. remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
  96. remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
  97. /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
  98. if (unlikely(remaining > chdat->transfer_len)) {
  99. dev_dbg(musb->controller, "Corrupt %s XFR_SIZE: 0x%08lx\n",
  100. chdat->tx ? "tx" : "rx", remaining);
  101. remaining = 0;
  102. }
  103. channel->actual_len = chdat->transfer_len - remaining;
  104. pio = chdat->len - channel->actual_len;
  105. dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
  106. /* Transfer remaining 1 - 31 bytes */
  107. if (pio > 0 && pio < 32) {
  108. u8 *buf;
  109. dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
  110. buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
  111. if (chdat->tx) {
  112. dma_unmap_single(dev, chdat->dma_addr,
  113. chdat->transfer_len,
  114. DMA_TO_DEVICE);
  115. musb_write_fifo(hw_ep, pio, buf);
  116. } else {
  117. dma_unmap_single(dev, chdat->dma_addr,
  118. chdat->transfer_len,
  119. DMA_FROM_DEVICE);
  120. musb_read_fifo(hw_ep, pio, buf);
  121. }
  122. channel->actual_len += pio;
  123. }
  124. if (!tusb_dma->multichannel)
  125. tusb_omap_free_shared_dmareq(chdat);
  126. channel->status = MUSB_DMA_STATUS_FREE;
  127. musb_dma_completion(musb, chdat->epnum, chdat->tx);
  128. /* We must terminate short tx transfers manually by setting TXPKTRDY.
  129. * REVISIT: This same problem may occur with other MUSB dma as well.
  130. * Easy to test with g_ether by pinging the MUSB board with ping -s54.
  131. */
  132. if ((chdat->transfer_len < chdat->packet_sz)
  133. || (chdat->transfer_len % chdat->packet_sz != 0)) {
  134. u16 csr;
  135. if (chdat->tx) {
  136. dev_dbg(musb->controller, "terminating short tx packet\n");
  137. musb_ep_select(mbase, chdat->epnum);
  138. csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
  139. csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
  140. | MUSB_TXCSR_P_WZC_BITS;
  141. musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
  142. }
  143. }
  144. spin_unlock_irqrestore(&musb->lock, flags);
  145. }
  146. static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
  147. u8 rndis_mode, dma_addr_t dma_addr, u32 len)
  148. {
  149. struct tusb_omap_dma_ch *chdat = to_chdat(channel);
  150. struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
  151. struct musb *musb = chdat->musb;
  152. struct device *dev = musb->controller;
  153. struct musb_hw_ep *hw_ep = chdat->hw_ep;
  154. void __iomem *mbase = musb->mregs;
  155. void __iomem *ep_conf = hw_ep->conf;
  156. dma_addr_t fifo_addr = hw_ep->fifo_sync;
  157. u32 dma_remaining;
  158. u16 csr;
  159. u32 psize;
  160. struct tusb_dma_data *dma_data;
  161. struct dma_async_tx_descriptor *dma_desc;
  162. struct dma_slave_config dma_cfg;
  163. enum dma_transfer_direction dma_dir;
  164. u32 port_window;
  165. int ret;
  166. if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
  167. return false;
  168. /*
  169. * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
  170. * register which will cause missed DMA interrupt. We could try to
  171. * use a timer for the callback, but it is unsafe as the XFR_SIZE
  172. * register is corrupt, and we won't know if the DMA worked.
  173. */
  174. if (dma_addr & 0x2)
  175. return false;
  176. /*
  177. * Because of HW issue #10, it seems like mixing sync DMA and async
  178. * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
  179. * using the channel for DMA.
  180. */
  181. if (chdat->tx)
  182. dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
  183. else
  184. dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
  185. dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
  186. if (dma_remaining) {
  187. dev_dbg(musb->controller, "Busy %s dma, not using: %08x\n",
  188. chdat->tx ? "tx" : "rx", dma_remaining);
  189. return false;
  190. }
  191. chdat->transfer_len = len & ~0x1f;
  192. if (len < packet_sz)
  193. chdat->transfer_packet_sz = chdat->transfer_len;
  194. else
  195. chdat->transfer_packet_sz = packet_sz;
  196. dma_data = chdat->dma_data;
  197. if (!tusb_dma->multichannel) {
  198. if (tusb_omap_use_shared_dmareq(chdat) != 0) {
  199. dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
  200. return false;
  201. }
  202. if (dma_data->dmareq < 0) {
  203. /* REVISIT: This should get blocked earlier, happens
  204. * with MSC ErrorRecoveryTest
  205. */
  206. WARN_ON(1);
  207. return false;
  208. }
  209. }
  210. chdat->packet_sz = packet_sz;
  211. chdat->len = len;
  212. channel->actual_len = 0;
  213. chdat->dma_addr = dma_addr;
  214. channel->status = MUSB_DMA_STATUS_BUSY;
  215. /* Since we're recycling dma areas, we need to clean or invalidate */
  216. if (chdat->tx) {
  217. dma_dir = DMA_MEM_TO_DEV;
  218. dma_map_single(dev, phys_to_virt(dma_addr), len,
  219. DMA_TO_DEVICE);
  220. } else {
  221. dma_dir = DMA_DEV_TO_MEM;
  222. dma_map_single(dev, phys_to_virt(dma_addr), len,
  223. DMA_FROM_DEVICE);
  224. }
  225. memset(&dma_cfg, 0, sizeof(dma_cfg));
  226. /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
  227. if ((dma_addr & 0x3) == 0) {
  228. dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  229. dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  230. port_window = 8;
  231. } else {
  232. dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  233. dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  234. port_window = 16;
  235. fifo_addr = hw_ep->fifo_async;
  236. }
  237. dev_dbg(musb->controller,
  238. "ep%i %s dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
  239. chdat->epnum, chdat->tx ? "tx" : "rx", &dma_addr,
  240. chdat->transfer_len, len, chdat->transfer_packet_sz, packet_sz);
  241. dma_cfg.src_addr = fifo_addr;
  242. dma_cfg.dst_addr = fifo_addr;
  243. dma_cfg.src_port_window_size = port_window;
  244. dma_cfg.src_maxburst = port_window;
  245. dma_cfg.dst_port_window_size = port_window;
  246. dma_cfg.dst_maxburst = port_window;
  247. ret = dmaengine_slave_config(dma_data->chan, &dma_cfg);
  248. if (ret) {
  249. dev_err(musb->controller, "DMA slave config failed: %d\n", ret);
  250. return false;
  251. }
  252. dma_desc = dmaengine_prep_slave_single(dma_data->chan, dma_addr,
  253. chdat->transfer_len, dma_dir,
  254. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  255. if (!dma_desc) {
  256. dev_err(musb->controller, "DMA prep_slave_single failed\n");
  257. return false;
  258. }
  259. dma_desc->callback = tusb_omap_dma_cb;
  260. dma_desc->callback_param = channel;
  261. dmaengine_submit(dma_desc);
  262. dev_dbg(musb->controller,
  263. "ep%i %s using %i-bit %s dma from %pad to %pad\n",
  264. chdat->epnum, chdat->tx ? "tx" : "rx",
  265. dma_cfg.src_addr_width * 8,
  266. ((dma_addr & 0x3) == 0) ? "sync" : "async",
  267. (dma_dir == DMA_MEM_TO_DEV) ? &dma_addr : &fifo_addr,
  268. (dma_dir == DMA_MEM_TO_DEV) ? &fifo_addr : &dma_addr);
  269. /*
  270. * Prepare MUSB for DMA transfer
  271. */
  272. musb_ep_select(mbase, chdat->epnum);
  273. if (chdat->tx) {
  274. csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
  275. csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
  276. | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
  277. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  278. musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
  279. } else {
  280. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  281. csr |= MUSB_RXCSR_DMAENAB;
  282. csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
  283. musb_writew(hw_ep->regs, MUSB_RXCSR,
  284. csr | MUSB_RXCSR_P_WZC_BITS);
  285. }
  286. /* Start DMA transfer */
  287. dma_async_issue_pending(dma_data->chan);
  288. if (chdat->tx) {
  289. /* Send transfer_packet_sz packets at a time */
  290. psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
  291. psize &= ~0x7ff;
  292. psize |= chdat->transfer_packet_sz;
  293. musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
  294. musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
  295. TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
  296. } else {
  297. /* Receive transfer_packet_sz packets at a time */
  298. psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
  299. psize &= ~(0x7ff << 16);
  300. psize |= (chdat->transfer_packet_sz << 16);
  301. musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
  302. musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
  303. TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
  304. }
  305. return true;
  306. }
  307. static int tusb_omap_dma_abort(struct dma_channel *channel)
  308. {
  309. struct tusb_omap_dma_ch *chdat = to_chdat(channel);
  310. if (chdat->dma_data)
  311. dmaengine_terminate_all(chdat->dma_data->chan);
  312. channel->status = MUSB_DMA_STATUS_FREE;
  313. return 0;
  314. }
  315. static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
  316. {
  317. u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
  318. int i, dmareq_nr = -1;
  319. for (i = 0; i < MAX_DMAREQ; i++) {
  320. int cur = (reg & (0xf << (i * 5))) >> (i * 5);
  321. if (cur == 0) {
  322. dmareq_nr = i;
  323. break;
  324. }
  325. }
  326. if (dmareq_nr == -1)
  327. return -EAGAIN;
  328. reg |= (chdat->epnum << (dmareq_nr * 5));
  329. if (chdat->tx)
  330. reg |= ((1 << 4) << (dmareq_nr * 5));
  331. musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
  332. chdat->dma_data = &chdat->tusb_dma->dma_pool[dmareq_nr];
  333. return 0;
  334. }
  335. static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
  336. {
  337. u32 reg;
  338. if (!chdat || !chdat->dma_data || chdat->dma_data->dmareq < 0)
  339. return;
  340. reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
  341. reg &= ~(0x1f << (chdat->dma_data->dmareq * 5));
  342. musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
  343. chdat->dma_data = NULL;
  344. }
  345. static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
  346. static struct dma_channel *
  347. tusb_omap_dma_allocate(struct dma_controller *c,
  348. struct musb_hw_ep *hw_ep,
  349. u8 tx)
  350. {
  351. int ret, i;
  352. struct tusb_omap_dma *tusb_dma;
  353. struct musb *musb;
  354. struct dma_channel *channel = NULL;
  355. struct tusb_omap_dma_ch *chdat = NULL;
  356. struct tusb_dma_data *dma_data = NULL;
  357. tusb_dma = container_of(c, struct tusb_omap_dma, controller);
  358. musb = tusb_dma->controller.musb;
  359. /* REVISIT: Why does dmareq5 not work? */
  360. if (hw_ep->epnum == 0) {
  361. dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
  362. return NULL;
  363. }
  364. for (i = 0; i < MAX_DMAREQ; i++) {
  365. struct dma_channel *ch = dma_channel_pool[i];
  366. if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
  367. ch->status = MUSB_DMA_STATUS_FREE;
  368. channel = ch;
  369. chdat = ch->private_data;
  370. break;
  371. }
  372. }
  373. if (!channel)
  374. return NULL;
  375. chdat->musb = tusb_dma->controller.musb;
  376. chdat->tbase = tusb_dma->tbase;
  377. chdat->hw_ep = hw_ep;
  378. chdat->epnum = hw_ep->epnum;
  379. chdat->completed_len = 0;
  380. chdat->tusb_dma = tusb_dma;
  381. if (tx)
  382. chdat->tx = 1;
  383. else
  384. chdat->tx = 0;
  385. channel->max_len = 0x7fffffff;
  386. channel->desired_mode = 0;
  387. channel->actual_len = 0;
  388. if (!chdat->dma_data) {
  389. if (tusb_dma->multichannel) {
  390. ret = tusb_omap_dma_allocate_dmareq(chdat);
  391. if (ret != 0)
  392. goto free_dmareq;
  393. } else {
  394. chdat->dma_data = &tusb_dma->dma_pool[0];
  395. }
  396. }
  397. dma_data = chdat->dma_data;
  398. dev_dbg(musb->controller, "ep%i %s dma: %s dmareq%i\n",
  399. chdat->epnum,
  400. chdat->tx ? "tx" : "rx",
  401. tusb_dma->multichannel ? "shared" : "dedicated",
  402. dma_data->dmareq);
  403. return channel;
  404. free_dmareq:
  405. tusb_omap_dma_free_dmareq(chdat);
  406. dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
  407. channel->status = MUSB_DMA_STATUS_UNKNOWN;
  408. return NULL;
  409. }
  410. static void tusb_omap_dma_release(struct dma_channel *channel)
  411. {
  412. struct tusb_omap_dma_ch *chdat = to_chdat(channel);
  413. struct musb *musb = chdat->musb;
  414. dev_dbg(musb->controller, "Release for ep%i\n", chdat->epnum);
  415. channel->status = MUSB_DMA_STATUS_UNKNOWN;
  416. dmaengine_terminate_sync(chdat->dma_data->chan);
  417. tusb_omap_dma_free_dmareq(chdat);
  418. channel = NULL;
  419. }
  420. void tusb_dma_controller_destroy(struct dma_controller *c)
  421. {
  422. struct tusb_omap_dma *tusb_dma;
  423. int i;
  424. tusb_dma = container_of(c, struct tusb_omap_dma, controller);
  425. for (i = 0; i < MAX_DMAREQ; i++) {
  426. struct dma_channel *ch = dma_channel_pool[i];
  427. if (ch) {
  428. kfree(ch->private_data);
  429. kfree(ch);
  430. }
  431. /* Free up the DMA channels */
  432. if (tusb_dma && tusb_dma->dma_pool[i].chan)
  433. dma_release_channel(tusb_dma->dma_pool[i].chan);
  434. }
  435. kfree(tusb_dma);
  436. }
  437. EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy);
  438. static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
  439. {
  440. struct musb *musb = tusb_dma->controller.musb;
  441. int i;
  442. int ret = 0;
  443. for (i = 0; i < MAX_DMAREQ; i++) {
  444. struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
  445. /*
  446. * Request DMA channels:
  447. * - one channel in case of non multichannel mode
  448. * - MAX_DMAREQ number of channels in multichannel mode
  449. */
  450. if (i == 0 || tusb_dma->multichannel) {
  451. char ch_name[8];
  452. sprintf(ch_name, "dmareq%d", i);
  453. dma_data->chan = dma_request_chan(musb->controller,
  454. ch_name);
  455. if (IS_ERR(dma_data->chan)) {
  456. dev_err(musb->controller,
  457. "Failed to request %s\n", ch_name);
  458. ret = PTR_ERR(dma_data->chan);
  459. goto dma_error;
  460. }
  461. dma_data->dmareq = i;
  462. } else {
  463. dma_data->dmareq = -1;
  464. }
  465. }
  466. return 0;
  467. dma_error:
  468. for (; i >= 0; i--) {
  469. struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
  470. if (dma_data->dmareq >= 0)
  471. dma_release_channel(dma_data->chan);
  472. }
  473. return ret;
  474. }
  475. struct dma_controller *
  476. tusb_dma_controller_create(struct musb *musb, void __iomem *base)
  477. {
  478. void __iomem *tbase = musb->ctrl_base;
  479. struct tusb_omap_dma *tusb_dma;
  480. int i;
  481. /* REVISIT: Get dmareq lines used from board-*.c */
  482. musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
  483. musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
  484. musb_writel(tbase, TUSB_DMA_REQ_CONF,
  485. TUSB_DMA_REQ_CONF_BURST_SIZE(2)
  486. | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
  487. | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
  488. tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
  489. if (!tusb_dma)
  490. goto out;
  491. tusb_dma->controller.musb = musb;
  492. tusb_dma->tbase = musb->ctrl_base;
  493. tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
  494. tusb_dma->controller.channel_release = tusb_omap_dma_release;
  495. tusb_dma->controller.channel_program = tusb_omap_dma_program;
  496. tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
  497. if (musb->tusb_revision >= TUSB_REV_30)
  498. tusb_dma->multichannel = 1;
  499. for (i = 0; i < MAX_DMAREQ; i++) {
  500. struct dma_channel *ch;
  501. struct tusb_omap_dma_ch *chdat;
  502. ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
  503. if (!ch)
  504. goto cleanup;
  505. dma_channel_pool[i] = ch;
  506. chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
  507. if (!chdat)
  508. goto cleanup;
  509. ch->status = MUSB_DMA_STATUS_UNKNOWN;
  510. ch->private_data = chdat;
  511. }
  512. if (tusb_omap_allocate_dma_pool(tusb_dma))
  513. goto cleanup;
  514. return &tusb_dma->controller;
  515. cleanup:
  516. musb_dma_controller_destroy(&tusb_dma->controller);
  517. out:
  518. return NULL;
  519. }
  520. EXPORT_SYMBOL_GPL(tusb_dma_controller_create);