tusb6010.h 8.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
  4. *
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. */
  8. #ifndef __TUSB6010_H__
  9. #define __TUSB6010_H__
  10. /* VLYNQ control register. 32-bit at offset 0x000 */
  11. #define TUSB_VLYNQ_CTRL 0x004
  12. /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
  13. #define TUSB_BASE_OFFSET 0x400
  14. /* FIFO registers 32-bit at offset 0x600 */
  15. #define TUSB_FIFO_BASE 0x600
  16. /* Device System & Control registers. 32-bit at offset 0x800 */
  17. #define TUSB_SYS_REG_BASE 0x800
  18. #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
  19. #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16)
  20. #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15)
  21. #define TUSB_DEV_CONF_SOFT_ID (1 << 1)
  22. #define TUSB_DEV_CONF_ID_SEL (1 << 0)
  23. #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
  24. #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
  25. #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
  26. #define TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP (1 << 23)
  27. #define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19)
  28. #define TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN (1 << 18)
  29. #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17)
  30. #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16)
  31. #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15)
  32. #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14)
  33. #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13)
  34. #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12)
  35. #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11)
  36. #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10)
  37. #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9)
  38. #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7)
  39. #define TUSB_PHY_OTG_CTRL_PD (1 << 6)
  40. #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5)
  41. #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4)
  42. #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3)
  43. #define TUSB_PHY_OTG_CTRL_RESET (1 << 2)
  44. #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1)
  45. #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
  46. /*OTG status register */
  47. #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
  48. #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8)
  49. #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7)
  50. #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6)
  51. #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5)
  52. #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4)
  53. #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3)
  54. #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2)
  55. #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
  56. #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1)
  57. #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
  58. #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
  59. # define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31)
  60. # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
  61. #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
  62. /* PRCM configuration register */
  63. #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
  64. #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24)
  65. #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
  66. /* PRCM management register */
  67. #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
  68. #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25)
  69. #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24)
  70. #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20)
  71. #define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19)
  72. #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18)
  73. #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17)
  74. #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
  75. #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
  76. #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8)
  77. #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4)
  78. #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3)
  79. #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2)
  80. #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1)
  81. #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
  82. /* Wake-up source clear and mask registers */
  83. #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
  84. #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
  85. #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
  86. #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
  87. #define TUSB_PRCM_WGPIO_7 (1 << 12)
  88. #define TUSB_PRCM_WGPIO_6 (1 << 11)
  89. #define TUSB_PRCM_WGPIO_5 (1 << 10)
  90. #define TUSB_PRCM_WGPIO_4 (1 << 9)
  91. #define TUSB_PRCM_WGPIO_3 (1 << 8)
  92. #define TUSB_PRCM_WGPIO_2 (1 << 7)
  93. #define TUSB_PRCM_WGPIO_1 (1 << 6)
  94. #define TUSB_PRCM_WGPIO_0 (1 << 5)
  95. #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */
  96. #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */
  97. #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */
  98. #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */
  99. #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
  100. #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
  101. #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
  102. #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
  103. #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
  104. #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
  105. #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
  106. #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
  107. #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
  108. #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
  109. #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
  110. #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
  111. #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
  112. #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
  113. #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
  114. #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
  115. #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
  116. /* NOR flash interrupt source registers */
  117. #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
  118. #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
  119. #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
  120. #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
  121. #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24)
  122. #define TUSB_INT_SRC_USB_IP_CORE (1 << 17)
  123. #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16)
  124. #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15)
  125. #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14)
  126. #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13)
  127. #define TUSB_INT_SRC_DEV_READY (1 << 12)
  128. #define TUSB_INT_SRC_USB_IP_TX (1 << 9)
  129. #define TUSB_INT_SRC_USB_IP_RX (1 << 8)
  130. #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7)
  131. #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6)
  132. #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5)
  133. #define TUSB_INT_SRC_USB_IP_CONN (1 << 4)
  134. #define TUSB_INT_SRC_USB_IP_SOF (1 << 3)
  135. #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2)
  136. #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1)
  137. #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
  138. /* NOR flash interrupt registers reserved bits. Must be written as 0 */
  139. #define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17)
  140. #define TUSB_INT_MASK_RESERVED_13 (1 << 13)
  141. #define TUSB_INT_MASK_RESERVED_8 (0xf << 8)
  142. #define TUSB_INT_SRC_RESERVED_26 (0x1f << 26)
  143. #define TUSB_INT_SRC_RESERVED_18 (0x3f << 18)
  144. #define TUSB_INT_SRC_RESERVED_10 (0x03 << 10)
  145. /* Reserved bits for NOR flash interrupt mask and clear register */
  146. #define TUSB_INT_MASK_RESERVED_BITS (TUSB_INT_MASK_RESERVED_17 | \
  147. TUSB_INT_MASK_RESERVED_13 | \
  148. TUSB_INT_MASK_RESERVED_8)
  149. /* Reserved bits for NOR flash interrupt status register */
  150. #define TUSB_INT_SRC_RESERVED_BITS (TUSB_INT_SRC_RESERVED_26 | \
  151. TUSB_INT_SRC_RESERVED_18 | \
  152. TUSB_INT_SRC_RESERVED_10)
  153. #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
  154. #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
  155. #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
  156. #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
  157. #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
  158. #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
  159. /* Offsets from each ep base register */
  160. #define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */
  161. #define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */
  162. #define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188
  163. #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
  164. #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
  165. #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
  166. /* Device System & Control register bitfields */
  167. #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18)
  168. #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
  169. #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16)
  170. #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
  171. #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
  172. #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20)
  173. #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16)
  174. #define TUSB_EP0_CONFIG_SW_EN (1 << 8)
  175. #define TUSB_EP0_CONFIG_DIR_TX (1 << 7)
  176. #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
  177. #define TUSB_EP_CONFIG_SW_EN (1 << 31)
  178. #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
  179. #define TUSB_PROD_TEST_RESET_VAL 0xa596
  180. #define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20)
  181. #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
  182. #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
  183. #define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf)
  184. #define TUSB_DIDR1_HI_REV_20 0
  185. #define TUSB_DIDR1_HI_REV_30 1
  186. #define TUSB_DIDR1_HI_REV_31 2
  187. #define TUSB_REV_10 0x10
  188. #define TUSB_REV_20 0x20
  189. #define TUSB_REV_30 0x30
  190. #define TUSB_REV_31 0x31
  191. #endif /* __TUSB6010_H__ */