sunxi.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Allwinner sun4i MUSB Glue Layer
  4. *
  5. * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
  6. *
  7. * Based on code from
  8. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/extcon.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/phy/phy-sun4i-usb.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/soc/sunxi/sunxi_sram.h>
  21. #include <linux/usb/musb.h>
  22. #include <linux/usb/of.h>
  23. #include <linux/usb/usb_phy_generic.h>
  24. #include <linux/workqueue.h>
  25. #include "musb_core.h"
  26. /*
  27. * Register offsets, note sunxi musb has a different layout then most
  28. * musb implementations, we translate the layout in musb_readb & friends.
  29. */
  30. #define SUNXI_MUSB_POWER 0x0040
  31. #define SUNXI_MUSB_DEVCTL 0x0041
  32. #define SUNXI_MUSB_INDEX 0x0042
  33. #define SUNXI_MUSB_VEND0 0x0043
  34. #define SUNXI_MUSB_INTRTX 0x0044
  35. #define SUNXI_MUSB_INTRRX 0x0046
  36. #define SUNXI_MUSB_INTRTXE 0x0048
  37. #define SUNXI_MUSB_INTRRXE 0x004a
  38. #define SUNXI_MUSB_INTRUSB 0x004c
  39. #define SUNXI_MUSB_INTRUSBE 0x0050
  40. #define SUNXI_MUSB_FRAME 0x0054
  41. #define SUNXI_MUSB_TXFIFOSZ 0x0090
  42. #define SUNXI_MUSB_TXFIFOADD 0x0092
  43. #define SUNXI_MUSB_RXFIFOSZ 0x0094
  44. #define SUNXI_MUSB_RXFIFOADD 0x0096
  45. #define SUNXI_MUSB_FADDR 0x0098
  46. #define SUNXI_MUSB_TXFUNCADDR 0x0098
  47. #define SUNXI_MUSB_TXHUBADDR 0x009a
  48. #define SUNXI_MUSB_TXHUBPORT 0x009b
  49. #define SUNXI_MUSB_RXFUNCADDR 0x009c
  50. #define SUNXI_MUSB_RXHUBADDR 0x009e
  51. #define SUNXI_MUSB_RXHUBPORT 0x009f
  52. #define SUNXI_MUSB_CONFIGDATA 0x00c0
  53. /* VEND0 bits */
  54. #define SUNXI_MUSB_VEND0_PIO_MODE 0
  55. /* flags */
  56. #define SUNXI_MUSB_FL_ENABLED 0
  57. #define SUNXI_MUSB_FL_HOSTMODE 1
  58. #define SUNXI_MUSB_FL_HOSTMODE_PEND 2
  59. #define SUNXI_MUSB_FL_VBUS_ON 3
  60. #define SUNXI_MUSB_FL_PHY_ON 4
  61. #define SUNXI_MUSB_FL_HAS_SRAM 5
  62. #define SUNXI_MUSB_FL_HAS_RESET 6
  63. #define SUNXI_MUSB_FL_NO_CONFIGDATA 7
  64. #define SUNXI_MUSB_FL_PHY_MODE_PEND 8
  65. /* Our read/write methods need access and do not get passed in a musb ref :| */
  66. static struct musb *sunxi_musb;
  67. struct sunxi_glue {
  68. struct device *dev;
  69. struct musb *musb;
  70. struct platform_device *musb_pdev;
  71. struct clk *clk;
  72. struct reset_control *rst;
  73. struct phy *phy;
  74. struct platform_device *usb_phy;
  75. struct usb_phy *xceiv;
  76. enum phy_mode phy_mode;
  77. unsigned long flags;
  78. struct work_struct work;
  79. struct extcon_dev *extcon;
  80. struct notifier_block host_nb;
  81. };
  82. /* phy_power_on / off may sleep, so we use a workqueue */
  83. static void sunxi_musb_work(struct work_struct *work)
  84. {
  85. struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
  86. bool vbus_on, phy_on;
  87. if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
  88. return;
  89. if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
  90. struct musb *musb = glue->musb;
  91. unsigned long flags;
  92. u8 devctl;
  93. spin_lock_irqsave(&musb->lock, flags);
  94. devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
  95. if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
  96. set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
  97. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  98. MUSB_HST_MODE(musb);
  99. devctl |= MUSB_DEVCTL_SESSION;
  100. } else {
  101. clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
  102. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  103. MUSB_DEV_MODE(musb);
  104. devctl &= ~MUSB_DEVCTL_SESSION;
  105. }
  106. writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
  107. spin_unlock_irqrestore(&musb->lock, flags);
  108. }
  109. vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
  110. phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
  111. if (phy_on != vbus_on) {
  112. if (vbus_on) {
  113. phy_power_on(glue->phy);
  114. set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
  115. } else {
  116. phy_power_off(glue->phy);
  117. clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
  118. }
  119. }
  120. if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags))
  121. phy_set_mode(glue->phy, glue->phy_mode);
  122. }
  123. static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
  124. {
  125. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  126. if (is_on) {
  127. set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
  128. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  129. } else {
  130. clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
  131. }
  132. schedule_work(&glue->work);
  133. }
  134. static void sunxi_musb_pre_root_reset_end(struct musb *musb)
  135. {
  136. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  137. sun4i_usb_phy_set_squelch_detect(glue->phy, false);
  138. }
  139. static void sunxi_musb_post_root_reset_end(struct musb *musb)
  140. {
  141. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  142. sun4i_usb_phy_set_squelch_detect(glue->phy, true);
  143. }
  144. static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
  145. {
  146. struct musb *musb = __hci;
  147. unsigned long flags;
  148. spin_lock_irqsave(&musb->lock, flags);
  149. musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
  150. if (musb->int_usb)
  151. writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
  152. if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
  153. /* ep0 FADDR must be 0 when (re)entering peripheral mode */
  154. musb_ep_select(musb->mregs, 0);
  155. musb_writeb(musb->mregs, MUSB_FADDR, 0);
  156. }
  157. musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
  158. if (musb->int_tx)
  159. writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
  160. musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
  161. if (musb->int_rx)
  162. writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
  163. musb_interrupt(musb);
  164. spin_unlock_irqrestore(&musb->lock, flags);
  165. return IRQ_HANDLED;
  166. }
  167. static int sunxi_musb_host_notifier(struct notifier_block *nb,
  168. unsigned long event, void *ptr)
  169. {
  170. struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
  171. if (event)
  172. set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
  173. else
  174. clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
  175. set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
  176. schedule_work(&glue->work);
  177. return NOTIFY_DONE;
  178. }
  179. static int sunxi_musb_init(struct musb *musb)
  180. {
  181. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  182. int ret;
  183. sunxi_musb = musb;
  184. musb->phy = glue->phy;
  185. musb->xceiv = glue->xceiv;
  186. if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
  187. ret = sunxi_sram_claim(musb->controller->parent);
  188. if (ret)
  189. return ret;
  190. }
  191. ret = clk_prepare_enable(glue->clk);
  192. if (ret)
  193. goto error_sram_release;
  194. if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
  195. ret = reset_control_deassert(glue->rst);
  196. if (ret)
  197. goto error_clk_disable;
  198. }
  199. writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
  200. /* Register notifier before calling phy_init() */
  201. ret = devm_extcon_register_notifier(glue->dev, glue->extcon,
  202. EXTCON_USB_HOST, &glue->host_nb);
  203. if (ret)
  204. goto error_reset_assert;
  205. ret = phy_init(glue->phy);
  206. if (ret)
  207. goto error_reset_assert;
  208. musb->isr = sunxi_musb_interrupt;
  209. /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
  210. pm_runtime_get(musb->controller);
  211. return 0;
  212. error_reset_assert:
  213. if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
  214. reset_control_assert(glue->rst);
  215. error_clk_disable:
  216. clk_disable_unprepare(glue->clk);
  217. error_sram_release:
  218. if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
  219. sunxi_sram_release(musb->controller->parent);
  220. return ret;
  221. }
  222. static int sunxi_musb_exit(struct musb *musb)
  223. {
  224. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  225. pm_runtime_put(musb->controller);
  226. cancel_work_sync(&glue->work);
  227. if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
  228. phy_power_off(glue->phy);
  229. phy_exit(glue->phy);
  230. if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
  231. reset_control_assert(glue->rst);
  232. clk_disable_unprepare(glue->clk);
  233. if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
  234. sunxi_sram_release(musb->controller->parent);
  235. devm_usb_put_phy(glue->dev, glue->xceiv);
  236. return 0;
  237. }
  238. static void sunxi_musb_enable(struct musb *musb)
  239. {
  240. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  241. glue->musb = musb;
  242. /* musb_core does not call us in a balanced manner */
  243. if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
  244. return;
  245. schedule_work(&glue->work);
  246. }
  247. static void sunxi_musb_disable(struct musb *musb)
  248. {
  249. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  250. clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
  251. }
  252. static struct dma_controller *
  253. sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base)
  254. {
  255. return NULL;
  256. }
  257. static void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
  258. {
  259. }
  260. static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
  261. {
  262. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  263. enum phy_mode new_mode;
  264. switch (mode) {
  265. case MUSB_HOST:
  266. new_mode = PHY_MODE_USB_HOST;
  267. break;
  268. case MUSB_PERIPHERAL:
  269. new_mode = PHY_MODE_USB_DEVICE;
  270. break;
  271. case MUSB_OTG:
  272. new_mode = PHY_MODE_USB_OTG;
  273. break;
  274. default:
  275. dev_err(musb->controller->parent,
  276. "Error requested mode not supported by this kernel\n");
  277. return -EINVAL;
  278. }
  279. if (glue->phy_mode == new_mode)
  280. return 0;
  281. if (musb->port_mode != MUSB_OTG) {
  282. dev_err(musb->controller->parent,
  283. "Error changing modes is only supported in dual role mode\n");
  284. return -EINVAL;
  285. }
  286. if (musb->port1_status & USB_PORT_STAT_ENABLE)
  287. musb_root_disconnect(musb);
  288. /*
  289. * phy_set_mode may sleep, and we're called with a spinlock held,
  290. * so let sunxi_musb_work deal with it.
  291. */
  292. glue->phy_mode = new_mode;
  293. set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
  294. schedule_work(&glue->work);
  295. return 0;
  296. }
  297. static int sunxi_musb_recover(struct musb *musb)
  298. {
  299. struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
  300. /*
  301. * Schedule a phy_set_mode with the current glue->phy_mode value,
  302. * this will force end the current session.
  303. */
  304. set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
  305. schedule_work(&glue->work);
  306. return 0;
  307. }
  308. /*
  309. * sunxi musb register layout
  310. * 0x00 - 0x17 fifo regs, 1 long per fifo
  311. * 0x40 - 0x57 generic control regs (power - frame)
  312. * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
  313. * 0x90 - 0x97 fifo control regs (indexed)
  314. * 0x98 - 0x9f multipoint / busctl regs (indexed)
  315. * 0xc0 configdata reg
  316. */
  317. static u32 sunxi_musb_fifo_offset(u8 epnum)
  318. {
  319. return (epnum * 4);
  320. }
  321. static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
  322. {
  323. WARN_ONCE(offset != 0,
  324. "sunxi_musb_ep_offset called with non 0 offset\n");
  325. return 0x80; /* indexed, so ignore epnum */
  326. }
  327. static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
  328. {
  329. return SUNXI_MUSB_TXFUNCADDR + offset;
  330. }
  331. static u8 sunxi_musb_readb(void __iomem *addr, u32 offset)
  332. {
  333. struct sunxi_glue *glue;
  334. if (addr == sunxi_musb->mregs) {
  335. /* generic control or fifo control reg access */
  336. switch (offset) {
  337. case MUSB_FADDR:
  338. return readb(addr + SUNXI_MUSB_FADDR);
  339. case MUSB_POWER:
  340. return readb(addr + SUNXI_MUSB_POWER);
  341. case MUSB_INTRUSB:
  342. return readb(addr + SUNXI_MUSB_INTRUSB);
  343. case MUSB_INTRUSBE:
  344. return readb(addr + SUNXI_MUSB_INTRUSBE);
  345. case MUSB_INDEX:
  346. return readb(addr + SUNXI_MUSB_INDEX);
  347. case MUSB_TESTMODE:
  348. return 0; /* No testmode on sunxi */
  349. case MUSB_DEVCTL:
  350. return readb(addr + SUNXI_MUSB_DEVCTL);
  351. case MUSB_TXFIFOSZ:
  352. return readb(addr + SUNXI_MUSB_TXFIFOSZ);
  353. case MUSB_RXFIFOSZ:
  354. return readb(addr + SUNXI_MUSB_RXFIFOSZ);
  355. case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
  356. glue = dev_get_drvdata(sunxi_musb->controller->parent);
  357. /* A33 saves a reg, and we get to hardcode this */
  358. if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
  359. &glue->flags))
  360. return 0xde;
  361. return readb(addr + SUNXI_MUSB_CONFIGDATA);
  362. /* Offset for these is fixed by sunxi_musb_busctl_offset() */
  363. case SUNXI_MUSB_TXFUNCADDR:
  364. case SUNXI_MUSB_TXHUBADDR:
  365. case SUNXI_MUSB_TXHUBPORT:
  366. case SUNXI_MUSB_RXFUNCADDR:
  367. case SUNXI_MUSB_RXHUBADDR:
  368. case SUNXI_MUSB_RXHUBPORT:
  369. /* multipoint / busctl reg access */
  370. return readb(addr + offset);
  371. default:
  372. dev_err(sunxi_musb->controller->parent,
  373. "Error unknown readb offset %u\n", offset);
  374. return 0;
  375. }
  376. } else if (addr == (sunxi_musb->mregs + 0x80)) {
  377. /* ep control reg access */
  378. /* sunxi has a 2 byte hole before the txtype register */
  379. if (offset >= MUSB_TXTYPE)
  380. offset += 2;
  381. return readb(addr + offset);
  382. }
  383. dev_err(sunxi_musb->controller->parent,
  384. "Error unknown readb at 0x%x bytes offset\n",
  385. (int)(addr - sunxi_musb->mregs));
  386. return 0;
  387. }
  388. static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
  389. {
  390. if (addr == sunxi_musb->mregs) {
  391. /* generic control or fifo control reg access */
  392. switch (offset) {
  393. case MUSB_FADDR:
  394. return writeb(data, addr + SUNXI_MUSB_FADDR);
  395. case MUSB_POWER:
  396. return writeb(data, addr + SUNXI_MUSB_POWER);
  397. case MUSB_INTRUSB:
  398. return writeb(data, addr + SUNXI_MUSB_INTRUSB);
  399. case MUSB_INTRUSBE:
  400. return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
  401. case MUSB_INDEX:
  402. return writeb(data, addr + SUNXI_MUSB_INDEX);
  403. case MUSB_TESTMODE:
  404. if (data)
  405. dev_warn(sunxi_musb->controller->parent,
  406. "sunxi-musb does not have testmode\n");
  407. return;
  408. case MUSB_DEVCTL:
  409. return writeb(data, addr + SUNXI_MUSB_DEVCTL);
  410. case MUSB_TXFIFOSZ:
  411. return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
  412. case MUSB_RXFIFOSZ:
  413. return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
  414. /* Offset for these is fixed by sunxi_musb_busctl_offset() */
  415. case SUNXI_MUSB_TXFUNCADDR:
  416. case SUNXI_MUSB_TXHUBADDR:
  417. case SUNXI_MUSB_TXHUBPORT:
  418. case SUNXI_MUSB_RXFUNCADDR:
  419. case SUNXI_MUSB_RXHUBADDR:
  420. case SUNXI_MUSB_RXHUBPORT:
  421. /* multipoint / busctl reg access */
  422. return writeb(data, addr + offset);
  423. default:
  424. dev_err(sunxi_musb->controller->parent,
  425. "Error unknown writeb offset %u\n", offset);
  426. return;
  427. }
  428. } else if (addr == (sunxi_musb->mregs + 0x80)) {
  429. /* ep control reg access */
  430. if (offset >= MUSB_TXTYPE)
  431. offset += 2;
  432. return writeb(data, addr + offset);
  433. }
  434. dev_err(sunxi_musb->controller->parent,
  435. "Error unknown writeb at 0x%x bytes offset\n",
  436. (int)(addr - sunxi_musb->mregs));
  437. }
  438. static u16 sunxi_musb_readw(void __iomem *addr, u32 offset)
  439. {
  440. if (addr == sunxi_musb->mregs) {
  441. /* generic control or fifo control reg access */
  442. switch (offset) {
  443. case MUSB_INTRTX:
  444. return readw(addr + SUNXI_MUSB_INTRTX);
  445. case MUSB_INTRRX:
  446. return readw(addr + SUNXI_MUSB_INTRRX);
  447. case MUSB_INTRTXE:
  448. return readw(addr + SUNXI_MUSB_INTRTXE);
  449. case MUSB_INTRRXE:
  450. return readw(addr + SUNXI_MUSB_INTRRXE);
  451. case MUSB_FRAME:
  452. return readw(addr + SUNXI_MUSB_FRAME);
  453. case MUSB_TXFIFOADD:
  454. return readw(addr + SUNXI_MUSB_TXFIFOADD);
  455. case MUSB_RXFIFOADD:
  456. return readw(addr + SUNXI_MUSB_RXFIFOADD);
  457. case MUSB_HWVERS:
  458. return 0; /* sunxi musb version is not known */
  459. default:
  460. dev_err(sunxi_musb->controller->parent,
  461. "Error unknown readw offset %u\n", offset);
  462. return 0;
  463. }
  464. } else if (addr == (sunxi_musb->mregs + 0x80)) {
  465. /* ep control reg access */
  466. return readw(addr + offset);
  467. }
  468. dev_err(sunxi_musb->controller->parent,
  469. "Error unknown readw at 0x%x bytes offset\n",
  470. (int)(addr - sunxi_musb->mregs));
  471. return 0;
  472. }
  473. static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
  474. {
  475. if (addr == sunxi_musb->mregs) {
  476. /* generic control or fifo control reg access */
  477. switch (offset) {
  478. case MUSB_INTRTX:
  479. return writew(data, addr + SUNXI_MUSB_INTRTX);
  480. case MUSB_INTRRX:
  481. return writew(data, addr + SUNXI_MUSB_INTRRX);
  482. case MUSB_INTRTXE:
  483. return writew(data, addr + SUNXI_MUSB_INTRTXE);
  484. case MUSB_INTRRXE:
  485. return writew(data, addr + SUNXI_MUSB_INTRRXE);
  486. case MUSB_FRAME:
  487. return writew(data, addr + SUNXI_MUSB_FRAME);
  488. case MUSB_TXFIFOADD:
  489. return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
  490. case MUSB_RXFIFOADD:
  491. return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
  492. default:
  493. dev_err(sunxi_musb->controller->parent,
  494. "Error unknown writew offset %u\n", offset);
  495. return;
  496. }
  497. } else if (addr == (sunxi_musb->mregs + 0x80)) {
  498. /* ep control reg access */
  499. return writew(data, addr + offset);
  500. }
  501. dev_err(sunxi_musb->controller->parent,
  502. "Error unknown writew at 0x%x bytes offset\n",
  503. (int)(addr - sunxi_musb->mregs));
  504. }
  505. static const struct musb_platform_ops sunxi_musb_ops = {
  506. .quirks = MUSB_INDEXED_EP,
  507. .init = sunxi_musb_init,
  508. .exit = sunxi_musb_exit,
  509. .enable = sunxi_musb_enable,
  510. .disable = sunxi_musb_disable,
  511. .fifo_offset = sunxi_musb_fifo_offset,
  512. .ep_offset = sunxi_musb_ep_offset,
  513. .busctl_offset = sunxi_musb_busctl_offset,
  514. .readb = sunxi_musb_readb,
  515. .writeb = sunxi_musb_writeb,
  516. .readw = sunxi_musb_readw,
  517. .writew = sunxi_musb_writew,
  518. .dma_init = sunxi_musb_dma_controller_create,
  519. .dma_exit = sunxi_musb_dma_controller_destroy,
  520. .set_mode = sunxi_musb_set_mode,
  521. .recover = sunxi_musb_recover,
  522. .set_vbus = sunxi_musb_set_vbus,
  523. .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
  524. .post_root_reset_end = sunxi_musb_post_root_reset_end,
  525. };
  526. /* Allwinner OTG supports up to 5 endpoints */
  527. #define SUNXI_MUSB_MAX_EP_NUM 6
  528. #define SUNXI_MUSB_RAM_BITS 11
  529. static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
  530. MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
  531. MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
  532. MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
  533. MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
  534. MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
  535. MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
  536. MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
  537. MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
  538. MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
  539. MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
  540. };
  541. /* H3/V3s OTG supports only 4 endpoints */
  542. #define SUNXI_MUSB_MAX_EP_NUM_H3 5
  543. static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
  544. MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
  545. MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
  546. MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
  547. MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
  548. MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
  549. MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
  550. MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
  551. MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
  552. };
  553. static const struct musb_hdrc_config sunxi_musb_hdrc_config = {
  554. .fifo_cfg = sunxi_musb_mode_cfg,
  555. .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
  556. .multipoint = true,
  557. .dyn_fifo = true,
  558. .num_eps = SUNXI_MUSB_MAX_EP_NUM,
  559. .ram_bits = SUNXI_MUSB_RAM_BITS,
  560. };
  561. static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = {
  562. .fifo_cfg = sunxi_musb_mode_cfg_h3,
  563. .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
  564. .multipoint = true,
  565. .dyn_fifo = true,
  566. .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
  567. .ram_bits = SUNXI_MUSB_RAM_BITS,
  568. };
  569. static int sunxi_musb_probe(struct platform_device *pdev)
  570. {
  571. struct musb_hdrc_platform_data pdata;
  572. struct platform_device_info pinfo;
  573. struct sunxi_glue *glue;
  574. struct device_node *np = pdev->dev.of_node;
  575. int ret;
  576. if (!np) {
  577. dev_err(&pdev->dev, "Error no device tree node found\n");
  578. return -EINVAL;
  579. }
  580. glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
  581. if (!glue)
  582. return -ENOMEM;
  583. memset(&pdata, 0, sizeof(pdata));
  584. switch (usb_get_dr_mode(&pdev->dev)) {
  585. #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
  586. case USB_DR_MODE_HOST:
  587. pdata.mode = MUSB_HOST;
  588. glue->phy_mode = PHY_MODE_USB_HOST;
  589. break;
  590. #endif
  591. #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET
  592. case USB_DR_MODE_PERIPHERAL:
  593. pdata.mode = MUSB_PERIPHERAL;
  594. glue->phy_mode = PHY_MODE_USB_DEVICE;
  595. break;
  596. #endif
  597. #ifdef CONFIG_USB_MUSB_DUAL_ROLE
  598. case USB_DR_MODE_OTG:
  599. pdata.mode = MUSB_OTG;
  600. glue->phy_mode = PHY_MODE_USB_OTG;
  601. break;
  602. #endif
  603. default:
  604. dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
  605. return -EINVAL;
  606. }
  607. pdata.platform_ops = &sunxi_musb_ops;
  608. if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb"))
  609. pdata.config = &sunxi_musb_hdrc_config;
  610. else
  611. pdata.config = &sunxi_musb_hdrc_config_h3;
  612. glue->dev = &pdev->dev;
  613. INIT_WORK(&glue->work, sunxi_musb_work);
  614. glue->host_nb.notifier_call = sunxi_musb_host_notifier;
  615. if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
  616. set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
  617. if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
  618. set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
  619. if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
  620. of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
  621. set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
  622. set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
  623. }
  624. glue->clk = devm_clk_get(&pdev->dev, NULL);
  625. if (IS_ERR(glue->clk)) {
  626. dev_err(&pdev->dev, "Error getting clock: %ld\n",
  627. PTR_ERR(glue->clk));
  628. return PTR_ERR(glue->clk);
  629. }
  630. if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
  631. glue->rst = devm_reset_control_get(&pdev->dev, NULL);
  632. if (IS_ERR(glue->rst)) {
  633. if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
  634. return -EPROBE_DEFER;
  635. dev_err(&pdev->dev, "Error getting reset %ld\n",
  636. PTR_ERR(glue->rst));
  637. return PTR_ERR(glue->rst);
  638. }
  639. }
  640. glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
  641. if (IS_ERR(glue->extcon)) {
  642. if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
  643. return -EPROBE_DEFER;
  644. dev_err(&pdev->dev, "Invalid or missing extcon\n");
  645. return PTR_ERR(glue->extcon);
  646. }
  647. glue->phy = devm_phy_get(&pdev->dev, "usb");
  648. if (IS_ERR(glue->phy)) {
  649. if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
  650. return -EPROBE_DEFER;
  651. dev_err(&pdev->dev, "Error getting phy %ld\n",
  652. PTR_ERR(glue->phy));
  653. return PTR_ERR(glue->phy);
  654. }
  655. glue->usb_phy = usb_phy_generic_register();
  656. if (IS_ERR(glue->usb_phy)) {
  657. dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
  658. PTR_ERR(glue->usb_phy));
  659. return PTR_ERR(glue->usb_phy);
  660. }
  661. glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
  662. if (IS_ERR(glue->xceiv)) {
  663. ret = PTR_ERR(glue->xceiv);
  664. dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
  665. goto err_unregister_usb_phy;
  666. }
  667. platform_set_drvdata(pdev, glue);
  668. memset(&pinfo, 0, sizeof(pinfo));
  669. pinfo.name = "musb-hdrc";
  670. pinfo.id = PLATFORM_DEVID_AUTO;
  671. pinfo.parent = &pdev->dev;
  672. pinfo.fwnode = of_fwnode_handle(pdev->dev.of_node);
  673. pinfo.of_node_reused = true;
  674. pinfo.res = pdev->resource;
  675. pinfo.num_res = pdev->num_resources;
  676. pinfo.data = &pdata;
  677. pinfo.size_data = sizeof(pdata);
  678. glue->musb_pdev = platform_device_register_full(&pinfo);
  679. if (IS_ERR(glue->musb_pdev)) {
  680. ret = PTR_ERR(glue->musb_pdev);
  681. dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
  682. goto err_unregister_usb_phy;
  683. }
  684. return 0;
  685. err_unregister_usb_phy:
  686. usb_phy_generic_unregister(glue->usb_phy);
  687. return ret;
  688. }
  689. static int sunxi_musb_remove(struct platform_device *pdev)
  690. {
  691. struct sunxi_glue *glue = platform_get_drvdata(pdev);
  692. struct platform_device *usb_phy = glue->usb_phy;
  693. platform_device_unregister(glue->musb_pdev);
  694. usb_phy_generic_unregister(usb_phy);
  695. return 0;
  696. }
  697. static const struct of_device_id sunxi_musb_match[] = {
  698. { .compatible = "allwinner,sun4i-a10-musb", },
  699. { .compatible = "allwinner,sun6i-a31-musb", },
  700. { .compatible = "allwinner,sun8i-a33-musb", },
  701. { .compatible = "allwinner,sun8i-h3-musb", },
  702. {}
  703. };
  704. MODULE_DEVICE_TABLE(of, sunxi_musb_match);
  705. static struct platform_driver sunxi_musb_driver = {
  706. .probe = sunxi_musb_probe,
  707. .remove = sunxi_musb_remove,
  708. .driver = {
  709. .name = "musb-sunxi",
  710. .of_match_table = sunxi_musb_match,
  711. },
  712. };
  713. module_platform_driver(sunxi_musb_driver);
  714. MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
  715. MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
  716. MODULE_LICENSE("GPL v2");