musbhsdma.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver - support for Mentor's DMA controller
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2007 by Texas Instruments
  7. */
  8. #include <linux/device.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include "musb_core.h"
  13. #include "musb_dma.h"
  14. #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
  15. (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
  16. #define musb_read_hsdma_addr(mbase, bchannel) \
  17. musb_readl(mbase, \
  18. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
  19. #define musb_write_hsdma_addr(mbase, bchannel, addr) \
  20. musb_writel(mbase, \
  21. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
  22. addr)
  23. #define musb_read_hsdma_count(mbase, bchannel) \
  24. musb_readl(mbase, \
  25. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
  26. #define musb_write_hsdma_count(mbase, bchannel, len) \
  27. musb_writel(mbase, \
  28. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
  29. len)
  30. /* control register (16-bit): */
  31. #define MUSB_HSDMA_ENABLE_SHIFT 0
  32. #define MUSB_HSDMA_TRANSMIT_SHIFT 1
  33. #define MUSB_HSDMA_MODE1_SHIFT 2
  34. #define MUSB_HSDMA_IRQENABLE_SHIFT 3
  35. #define MUSB_HSDMA_ENDPOINT_SHIFT 4
  36. #define MUSB_HSDMA_BUSERROR_SHIFT 8
  37. #define MUSB_HSDMA_BURSTMODE_SHIFT 9
  38. #define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
  39. #define MUSB_HSDMA_BURSTMODE_UNSPEC 0
  40. #define MUSB_HSDMA_BURSTMODE_INCR4 1
  41. #define MUSB_HSDMA_BURSTMODE_INCR8 2
  42. #define MUSB_HSDMA_BURSTMODE_INCR16 3
  43. #define MUSB_HSDMA_CHANNELS 8
  44. struct musb_dma_controller;
  45. struct musb_dma_channel {
  46. struct dma_channel channel;
  47. struct musb_dma_controller *controller;
  48. u32 start_addr;
  49. u32 len;
  50. u16 max_packet_sz;
  51. u8 idx;
  52. u8 epnum;
  53. u8 transmit;
  54. };
  55. struct musb_dma_controller {
  56. struct dma_controller controller;
  57. struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
  58. void *private_data;
  59. void __iomem *base;
  60. u8 channel_count;
  61. u8 used_channels;
  62. int irq;
  63. };
  64. static void dma_channel_release(struct dma_channel *channel);
  65. static void dma_controller_stop(struct musb_dma_controller *controller)
  66. {
  67. struct musb *musb = controller->private_data;
  68. struct dma_channel *channel;
  69. u8 bit;
  70. if (controller->used_channels != 0) {
  71. dev_err(musb->controller,
  72. "Stopping DMA controller while channel active\n");
  73. for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  74. if (controller->used_channels & (1 << bit)) {
  75. channel = &controller->channel[bit].channel;
  76. dma_channel_release(channel);
  77. if (!controller->used_channels)
  78. break;
  79. }
  80. }
  81. }
  82. }
  83. static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
  84. struct musb_hw_ep *hw_ep, u8 transmit)
  85. {
  86. struct musb_dma_controller *controller = container_of(c,
  87. struct musb_dma_controller, controller);
  88. struct musb_dma_channel *musb_channel = NULL;
  89. struct dma_channel *channel = NULL;
  90. u8 bit;
  91. for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  92. if (!(controller->used_channels & (1 << bit))) {
  93. controller->used_channels |= (1 << bit);
  94. musb_channel = &(controller->channel[bit]);
  95. musb_channel->controller = controller;
  96. musb_channel->idx = bit;
  97. musb_channel->epnum = hw_ep->epnum;
  98. musb_channel->transmit = transmit;
  99. channel = &(musb_channel->channel);
  100. channel->private_data = musb_channel;
  101. channel->status = MUSB_DMA_STATUS_FREE;
  102. channel->max_len = 0x100000;
  103. /* Tx => mode 1; Rx => mode 0 */
  104. channel->desired_mode = transmit;
  105. channel->actual_len = 0;
  106. break;
  107. }
  108. }
  109. return channel;
  110. }
  111. static void dma_channel_release(struct dma_channel *channel)
  112. {
  113. struct musb_dma_channel *musb_channel = channel->private_data;
  114. channel->actual_len = 0;
  115. musb_channel->start_addr = 0;
  116. musb_channel->len = 0;
  117. musb_channel->controller->used_channels &=
  118. ~(1 << musb_channel->idx);
  119. channel->status = MUSB_DMA_STATUS_UNKNOWN;
  120. }
  121. static void configure_channel(struct dma_channel *channel,
  122. u16 packet_sz, u8 mode,
  123. dma_addr_t dma_addr, u32 len)
  124. {
  125. struct musb_dma_channel *musb_channel = channel->private_data;
  126. struct musb_dma_controller *controller = musb_channel->controller;
  127. struct musb *musb = controller->private_data;
  128. void __iomem *mbase = controller->base;
  129. u8 bchannel = musb_channel->idx;
  130. u16 csr = 0;
  131. musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
  132. channel, packet_sz, &dma_addr, len, mode);
  133. if (mode) {
  134. csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
  135. BUG_ON(len < packet_sz);
  136. }
  137. csr |= MUSB_HSDMA_BURSTMODE_INCR16
  138. << MUSB_HSDMA_BURSTMODE_SHIFT;
  139. csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
  140. | (1 << MUSB_HSDMA_ENABLE_SHIFT)
  141. | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
  142. | (musb_channel->transmit
  143. ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
  144. : 0);
  145. /* address/count */
  146. musb_write_hsdma_addr(mbase, bchannel, dma_addr);
  147. musb_write_hsdma_count(mbase, bchannel, len);
  148. /* control (this should start things) */
  149. musb_writew(mbase,
  150. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
  151. csr);
  152. }
  153. static int dma_channel_program(struct dma_channel *channel,
  154. u16 packet_sz, u8 mode,
  155. dma_addr_t dma_addr, u32 len)
  156. {
  157. struct musb_dma_channel *musb_channel = channel->private_data;
  158. struct musb_dma_controller *controller = musb_channel->controller;
  159. struct musb *musb = controller->private_data;
  160. musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
  161. musb_channel->epnum,
  162. musb_channel->transmit ? "Tx" : "Rx",
  163. packet_sz, &dma_addr, len, mode);
  164. BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
  165. channel->status == MUSB_DMA_STATUS_BUSY);
  166. /*
  167. * The DMA engine in RTL1.8 and above cannot handle
  168. * DMA addresses that are not aligned to a 4 byte boundary.
  169. * It ends up masking the last two bits of the address
  170. * programmed in DMA_ADDR.
  171. *
  172. * Fail such DMA transfers, so that the backup PIO mode
  173. * can carry out the transfer
  174. */
  175. if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
  176. return false;
  177. channel->actual_len = 0;
  178. musb_channel->start_addr = dma_addr;
  179. musb_channel->len = len;
  180. musb_channel->max_packet_sz = packet_sz;
  181. channel->status = MUSB_DMA_STATUS_BUSY;
  182. configure_channel(channel, packet_sz, mode, dma_addr, len);
  183. return true;
  184. }
  185. static int dma_channel_abort(struct dma_channel *channel)
  186. {
  187. struct musb_dma_channel *musb_channel = channel->private_data;
  188. void __iomem *mbase = musb_channel->controller->base;
  189. struct musb *musb = musb_channel->controller->private_data;
  190. u8 bchannel = musb_channel->idx;
  191. int offset;
  192. u16 csr;
  193. if (channel->status == MUSB_DMA_STATUS_BUSY) {
  194. if (musb_channel->transmit) {
  195. offset = musb->io.ep_offset(musb_channel->epnum,
  196. MUSB_TXCSR);
  197. /*
  198. * The programming guide says that we must clear
  199. * the DMAENAB bit before the DMAMODE bit...
  200. */
  201. csr = musb_readw(mbase, offset);
  202. csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
  203. musb_writew(mbase, offset, csr);
  204. csr &= ~MUSB_TXCSR_DMAMODE;
  205. musb_writew(mbase, offset, csr);
  206. } else {
  207. offset = musb->io.ep_offset(musb_channel->epnum,
  208. MUSB_RXCSR);
  209. csr = musb_readw(mbase, offset);
  210. csr &= ~(MUSB_RXCSR_AUTOCLEAR |
  211. MUSB_RXCSR_DMAENAB |
  212. MUSB_RXCSR_DMAMODE);
  213. musb_writew(mbase, offset, csr);
  214. }
  215. musb_writew(mbase,
  216. MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
  217. 0);
  218. musb_write_hsdma_addr(mbase, bchannel, 0);
  219. musb_write_hsdma_count(mbase, bchannel, 0);
  220. channel->status = MUSB_DMA_STATUS_FREE;
  221. }
  222. return 0;
  223. }
  224. irqreturn_t dma_controller_irq(int irq, void *private_data)
  225. {
  226. struct musb_dma_controller *controller = private_data;
  227. struct musb *musb = controller->private_data;
  228. struct musb_dma_channel *musb_channel;
  229. struct dma_channel *channel;
  230. void __iomem *mbase = controller->base;
  231. irqreturn_t retval = IRQ_NONE;
  232. unsigned long flags;
  233. u8 bchannel;
  234. u8 int_hsdma;
  235. u32 addr, count;
  236. u16 csr;
  237. spin_lock_irqsave(&musb->lock, flags);
  238. int_hsdma = musb_clearb(mbase, MUSB_HSDMA_INTR);
  239. if (!int_hsdma) {
  240. musb_dbg(musb, "spurious DMA irq");
  241. for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
  242. musb_channel = (struct musb_dma_channel *)
  243. &(controller->channel[bchannel]);
  244. channel = &musb_channel->channel;
  245. if (channel->status == MUSB_DMA_STATUS_BUSY) {
  246. count = musb_read_hsdma_count(mbase, bchannel);
  247. if (count == 0)
  248. int_hsdma |= (1 << bchannel);
  249. }
  250. }
  251. musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
  252. if (!int_hsdma)
  253. goto done;
  254. }
  255. for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
  256. if (int_hsdma & (1 << bchannel)) {
  257. musb_channel = (struct musb_dma_channel *)
  258. &(controller->channel[bchannel]);
  259. channel = &musb_channel->channel;
  260. csr = musb_readw(mbase,
  261. MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
  262. MUSB_HSDMA_CONTROL));
  263. if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
  264. musb_channel->channel.status =
  265. MUSB_DMA_STATUS_BUS_ABORT;
  266. } else {
  267. u8 devctl;
  268. addr = musb_read_hsdma_addr(mbase,
  269. bchannel);
  270. channel->actual_len = addr
  271. - musb_channel->start_addr;
  272. musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
  273. channel, musb_channel->start_addr,
  274. addr, channel->actual_len,
  275. musb_channel->len,
  276. (channel->actual_len
  277. < musb_channel->len) ?
  278. "=> reconfig 0" : "=> complete");
  279. devctl = musb_readb(mbase, MUSB_DEVCTL);
  280. channel->status = MUSB_DMA_STATUS_FREE;
  281. /* completed */
  282. if (musb_channel->transmit &&
  283. (!channel->desired_mode ||
  284. (channel->actual_len %
  285. musb_channel->max_packet_sz))) {
  286. u8 epnum = musb_channel->epnum;
  287. int offset = musb->io.ep_offset(epnum,
  288. MUSB_TXCSR);
  289. u16 txcsr;
  290. /*
  291. * The programming guide says that we
  292. * must clear DMAENAB before DMAMODE.
  293. */
  294. musb_ep_select(mbase, epnum);
  295. txcsr = musb_readw(mbase, offset);
  296. if (channel->desired_mode == 1) {
  297. txcsr &= ~(MUSB_TXCSR_DMAENAB
  298. | MUSB_TXCSR_AUTOSET);
  299. musb_writew(mbase, offset, txcsr);
  300. /* Send out the packet */
  301. txcsr &= ~MUSB_TXCSR_DMAMODE;
  302. txcsr |= MUSB_TXCSR_DMAENAB;
  303. }
  304. txcsr |= MUSB_TXCSR_TXPKTRDY;
  305. musb_writew(mbase, offset, txcsr);
  306. }
  307. musb_dma_completion(musb, musb_channel->epnum,
  308. musb_channel->transmit);
  309. }
  310. }
  311. }
  312. retval = IRQ_HANDLED;
  313. done:
  314. spin_unlock_irqrestore(&musb->lock, flags);
  315. return retval;
  316. }
  317. EXPORT_SYMBOL_GPL(dma_controller_irq);
  318. void musbhs_dma_controller_destroy(struct dma_controller *c)
  319. {
  320. struct musb_dma_controller *controller = container_of(c,
  321. struct musb_dma_controller, controller);
  322. dma_controller_stop(controller);
  323. if (controller->irq)
  324. free_irq(controller->irq, c);
  325. kfree(controller);
  326. }
  327. EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
  328. static struct musb_dma_controller *
  329. dma_controller_alloc(struct musb *musb, void __iomem *base)
  330. {
  331. struct musb_dma_controller *controller;
  332. controller = kzalloc(sizeof(*controller), GFP_KERNEL);
  333. if (!controller)
  334. return NULL;
  335. controller->channel_count = MUSB_HSDMA_CHANNELS;
  336. controller->private_data = musb;
  337. controller->base = base;
  338. controller->controller.channel_alloc = dma_channel_allocate;
  339. controller->controller.channel_release = dma_channel_release;
  340. controller->controller.channel_program = dma_channel_program;
  341. controller->controller.channel_abort = dma_channel_abort;
  342. return controller;
  343. }
  344. struct dma_controller *
  345. musbhs_dma_controller_create(struct musb *musb, void __iomem *base)
  346. {
  347. struct musb_dma_controller *controller;
  348. struct device *dev = musb->controller;
  349. struct platform_device *pdev = to_platform_device(dev);
  350. int irq = platform_get_irq_byname(pdev, "dma");
  351. if (irq <= 0) {
  352. dev_err(dev, "No DMA interrupt line!\n");
  353. return NULL;
  354. }
  355. controller = dma_controller_alloc(musb, base);
  356. if (!controller)
  357. return NULL;
  358. if (request_irq(irq, dma_controller_irq, 0,
  359. dev_name(musb->controller), controller)) {
  360. dev_err(dev, "request_irq %d failed!\n", irq);
  361. musb_dma_controller_destroy(&controller->controller);
  362. return NULL;
  363. }
  364. controller->irq = irq;
  365. return &controller->controller;
  366. }
  367. EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
  368. struct dma_controller *
  369. musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base)
  370. {
  371. struct musb_dma_controller *controller;
  372. controller = dma_controller_alloc(musb, base);
  373. if (!controller)
  374. return NULL;
  375. return &controller->controller;
  376. }
  377. EXPORT_SYMBOL_GPL(musbhs_dma_controller_create_noirq);