musb_regs.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * MUSB OTG driver register defines
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. */
  9. #ifndef __MUSB_REGS_H__
  10. #define __MUSB_REGS_H__
  11. #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
  12. /*
  13. * MUSB Register bits
  14. */
  15. /* POWER */
  16. #define MUSB_POWER_ISOUPDATE 0x80
  17. #define MUSB_POWER_SOFTCONN 0x40
  18. #define MUSB_POWER_HSENAB 0x20
  19. #define MUSB_POWER_HSMODE 0x10
  20. #define MUSB_POWER_RESET 0x08
  21. #define MUSB_POWER_RESUME 0x04
  22. #define MUSB_POWER_SUSPENDM 0x02
  23. #define MUSB_POWER_ENSUSPEND 0x01
  24. /* INTRUSB */
  25. #define MUSB_INTR_SUSPEND 0x01
  26. #define MUSB_INTR_RESUME 0x02
  27. #define MUSB_INTR_RESET 0x04
  28. #define MUSB_INTR_BABBLE 0x04
  29. #define MUSB_INTR_SOF 0x08
  30. #define MUSB_INTR_CONNECT 0x10
  31. #define MUSB_INTR_DISCONNECT 0x20
  32. #define MUSB_INTR_SESSREQ 0x40
  33. #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
  34. /* DEVCTL */
  35. #define MUSB_DEVCTL_BDEVICE 0x80
  36. #define MUSB_DEVCTL_FSDEV 0x40
  37. #define MUSB_DEVCTL_LSDEV 0x20
  38. #define MUSB_DEVCTL_VBUS 0x18
  39. #define MUSB_DEVCTL_VBUS_SHIFT 3
  40. #define MUSB_DEVCTL_HM 0x04
  41. #define MUSB_DEVCTL_HR 0x02
  42. #define MUSB_DEVCTL_SESSION 0x01
  43. /* BABBLE_CTL */
  44. #define MUSB_BABBLE_FORCE_TXIDLE 0x80
  45. #define MUSB_BABBLE_SW_SESSION_CTRL 0x40
  46. #define MUSB_BABBLE_STUCK_J 0x20
  47. #define MUSB_BABBLE_RCV_DISABLE 0x04
  48. /* MUSB ULPI VBUSCONTROL */
  49. #define MUSB_ULPI_USE_EXTVBUS 0x01
  50. #define MUSB_ULPI_USE_EXTVBUSIND 0x02
  51. /* ULPI_REG_CONTROL */
  52. #define MUSB_ULPI_REG_REQ (1 << 0)
  53. #define MUSB_ULPI_REG_CMPLT (1 << 1)
  54. #define MUSB_ULPI_RDN_WR (1 << 2)
  55. /* TESTMODE */
  56. #define MUSB_TEST_FORCE_HOST 0x80
  57. #define MUSB_TEST_FIFO_ACCESS 0x40
  58. #define MUSB_TEST_FORCE_FS 0x20
  59. #define MUSB_TEST_FORCE_HS 0x10
  60. #define MUSB_TEST_PACKET 0x08
  61. #define MUSB_TEST_K 0x04
  62. #define MUSB_TEST_J 0x02
  63. #define MUSB_TEST_SE0_NAK 0x01
  64. /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
  65. #define MUSB_FIFOSZ_DPB 0x10
  66. /* Allocation size (8, 16, 32, ... 4096) */
  67. #define MUSB_FIFOSZ_SIZE 0x0f
  68. /* CSR0 */
  69. #define MUSB_CSR0_FLUSHFIFO 0x0100
  70. #define MUSB_CSR0_TXPKTRDY 0x0002
  71. #define MUSB_CSR0_RXPKTRDY 0x0001
  72. /* CSR0 in Peripheral mode */
  73. #define MUSB_CSR0_P_SVDSETUPEND 0x0080
  74. #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
  75. #define MUSB_CSR0_P_SENDSTALL 0x0020
  76. #define MUSB_CSR0_P_SETUPEND 0x0010
  77. #define MUSB_CSR0_P_DATAEND 0x0008
  78. #define MUSB_CSR0_P_SENTSTALL 0x0004
  79. /* CSR0 in Host mode */
  80. #define MUSB_CSR0_H_DIS_PING 0x0800
  81. #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
  82. #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
  83. #define MUSB_CSR0_H_NAKTIMEOUT 0x0080
  84. #define MUSB_CSR0_H_STATUSPKT 0x0040
  85. #define MUSB_CSR0_H_REQPKT 0x0020
  86. #define MUSB_CSR0_H_ERROR 0x0010
  87. #define MUSB_CSR0_H_SETUPPKT 0x0008
  88. #define MUSB_CSR0_H_RXSTALL 0x0004
  89. /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
  90. #define MUSB_CSR0_P_WZC_BITS \
  91. (MUSB_CSR0_P_SENTSTALL)
  92. #define MUSB_CSR0_H_WZC_BITS \
  93. (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
  94. | MUSB_CSR0_RXPKTRDY)
  95. /* TxType/RxType */
  96. #define MUSB_TYPE_SPEED 0xc0
  97. #define MUSB_TYPE_SPEED_SHIFT 6
  98. #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
  99. #define MUSB_TYPE_PROTO_SHIFT 4
  100. #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
  101. /* CONFIGDATA */
  102. #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
  103. #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
  104. #define MUSB_CONFIGDATA_BIGENDIAN 0x20
  105. #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
  106. #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
  107. #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
  108. #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
  109. #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
  110. /* TXCSR in Peripheral and Host mode */
  111. #define MUSB_TXCSR_AUTOSET 0x8000
  112. #define MUSB_TXCSR_DMAENAB 0x1000
  113. #define MUSB_TXCSR_FRCDATATOG 0x0800
  114. #define MUSB_TXCSR_DMAMODE 0x0400
  115. #define MUSB_TXCSR_CLRDATATOG 0x0040
  116. #define MUSB_TXCSR_FLUSHFIFO 0x0008
  117. #define MUSB_TXCSR_FIFONOTEMPTY 0x0002
  118. #define MUSB_TXCSR_TXPKTRDY 0x0001
  119. /* TXCSR in Peripheral mode */
  120. #define MUSB_TXCSR_P_ISO 0x4000
  121. #define MUSB_TXCSR_P_INCOMPTX 0x0080
  122. #define MUSB_TXCSR_P_SENTSTALL 0x0020
  123. #define MUSB_TXCSR_P_SENDSTALL 0x0010
  124. #define MUSB_TXCSR_P_UNDERRUN 0x0004
  125. /* TXCSR in Host mode */
  126. #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
  127. #define MUSB_TXCSR_H_DATATOGGLE 0x0100
  128. #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
  129. #define MUSB_TXCSR_H_RXSTALL 0x0020
  130. #define MUSB_TXCSR_H_ERROR 0x0004
  131. /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
  132. #define MUSB_TXCSR_P_WZC_BITS \
  133. (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
  134. | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
  135. #define MUSB_TXCSR_H_WZC_BITS \
  136. (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
  137. | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
  138. /* RXCSR in Peripheral and Host mode */
  139. #define MUSB_RXCSR_AUTOCLEAR 0x8000
  140. #define MUSB_RXCSR_DMAENAB 0x2000
  141. #define MUSB_RXCSR_DISNYET 0x1000
  142. #define MUSB_RXCSR_PID_ERR 0x1000
  143. #define MUSB_RXCSR_DMAMODE 0x0800
  144. #define MUSB_RXCSR_INCOMPRX 0x0100
  145. #define MUSB_RXCSR_CLRDATATOG 0x0080
  146. #define MUSB_RXCSR_FLUSHFIFO 0x0010
  147. #define MUSB_RXCSR_DATAERROR 0x0008
  148. #define MUSB_RXCSR_FIFOFULL 0x0002
  149. #define MUSB_RXCSR_RXPKTRDY 0x0001
  150. /* RXCSR in Peripheral mode */
  151. #define MUSB_RXCSR_P_ISO 0x4000
  152. #define MUSB_RXCSR_P_SENTSTALL 0x0040
  153. #define MUSB_RXCSR_P_SENDSTALL 0x0020
  154. #define MUSB_RXCSR_P_OVERRUN 0x0004
  155. /* RXCSR in Host mode */
  156. #define MUSB_RXCSR_H_AUTOREQ 0x4000
  157. #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
  158. #define MUSB_RXCSR_H_DATATOGGLE 0x0200
  159. #define MUSB_RXCSR_H_RXSTALL 0x0040
  160. #define MUSB_RXCSR_H_REQPKT 0x0020
  161. #define MUSB_RXCSR_H_ERROR 0x0004
  162. /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
  163. #define MUSB_RXCSR_P_WZC_BITS \
  164. (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
  165. | MUSB_RXCSR_RXPKTRDY)
  166. #define MUSB_RXCSR_H_WZC_BITS \
  167. (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
  168. | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
  169. /* HUBADDR */
  170. #define MUSB_HUBADDR_MULTI_TT 0x80
  171. /*
  172. * Common USB registers
  173. */
  174. #define MUSB_FADDR 0x00 /* 8-bit */
  175. #define MUSB_POWER 0x01 /* 8-bit */
  176. #define MUSB_INTRTX 0x02 /* 16-bit */
  177. #define MUSB_INTRRX 0x04
  178. #define MUSB_INTRTXE 0x06
  179. #define MUSB_INTRRXE 0x08
  180. #define MUSB_INTRUSB 0x0A /* 8 bit */
  181. #define MUSB_INTRUSBE 0x0B /* 8 bit */
  182. #define MUSB_FRAME 0x0C
  183. #define MUSB_INDEX 0x0E /* 8 bit */
  184. #define MUSB_TESTMODE 0x0F /* 8 bit */
  185. /*
  186. * Additional Control Registers
  187. */
  188. #define MUSB_DEVCTL 0x60 /* 8 bit */
  189. #define MUSB_BABBLE_CTL 0x61 /* 8 bit */
  190. /* These are always controlled through the INDEX register */
  191. #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
  192. #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
  193. #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
  194. #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
  195. /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
  196. #define MUSB_HWVERS 0x6C /* 8 bit */
  197. #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
  198. #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
  199. #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
  200. #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
  201. #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
  202. #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
  203. #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
  204. #define MUSB_EPINFO 0x78 /* 8 bit */
  205. #define MUSB_RAMINFO 0x79 /* 8 bit */
  206. #define MUSB_LINKINFO 0x7a /* 8 bit */
  207. #define MUSB_VPLEN 0x7b /* 8 bit */
  208. #define MUSB_HS_EOF1 0x7c /* 8 bit */
  209. #define MUSB_FS_EOF1 0x7d /* 8 bit */
  210. #define MUSB_LS_EOF1 0x7e /* 8 bit */
  211. /* Offsets to endpoint registers */
  212. #define MUSB_TXMAXP 0x00
  213. #define MUSB_TXCSR 0x02
  214. #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
  215. #define MUSB_RXMAXP 0x04
  216. #define MUSB_RXCSR 0x06
  217. #define MUSB_RXCOUNT 0x08
  218. #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
  219. #define MUSB_TXTYPE 0x0A
  220. #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
  221. #define MUSB_TXINTERVAL 0x0B
  222. #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
  223. #define MUSB_RXTYPE 0x0C
  224. #define MUSB_RXINTERVAL 0x0D
  225. #define MUSB_FIFOSIZE 0x0F
  226. #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
  227. #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
  228. #define MUSB_TXCSR_MODE 0x2000
  229. /* "bus control"/target registers, for host side multipoint (external hubs) */
  230. #define MUSB_TXFUNCADDR 0x00
  231. #define MUSB_TXHUBADDR 0x02
  232. #define MUSB_TXHUBPORT 0x03
  233. #define MUSB_RXFUNCADDR 0x04
  234. #define MUSB_RXHUBADDR 0x06
  235. #define MUSB_RXHUBPORT 0x07
  236. static inline u8 musb_read_configdata(void __iomem *mbase)
  237. {
  238. musb_writeb(mbase, MUSB_INDEX, 0);
  239. return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
  240. }
  241. static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum,
  242. u8 qh_addr_reg)
  243. {
  244. musb_writeb(musb->mregs,
  245. musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR),
  246. qh_addr_reg);
  247. }
  248. static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum,
  249. u8 qh_h_addr_reg)
  250. {
  251. musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR),
  252. qh_h_addr_reg);
  253. }
  254. static inline void musb_write_rxhubport(struct musb *musb, u8 epnum,
  255. u8 qh_h_port_reg)
  256. {
  257. musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT),
  258. qh_h_port_reg);
  259. }
  260. static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum,
  261. u8 qh_addr_reg)
  262. {
  263. musb_writeb(musb->mregs,
  264. musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR),
  265. qh_addr_reg);
  266. }
  267. static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum,
  268. u8 qh_addr_reg)
  269. {
  270. musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR),
  271. qh_addr_reg);
  272. }
  273. static inline void musb_write_txhubport(struct musb *musb, u8 epnum,
  274. u8 qh_h_port_reg)
  275. {
  276. musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT),
  277. qh_h_port_reg);
  278. }
  279. static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum)
  280. {
  281. return musb_readb(musb->mregs,
  282. musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR));
  283. }
  284. static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum)
  285. {
  286. return musb_readb(musb->mregs,
  287. musb->io.busctl_offset(epnum, MUSB_RXHUBADDR));
  288. }
  289. static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum)
  290. {
  291. return musb_readb(musb->mregs,
  292. musb->io.busctl_offset(epnum, MUSB_RXHUBPORT));
  293. }
  294. static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum)
  295. {
  296. return musb_readb(musb->mregs,
  297. musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR));
  298. }
  299. static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum)
  300. {
  301. return musb_readb(musb->mregs,
  302. musb->io.busctl_offset(epnum, MUSB_TXHUBADDR));
  303. }
  304. static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
  305. {
  306. return musb_readb(musb->mregs,
  307. musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
  308. }
  309. #endif /* __MUSB_REGS_H__ */