musb_gadget_ep0.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG peripheral driver ep0 handling
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/list.h>
  12. #include <linux/timer.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/device.h>
  15. #include <linux/interrupt.h>
  16. #include "musb_core.h"
  17. /* ep0 is always musb->endpoints[0].ep_in */
  18. #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
  19. /*
  20. * locking note: we use only the controller lock, for simpler correctness.
  21. * It's always held with IRQs blocked.
  22. *
  23. * It protects the ep0 request queue as well as ep0_state, not just the
  24. * controller and indexed registers. And that lock stays held unless it
  25. * needs to be dropped to allow reentering this driver ... like upcalls to
  26. * the gadget driver, or adjusting endpoint halt status.
  27. */
  28. static char *decode_ep0stage(u8 stage)
  29. {
  30. switch (stage) {
  31. case MUSB_EP0_STAGE_IDLE: return "idle";
  32. case MUSB_EP0_STAGE_SETUP: return "setup";
  33. case MUSB_EP0_STAGE_TX: return "in";
  34. case MUSB_EP0_STAGE_RX: return "out";
  35. case MUSB_EP0_STAGE_ACKWAIT: return "wait";
  36. case MUSB_EP0_STAGE_STATUSIN: return "in/status";
  37. case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
  38. default: return "?";
  39. }
  40. }
  41. /* handle a standard GET_STATUS request
  42. * Context: caller holds controller lock
  43. */
  44. static int service_tx_status_request(
  45. struct musb *musb,
  46. const struct usb_ctrlrequest *ctrlrequest)
  47. {
  48. void __iomem *mbase = musb->mregs;
  49. int handled = 1;
  50. u8 result[2], epnum = 0;
  51. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  52. result[1] = 0;
  53. switch (recip) {
  54. case USB_RECIP_DEVICE:
  55. result[0] = musb->g.is_selfpowered << USB_DEVICE_SELF_POWERED;
  56. result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  57. if (musb->g.is_otg) {
  58. result[0] |= musb->g.b_hnp_enable
  59. << USB_DEVICE_B_HNP_ENABLE;
  60. result[0] |= musb->g.a_alt_hnp_support
  61. << USB_DEVICE_A_ALT_HNP_SUPPORT;
  62. result[0] |= musb->g.a_hnp_support
  63. << USB_DEVICE_A_HNP_SUPPORT;
  64. }
  65. break;
  66. case USB_RECIP_INTERFACE:
  67. result[0] = 0;
  68. break;
  69. case USB_RECIP_ENDPOINT: {
  70. int is_in;
  71. struct musb_ep *ep;
  72. u16 tmp;
  73. void __iomem *regs;
  74. epnum = (u8) ctrlrequest->wIndex;
  75. if (!epnum) {
  76. result[0] = 0;
  77. break;
  78. }
  79. is_in = epnum & USB_DIR_IN;
  80. epnum &= 0x0f;
  81. if (epnum >= MUSB_C_NUM_EPS) {
  82. handled = -EINVAL;
  83. break;
  84. }
  85. if (is_in)
  86. ep = &musb->endpoints[epnum].ep_in;
  87. else
  88. ep = &musb->endpoints[epnum].ep_out;
  89. regs = musb->endpoints[epnum].regs;
  90. if (!ep->desc) {
  91. handled = -EINVAL;
  92. break;
  93. }
  94. musb_ep_select(mbase, epnum);
  95. if (is_in)
  96. tmp = musb_readw(regs, MUSB_TXCSR)
  97. & MUSB_TXCSR_P_SENDSTALL;
  98. else
  99. tmp = musb_readw(regs, MUSB_RXCSR)
  100. & MUSB_RXCSR_P_SENDSTALL;
  101. musb_ep_select(mbase, 0);
  102. result[0] = tmp ? 1 : 0;
  103. } break;
  104. default:
  105. /* class, vendor, etc ... delegate */
  106. handled = 0;
  107. break;
  108. }
  109. /* fill up the fifo; caller updates csr0 */
  110. if (handled > 0) {
  111. u16 len = le16_to_cpu(ctrlrequest->wLength);
  112. if (len > 2)
  113. len = 2;
  114. musb_write_fifo(&musb->endpoints[0], len, result);
  115. }
  116. return handled;
  117. }
  118. /*
  119. * handle a control-IN request, the end0 buffer contains the current request
  120. * that is supposed to be a standard control request. Assumes the fifo to
  121. * be at least 2 bytes long.
  122. *
  123. * @return 0 if the request was NOT HANDLED,
  124. * < 0 when error
  125. * > 0 when the request is processed
  126. *
  127. * Context: caller holds controller lock
  128. */
  129. static int
  130. service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  131. {
  132. int handled = 0; /* not handled */
  133. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  134. == USB_TYPE_STANDARD) {
  135. switch (ctrlrequest->bRequest) {
  136. case USB_REQ_GET_STATUS:
  137. handled = service_tx_status_request(musb,
  138. ctrlrequest);
  139. break;
  140. /* case USB_REQ_SYNC_FRAME: */
  141. default:
  142. break;
  143. }
  144. }
  145. return handled;
  146. }
  147. /*
  148. * Context: caller holds controller lock
  149. */
  150. static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
  151. {
  152. musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
  153. }
  154. /*
  155. * Tries to start B-device HNP negotiation if enabled via sysfs
  156. */
  157. static inline void musb_try_b_hnp_enable(struct musb *musb)
  158. {
  159. void __iomem *mbase = musb->mregs;
  160. u8 devctl;
  161. musb_dbg(musb, "HNP: Setting HR");
  162. devctl = musb_readb(mbase, MUSB_DEVCTL);
  163. musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
  164. }
  165. /*
  166. * Handle all control requests with no DATA stage, including standard
  167. * requests such as:
  168. * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
  169. * always delegated to the gadget driver
  170. * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
  171. * always handled here, except for class/vendor/... features
  172. *
  173. * Context: caller holds controller lock
  174. */
  175. static int
  176. service_zero_data_request(struct musb *musb,
  177. struct usb_ctrlrequest *ctrlrequest)
  178. __releases(musb->lock)
  179. __acquires(musb->lock)
  180. {
  181. int handled = -EINVAL;
  182. void __iomem *mbase = musb->mregs;
  183. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  184. /* the gadget driver handles everything except what we MUST handle */
  185. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  186. == USB_TYPE_STANDARD) {
  187. switch (ctrlrequest->bRequest) {
  188. case USB_REQ_SET_ADDRESS:
  189. /* change it after the status stage */
  190. musb->set_address = true;
  191. musb->address = (u8) (ctrlrequest->wValue & 0x7f);
  192. handled = 1;
  193. break;
  194. case USB_REQ_CLEAR_FEATURE:
  195. switch (recip) {
  196. case USB_RECIP_DEVICE:
  197. if (ctrlrequest->wValue
  198. != USB_DEVICE_REMOTE_WAKEUP)
  199. break;
  200. musb->may_wakeup = 0;
  201. handled = 1;
  202. break;
  203. case USB_RECIP_INTERFACE:
  204. break;
  205. case USB_RECIP_ENDPOINT:{
  206. const u8 epnum =
  207. ctrlrequest->wIndex & 0x0f;
  208. struct musb_ep *musb_ep;
  209. struct musb_hw_ep *ep;
  210. struct musb_request *request;
  211. void __iomem *regs;
  212. int is_in;
  213. u16 csr;
  214. if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
  215. ctrlrequest->wValue != USB_ENDPOINT_HALT)
  216. break;
  217. ep = musb->endpoints + epnum;
  218. regs = ep->regs;
  219. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  220. if (is_in)
  221. musb_ep = &ep->ep_in;
  222. else
  223. musb_ep = &ep->ep_out;
  224. if (!musb_ep->desc)
  225. break;
  226. handled = 1;
  227. /* Ignore request if endpoint is wedged */
  228. if (musb_ep->wedged)
  229. break;
  230. musb_ep_select(mbase, epnum);
  231. if (is_in) {
  232. csr = musb_readw(regs, MUSB_TXCSR);
  233. csr |= MUSB_TXCSR_CLRDATATOG |
  234. MUSB_TXCSR_P_WZC_BITS;
  235. csr &= ~(MUSB_TXCSR_P_SENDSTALL |
  236. MUSB_TXCSR_P_SENTSTALL |
  237. MUSB_TXCSR_TXPKTRDY);
  238. musb_writew(regs, MUSB_TXCSR, csr);
  239. } else {
  240. csr = musb_readw(regs, MUSB_RXCSR);
  241. csr |= MUSB_RXCSR_CLRDATATOG |
  242. MUSB_RXCSR_P_WZC_BITS;
  243. csr &= ~(MUSB_RXCSR_P_SENDSTALL |
  244. MUSB_RXCSR_P_SENTSTALL);
  245. musb_writew(regs, MUSB_RXCSR, csr);
  246. }
  247. /* Maybe start the first request in the queue */
  248. request = next_request(musb_ep);
  249. if (!musb_ep->busy && request) {
  250. musb_dbg(musb, "restarting the request");
  251. musb_ep_restart(musb, request);
  252. }
  253. /* select ep0 again */
  254. musb_ep_select(mbase, 0);
  255. } break;
  256. default:
  257. /* class, vendor, etc ... delegate */
  258. handled = 0;
  259. break;
  260. }
  261. break;
  262. case USB_REQ_SET_FEATURE:
  263. switch (recip) {
  264. case USB_RECIP_DEVICE:
  265. handled = 1;
  266. switch (ctrlrequest->wValue) {
  267. case USB_DEVICE_REMOTE_WAKEUP:
  268. musb->may_wakeup = 1;
  269. break;
  270. case USB_DEVICE_TEST_MODE:
  271. if (musb->g.speed != USB_SPEED_HIGH)
  272. goto stall;
  273. if (ctrlrequest->wIndex & 0xff)
  274. goto stall;
  275. switch (ctrlrequest->wIndex >> 8) {
  276. case USB_TEST_J:
  277. pr_debug("USB_TEST_J\n");
  278. musb->test_mode_nr =
  279. MUSB_TEST_J;
  280. break;
  281. case USB_TEST_K:
  282. pr_debug("USB_TEST_K\n");
  283. musb->test_mode_nr =
  284. MUSB_TEST_K;
  285. break;
  286. case USB_TEST_SE0_NAK:
  287. pr_debug("USB_TEST_SE0_NAK\n");
  288. musb->test_mode_nr =
  289. MUSB_TEST_SE0_NAK;
  290. break;
  291. case USB_TEST_PACKET:
  292. pr_debug("USB_TEST_PACKET\n");
  293. musb->test_mode_nr =
  294. MUSB_TEST_PACKET;
  295. break;
  296. case 0xc0:
  297. /* TEST_FORCE_HS */
  298. pr_debug("TEST_FORCE_HS\n");
  299. musb->test_mode_nr =
  300. MUSB_TEST_FORCE_HS;
  301. break;
  302. case 0xc1:
  303. /* TEST_FORCE_FS */
  304. pr_debug("TEST_FORCE_FS\n");
  305. musb->test_mode_nr =
  306. MUSB_TEST_FORCE_FS;
  307. break;
  308. case 0xc2:
  309. /* TEST_FIFO_ACCESS */
  310. pr_debug("TEST_FIFO_ACCESS\n");
  311. musb->test_mode_nr =
  312. MUSB_TEST_FIFO_ACCESS;
  313. break;
  314. case 0xc3:
  315. /* TEST_FORCE_HOST */
  316. pr_debug("TEST_FORCE_HOST\n");
  317. musb->test_mode_nr =
  318. MUSB_TEST_FORCE_HOST;
  319. break;
  320. default:
  321. goto stall;
  322. }
  323. /* enter test mode after irq */
  324. if (handled > 0)
  325. musb->test_mode = true;
  326. break;
  327. case USB_DEVICE_B_HNP_ENABLE:
  328. if (!musb->g.is_otg)
  329. goto stall;
  330. musb->g.b_hnp_enable = 1;
  331. musb_try_b_hnp_enable(musb);
  332. break;
  333. case USB_DEVICE_A_HNP_SUPPORT:
  334. if (!musb->g.is_otg)
  335. goto stall;
  336. musb->g.a_hnp_support = 1;
  337. break;
  338. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  339. if (!musb->g.is_otg)
  340. goto stall;
  341. musb->g.a_alt_hnp_support = 1;
  342. break;
  343. case USB_DEVICE_DEBUG_MODE:
  344. handled = 0;
  345. break;
  346. stall:
  347. default:
  348. handled = -EINVAL;
  349. break;
  350. }
  351. break;
  352. case USB_RECIP_INTERFACE:
  353. break;
  354. case USB_RECIP_ENDPOINT:{
  355. const u8 epnum =
  356. ctrlrequest->wIndex & 0x0f;
  357. struct musb_ep *musb_ep;
  358. struct musb_hw_ep *ep;
  359. void __iomem *regs;
  360. int is_in;
  361. u16 csr;
  362. if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
  363. ctrlrequest->wValue != USB_ENDPOINT_HALT)
  364. break;
  365. ep = musb->endpoints + epnum;
  366. regs = ep->regs;
  367. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  368. if (is_in)
  369. musb_ep = &ep->ep_in;
  370. else
  371. musb_ep = &ep->ep_out;
  372. if (!musb_ep->desc)
  373. break;
  374. musb_ep_select(mbase, epnum);
  375. if (is_in) {
  376. csr = musb_readw(regs, MUSB_TXCSR);
  377. if (csr & MUSB_TXCSR_FIFONOTEMPTY)
  378. csr |= MUSB_TXCSR_FLUSHFIFO;
  379. csr |= MUSB_TXCSR_P_SENDSTALL
  380. | MUSB_TXCSR_CLRDATATOG
  381. | MUSB_TXCSR_P_WZC_BITS;
  382. musb_writew(regs, MUSB_TXCSR, csr);
  383. } else {
  384. csr = musb_readw(regs, MUSB_RXCSR);
  385. csr |= MUSB_RXCSR_P_SENDSTALL
  386. | MUSB_RXCSR_FLUSHFIFO
  387. | MUSB_RXCSR_CLRDATATOG
  388. | MUSB_RXCSR_P_WZC_BITS;
  389. musb_writew(regs, MUSB_RXCSR, csr);
  390. }
  391. /* select ep0 again */
  392. musb_ep_select(mbase, 0);
  393. handled = 1;
  394. } break;
  395. default:
  396. /* class, vendor, etc ... delegate */
  397. handled = 0;
  398. break;
  399. }
  400. break;
  401. default:
  402. /* delegate SET_CONFIGURATION, etc */
  403. handled = 0;
  404. }
  405. } else
  406. handled = 0;
  407. return handled;
  408. }
  409. /* we have an ep0out data packet
  410. * Context: caller holds controller lock
  411. */
  412. static void ep0_rxstate(struct musb *musb)
  413. {
  414. void __iomem *regs = musb->control_ep->regs;
  415. struct musb_request *request;
  416. struct usb_request *req;
  417. u16 count, csr;
  418. request = next_ep0_request(musb);
  419. req = &request->request;
  420. /* read packet and ack; or stall because of gadget driver bug:
  421. * should have provided the rx buffer before setup() returned.
  422. */
  423. if (req) {
  424. void *buf = req->buf + req->actual;
  425. unsigned len = req->length - req->actual;
  426. /* read the buffer */
  427. count = musb_readb(regs, MUSB_COUNT0);
  428. if (count > len) {
  429. req->status = -EOVERFLOW;
  430. count = len;
  431. }
  432. if (count > 0) {
  433. musb_read_fifo(&musb->endpoints[0], count, buf);
  434. req->actual += count;
  435. }
  436. csr = MUSB_CSR0_P_SVDRXPKTRDY;
  437. if (count < 64 || req->actual == req->length) {
  438. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  439. csr |= MUSB_CSR0_P_DATAEND;
  440. } else
  441. req = NULL;
  442. } else
  443. csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
  444. /* Completion handler may choose to stall, e.g. because the
  445. * message just received holds invalid data.
  446. */
  447. if (req) {
  448. musb->ackpend = csr;
  449. musb_g_ep0_giveback(musb, req);
  450. if (!musb->ackpend)
  451. return;
  452. musb->ackpend = 0;
  453. }
  454. musb_ep_select(musb->mregs, 0);
  455. musb_writew(regs, MUSB_CSR0, csr);
  456. }
  457. /*
  458. * transmitting to the host (IN), this code might be called from IRQ
  459. * and from kernel thread.
  460. *
  461. * Context: caller holds controller lock
  462. */
  463. static void ep0_txstate(struct musb *musb)
  464. {
  465. void __iomem *regs = musb->control_ep->regs;
  466. struct musb_request *req = next_ep0_request(musb);
  467. struct usb_request *request;
  468. u16 csr = MUSB_CSR0_TXPKTRDY;
  469. u8 *fifo_src;
  470. u8 fifo_count;
  471. if (!req) {
  472. /* WARN_ON(1); */
  473. musb_dbg(musb, "odd; csr0 %04x", musb_readw(regs, MUSB_CSR0));
  474. return;
  475. }
  476. request = &req->request;
  477. /* load the data */
  478. fifo_src = (u8 *) request->buf + request->actual;
  479. fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
  480. request->length - request->actual);
  481. musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
  482. request->actual += fifo_count;
  483. /* update the flags */
  484. if (fifo_count < MUSB_MAX_END0_PACKET
  485. || (request->actual == request->length
  486. && !request->zero)) {
  487. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  488. csr |= MUSB_CSR0_P_DATAEND;
  489. } else
  490. request = NULL;
  491. /* report completions as soon as the fifo's loaded; there's no
  492. * win in waiting till this last packet gets acked. (other than
  493. * very precise fault reporting, needed by USB TMC; possible with
  494. * this hardware, but not usable from portable gadget drivers.)
  495. */
  496. if (request) {
  497. musb->ackpend = csr;
  498. musb_g_ep0_giveback(musb, request);
  499. if (!musb->ackpend)
  500. return;
  501. musb->ackpend = 0;
  502. }
  503. /* send it out, triggering a "txpktrdy cleared" irq */
  504. musb_ep_select(musb->mregs, 0);
  505. musb_writew(regs, MUSB_CSR0, csr);
  506. }
  507. /*
  508. * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
  509. * Fields are left in USB byte-order.
  510. *
  511. * Context: caller holds controller lock.
  512. */
  513. static void
  514. musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
  515. {
  516. struct musb_request *r;
  517. void __iomem *regs = musb->control_ep->regs;
  518. musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
  519. /* NOTE: earlier 2.6 versions changed setup packets to host
  520. * order, but now USB packets always stay in USB byte order.
  521. */
  522. musb_dbg(musb, "SETUP req%02x.%02x v%04x i%04x l%d",
  523. req->bRequestType,
  524. req->bRequest,
  525. le16_to_cpu(req->wValue),
  526. le16_to_cpu(req->wIndex),
  527. le16_to_cpu(req->wLength));
  528. /* clean up any leftover transfers */
  529. r = next_ep0_request(musb);
  530. if (r)
  531. musb_g_ep0_giveback(musb, &r->request);
  532. /* For zero-data requests we want to delay the STATUS stage to
  533. * avoid SETUPEND errors. If we read data (OUT), delay accepting
  534. * packets until there's a buffer to store them in.
  535. *
  536. * If we write data, the controller acts happier if we enable
  537. * the TX FIFO right away, and give the controller a moment
  538. * to switch modes...
  539. */
  540. musb->set_address = false;
  541. musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
  542. if (req->wLength == 0) {
  543. if (req->bRequestType & USB_DIR_IN)
  544. musb->ackpend |= MUSB_CSR0_TXPKTRDY;
  545. musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
  546. } else if (req->bRequestType & USB_DIR_IN) {
  547. musb->ep0_state = MUSB_EP0_STAGE_TX;
  548. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
  549. while ((musb_readw(regs, MUSB_CSR0)
  550. & MUSB_CSR0_RXPKTRDY) != 0)
  551. cpu_relax();
  552. musb->ackpend = 0;
  553. } else
  554. musb->ep0_state = MUSB_EP0_STAGE_RX;
  555. }
  556. static int
  557. forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  558. __releases(musb->lock)
  559. __acquires(musb->lock)
  560. {
  561. int retval;
  562. if (!musb->gadget_driver)
  563. return -EOPNOTSUPP;
  564. spin_unlock(&musb->lock);
  565. retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
  566. spin_lock(&musb->lock);
  567. return retval;
  568. }
  569. /*
  570. * Handle peripheral ep0 interrupt
  571. *
  572. * Context: irq handler; we won't re-enter the driver that way.
  573. */
  574. irqreturn_t musb_g_ep0_irq(struct musb *musb)
  575. {
  576. u16 csr;
  577. u16 len;
  578. void __iomem *mbase = musb->mregs;
  579. void __iomem *regs = musb->endpoints[0].regs;
  580. irqreturn_t retval = IRQ_NONE;
  581. musb_ep_select(mbase, 0); /* select ep0 */
  582. csr = musb_readw(regs, MUSB_CSR0);
  583. len = musb_readb(regs, MUSB_COUNT0);
  584. musb_dbg(musb, "csr %04x, count %d, ep0stage %s",
  585. csr, len, decode_ep0stage(musb->ep0_state));
  586. if (csr & MUSB_CSR0_P_DATAEND) {
  587. /*
  588. * If DATAEND is set we should not call the callback,
  589. * hence the status stage is not complete.
  590. */
  591. return IRQ_HANDLED;
  592. }
  593. /* I sent a stall.. need to acknowledge it now.. */
  594. if (csr & MUSB_CSR0_P_SENTSTALL) {
  595. musb_writew(regs, MUSB_CSR0,
  596. csr & ~MUSB_CSR0_P_SENTSTALL);
  597. retval = IRQ_HANDLED;
  598. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  599. csr = musb_readw(regs, MUSB_CSR0);
  600. }
  601. /* request ended "early" */
  602. if (csr & MUSB_CSR0_P_SETUPEND) {
  603. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
  604. retval = IRQ_HANDLED;
  605. /* Transition into the early status phase */
  606. switch (musb->ep0_state) {
  607. case MUSB_EP0_STAGE_TX:
  608. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  609. break;
  610. case MUSB_EP0_STAGE_RX:
  611. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  612. break;
  613. default:
  614. ERR("SetupEnd came in a wrong ep0stage %s\n",
  615. decode_ep0stage(musb->ep0_state));
  616. }
  617. csr = musb_readw(regs, MUSB_CSR0);
  618. /* NOTE: request may need completion */
  619. }
  620. /* docs from Mentor only describe tx, rx, and idle/setup states.
  621. * we need to handle nuances around status stages, and also the
  622. * case where status and setup stages come back-to-back ...
  623. */
  624. switch (musb->ep0_state) {
  625. case MUSB_EP0_STAGE_TX:
  626. /* irq on clearing txpktrdy */
  627. if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
  628. ep0_txstate(musb);
  629. retval = IRQ_HANDLED;
  630. }
  631. break;
  632. case MUSB_EP0_STAGE_RX:
  633. /* irq on set rxpktrdy */
  634. if (csr & MUSB_CSR0_RXPKTRDY) {
  635. ep0_rxstate(musb);
  636. retval = IRQ_HANDLED;
  637. }
  638. break;
  639. case MUSB_EP0_STAGE_STATUSIN:
  640. /* end of sequence #2 (OUT/RX state) or #3 (no data) */
  641. /* update address (if needed) only @ the end of the
  642. * status phase per usb spec, which also guarantees
  643. * we get 10 msec to receive this irq... until this
  644. * is done we won't see the next packet.
  645. */
  646. if (musb->set_address) {
  647. musb->set_address = false;
  648. musb_writeb(mbase, MUSB_FADDR, musb->address);
  649. }
  650. /* enter test mode if needed (exit by reset) */
  651. else if (musb->test_mode) {
  652. musb_dbg(musb, "entering TESTMODE");
  653. if (MUSB_TEST_PACKET == musb->test_mode_nr)
  654. musb_load_testpacket(musb);
  655. musb_writeb(mbase, MUSB_TESTMODE,
  656. musb->test_mode_nr);
  657. }
  658. fallthrough;
  659. case MUSB_EP0_STAGE_STATUSOUT:
  660. /* end of sequence #1: write to host (TX state) */
  661. {
  662. struct musb_request *req;
  663. req = next_ep0_request(musb);
  664. if (req)
  665. musb_g_ep0_giveback(musb, &req->request);
  666. }
  667. /*
  668. * In case when several interrupts can get coalesced,
  669. * check to see if we've already received a SETUP packet...
  670. */
  671. if (csr & MUSB_CSR0_RXPKTRDY)
  672. goto setup;
  673. retval = IRQ_HANDLED;
  674. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  675. break;
  676. case MUSB_EP0_STAGE_IDLE:
  677. /*
  678. * This state is typically (but not always) indiscernible
  679. * from the status states since the corresponding interrupts
  680. * tend to happen within too little period of time (with only
  681. * a zero-length packet in between) and so get coalesced...
  682. */
  683. retval = IRQ_HANDLED;
  684. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  685. fallthrough;
  686. case MUSB_EP0_STAGE_SETUP:
  687. setup:
  688. if (csr & MUSB_CSR0_RXPKTRDY) {
  689. struct usb_ctrlrequest setup;
  690. int handled = 0;
  691. if (len != 8) {
  692. ERR("SETUP packet len %d != 8 ?\n", len);
  693. break;
  694. }
  695. musb_read_setup(musb, &setup);
  696. retval = IRQ_HANDLED;
  697. /* sometimes the RESET won't be reported */
  698. if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
  699. u8 power;
  700. printk(KERN_NOTICE "%s: peripheral reset "
  701. "irq lost!\n",
  702. musb_driver_name);
  703. power = musb_readb(mbase, MUSB_POWER);
  704. musb->g.speed = (power & MUSB_POWER_HSMODE)
  705. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  706. }
  707. switch (musb->ep0_state) {
  708. /* sequence #3 (no data stage), includes requests
  709. * we can't forward (notably SET_ADDRESS and the
  710. * device/endpoint feature set/clear operations)
  711. * plus SET_CONFIGURATION and others we must
  712. */
  713. case MUSB_EP0_STAGE_ACKWAIT:
  714. handled = service_zero_data_request(
  715. musb, &setup);
  716. /*
  717. * We're expecting no data in any case, so
  718. * always set the DATAEND bit -- doing this
  719. * here helps avoid SetupEnd interrupt coming
  720. * in the idle stage when we're stalling...
  721. */
  722. musb->ackpend |= MUSB_CSR0_P_DATAEND;
  723. /* status stage might be immediate */
  724. if (handled > 0)
  725. musb->ep0_state =
  726. MUSB_EP0_STAGE_STATUSIN;
  727. break;
  728. /* sequence #1 (IN to host), includes GET_STATUS
  729. * requests that we can't forward, GET_DESCRIPTOR
  730. * and others that we must
  731. */
  732. case MUSB_EP0_STAGE_TX:
  733. handled = service_in_request(musb, &setup);
  734. if (handled > 0) {
  735. musb->ackpend = MUSB_CSR0_TXPKTRDY
  736. | MUSB_CSR0_P_DATAEND;
  737. musb->ep0_state =
  738. MUSB_EP0_STAGE_STATUSOUT;
  739. }
  740. break;
  741. /* sequence #2 (OUT from host), always forward */
  742. default: /* MUSB_EP0_STAGE_RX */
  743. break;
  744. }
  745. musb_dbg(musb, "handled %d, csr %04x, ep0stage %s",
  746. handled, csr,
  747. decode_ep0stage(musb->ep0_state));
  748. /* unless we need to delegate this to the gadget
  749. * driver, we know how to wrap this up: csr0 has
  750. * not yet been written.
  751. */
  752. if (handled < 0)
  753. goto stall;
  754. else if (handled > 0)
  755. goto finish;
  756. handled = forward_to_driver(musb, &setup);
  757. if (handled < 0) {
  758. musb_ep_select(mbase, 0);
  759. stall:
  760. musb_dbg(musb, "stall (%d)", handled);
  761. musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
  762. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  763. finish:
  764. musb_writew(regs, MUSB_CSR0,
  765. musb->ackpend);
  766. musb->ackpend = 0;
  767. }
  768. }
  769. break;
  770. case MUSB_EP0_STAGE_ACKWAIT:
  771. /* This should not happen. But happens with tusb6010 with
  772. * g_file_storage and high speed. Do nothing.
  773. */
  774. retval = IRQ_HANDLED;
  775. break;
  776. default:
  777. /* "can't happen" */
  778. WARN_ON(1);
  779. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
  780. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  781. break;
  782. }
  783. return retval;
  784. }
  785. static int
  786. musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
  787. {
  788. /* always enabled */
  789. return -EINVAL;
  790. }
  791. static int musb_g_ep0_disable(struct usb_ep *e)
  792. {
  793. /* always enabled */
  794. return -EINVAL;
  795. }
  796. static int
  797. musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
  798. {
  799. struct musb_ep *ep;
  800. struct musb_request *req;
  801. struct musb *musb;
  802. int status;
  803. unsigned long lockflags;
  804. void __iomem *regs;
  805. if (!e || !r)
  806. return -EINVAL;
  807. ep = to_musb_ep(e);
  808. musb = ep->musb;
  809. regs = musb->control_ep->regs;
  810. req = to_musb_request(r);
  811. req->musb = musb;
  812. req->request.actual = 0;
  813. req->request.status = -EINPROGRESS;
  814. req->tx = ep->is_in;
  815. spin_lock_irqsave(&musb->lock, lockflags);
  816. if (!list_empty(&ep->req_list)) {
  817. status = -EBUSY;
  818. goto cleanup;
  819. }
  820. switch (musb->ep0_state) {
  821. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  822. case MUSB_EP0_STAGE_TX: /* control-IN data */
  823. case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
  824. status = 0;
  825. break;
  826. default:
  827. musb_dbg(musb, "ep0 request queued in state %d",
  828. musb->ep0_state);
  829. status = -EINVAL;
  830. goto cleanup;
  831. }
  832. /* add request to the list */
  833. list_add_tail(&req->list, &ep->req_list);
  834. musb_dbg(musb, "queue to %s (%s), length=%d",
  835. ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
  836. req->request.length);
  837. musb_ep_select(musb->mregs, 0);
  838. /* sequence #1, IN ... start writing the data */
  839. if (musb->ep0_state == MUSB_EP0_STAGE_TX)
  840. ep0_txstate(musb);
  841. /* sequence #3, no-data ... issue IN status */
  842. else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
  843. if (req->request.length)
  844. status = -EINVAL;
  845. else {
  846. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  847. musb_writew(regs, MUSB_CSR0,
  848. musb->ackpend | MUSB_CSR0_P_DATAEND);
  849. musb->ackpend = 0;
  850. musb_g_ep0_giveback(ep->musb, r);
  851. }
  852. /* else for sequence #2 (OUT), caller provides a buffer
  853. * before the next packet arrives. deferred responses
  854. * (after SETUP is acked) are racey.
  855. */
  856. } else if (musb->ackpend) {
  857. musb_writew(regs, MUSB_CSR0, musb->ackpend);
  858. musb->ackpend = 0;
  859. }
  860. cleanup:
  861. spin_unlock_irqrestore(&musb->lock, lockflags);
  862. return status;
  863. }
  864. static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
  865. {
  866. /* we just won't support this */
  867. return -EINVAL;
  868. }
  869. static int musb_g_ep0_halt(struct usb_ep *e, int value)
  870. {
  871. struct musb_ep *ep;
  872. struct musb *musb;
  873. void __iomem *base, *regs;
  874. unsigned long flags;
  875. int status;
  876. u16 csr;
  877. if (!e || !value)
  878. return -EINVAL;
  879. ep = to_musb_ep(e);
  880. musb = ep->musb;
  881. base = musb->mregs;
  882. regs = musb->control_ep->regs;
  883. status = 0;
  884. spin_lock_irqsave(&musb->lock, flags);
  885. if (!list_empty(&ep->req_list)) {
  886. status = -EBUSY;
  887. goto cleanup;
  888. }
  889. musb_ep_select(base, 0);
  890. csr = musb->ackpend;
  891. switch (musb->ep0_state) {
  892. /* Stalls are usually issued after parsing SETUP packet, either
  893. * directly in irq context from setup() or else later.
  894. */
  895. case MUSB_EP0_STAGE_TX: /* control-IN data */
  896. case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
  897. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  898. csr = musb_readw(regs, MUSB_CSR0);
  899. fallthrough;
  900. /* It's also OK to issue stalls during callbacks when a non-empty
  901. * DATA stage buffer has been read (or even written).
  902. */
  903. case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
  904. case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
  905. csr |= MUSB_CSR0_P_SENDSTALL;
  906. musb_writew(regs, MUSB_CSR0, csr);
  907. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  908. musb->ackpend = 0;
  909. break;
  910. default:
  911. musb_dbg(musb, "ep0 can't halt in state %d", musb->ep0_state);
  912. status = -EINVAL;
  913. }
  914. cleanup:
  915. spin_unlock_irqrestore(&musb->lock, flags);
  916. return status;
  917. }
  918. const struct usb_ep_ops musb_g_ep0_ops = {
  919. .enable = musb_g_ep0_enable,
  920. .disable = musb_g_ep0_disable,
  921. .alloc_request = musb_alloc_request,
  922. .free_request = musb_free_request,
  923. .queue = musb_g_ep0_queue,
  924. .dequeue = musb_g_ep0_dequeue,
  925. .set_halt = musb_g_ep0_halt,
  926. };