musb_gadget.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver peripheral support
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/list.h>
  12. #include <linux/timer.h>
  13. #include <linux/module.h>
  14. #include <linux/smp.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/delay.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/slab.h>
  19. #include "musb_core.h"
  20. #include "musb_trace.h"
  21. /* ----------------------------------------------------------------------- */
  22. #define is_buffer_mapped(req) (is_dma_capable() && \
  23. (req->map_state != UN_MAPPED))
  24. /* Maps the buffer to dma */
  25. static inline void map_dma_buffer(struct musb_request *request,
  26. struct musb *musb, struct musb_ep *musb_ep)
  27. {
  28. int compatible = true;
  29. struct dma_controller *dma = musb->dma_controller;
  30. request->map_state = UN_MAPPED;
  31. if (!is_dma_capable() || !musb_ep->dma)
  32. return;
  33. /* Check if DMA engine can handle this request.
  34. * DMA code must reject the USB request explicitly.
  35. * Default behaviour is to map the request.
  36. */
  37. if (dma->is_compatible)
  38. compatible = dma->is_compatible(musb_ep->dma,
  39. musb_ep->packet_sz, request->request.buf,
  40. request->request.length);
  41. if (!compatible)
  42. return;
  43. if (request->request.dma == DMA_ADDR_INVALID) {
  44. dma_addr_t dma_addr;
  45. int ret;
  46. dma_addr = dma_map_single(
  47. musb->controller,
  48. request->request.buf,
  49. request->request.length,
  50. request->tx
  51. ? DMA_TO_DEVICE
  52. : DMA_FROM_DEVICE);
  53. ret = dma_mapping_error(musb->controller, dma_addr);
  54. if (ret)
  55. return;
  56. request->request.dma = dma_addr;
  57. request->map_state = MUSB_MAPPED;
  58. } else {
  59. dma_sync_single_for_device(musb->controller,
  60. request->request.dma,
  61. request->request.length,
  62. request->tx
  63. ? DMA_TO_DEVICE
  64. : DMA_FROM_DEVICE);
  65. request->map_state = PRE_MAPPED;
  66. }
  67. }
  68. /* Unmap the buffer from dma and maps it back to cpu */
  69. static inline void unmap_dma_buffer(struct musb_request *request,
  70. struct musb *musb)
  71. {
  72. struct musb_ep *musb_ep = request->ep;
  73. if (!is_buffer_mapped(request) || !musb_ep->dma)
  74. return;
  75. if (request->request.dma == DMA_ADDR_INVALID) {
  76. dev_vdbg(musb->controller,
  77. "not unmapping a never mapped buffer\n");
  78. return;
  79. }
  80. if (request->map_state == MUSB_MAPPED) {
  81. dma_unmap_single(musb->controller,
  82. request->request.dma,
  83. request->request.length,
  84. request->tx
  85. ? DMA_TO_DEVICE
  86. : DMA_FROM_DEVICE);
  87. request->request.dma = DMA_ADDR_INVALID;
  88. } else { /* PRE_MAPPED */
  89. dma_sync_single_for_cpu(musb->controller,
  90. request->request.dma,
  91. request->request.length,
  92. request->tx
  93. ? DMA_TO_DEVICE
  94. : DMA_FROM_DEVICE);
  95. }
  96. request->map_state = UN_MAPPED;
  97. }
  98. /*
  99. * Immediately complete a request.
  100. *
  101. * @param request the request to complete
  102. * @param status the status to complete the request with
  103. * Context: controller locked, IRQs blocked.
  104. */
  105. void musb_g_giveback(
  106. struct musb_ep *ep,
  107. struct usb_request *request,
  108. int status)
  109. __releases(ep->musb->lock)
  110. __acquires(ep->musb->lock)
  111. {
  112. struct musb_request *req;
  113. struct musb *musb;
  114. int busy = ep->busy;
  115. req = to_musb_request(request);
  116. list_del(&req->list);
  117. if (req->request.status == -EINPROGRESS)
  118. req->request.status = status;
  119. musb = req->musb;
  120. ep->busy = 1;
  121. spin_unlock(&musb->lock);
  122. if (!dma_mapping_error(&musb->g.dev, request->dma))
  123. unmap_dma_buffer(req, musb);
  124. trace_musb_req_gb(req);
  125. usb_gadget_giveback_request(&req->ep->end_point, &req->request);
  126. spin_lock(&musb->lock);
  127. ep->busy = busy;
  128. }
  129. /* ----------------------------------------------------------------------- */
  130. /*
  131. * Abort requests queued to an endpoint using the status. Synchronous.
  132. * caller locked controller and blocked irqs, and selected this ep.
  133. */
  134. static void nuke(struct musb_ep *ep, const int status)
  135. {
  136. struct musb *musb = ep->musb;
  137. struct musb_request *req = NULL;
  138. void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
  139. ep->busy = 1;
  140. if (is_dma_capable() && ep->dma) {
  141. struct dma_controller *c = ep->musb->dma_controller;
  142. int value;
  143. if (ep->is_in) {
  144. /*
  145. * The programming guide says that we must not clear
  146. * the DMAMODE bit before DMAENAB, so we only
  147. * clear it in the second write...
  148. */
  149. musb_writew(epio, MUSB_TXCSR,
  150. MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
  151. musb_writew(epio, MUSB_TXCSR,
  152. 0 | MUSB_TXCSR_FLUSHFIFO);
  153. } else {
  154. musb_writew(epio, MUSB_RXCSR,
  155. 0 | MUSB_RXCSR_FLUSHFIFO);
  156. musb_writew(epio, MUSB_RXCSR,
  157. 0 | MUSB_RXCSR_FLUSHFIFO);
  158. }
  159. value = c->channel_abort(ep->dma);
  160. musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value);
  161. c->channel_release(ep->dma);
  162. ep->dma = NULL;
  163. }
  164. while (!list_empty(&ep->req_list)) {
  165. req = list_first_entry(&ep->req_list, struct musb_request, list);
  166. musb_g_giveback(ep, &req->request, status);
  167. }
  168. }
  169. /* ----------------------------------------------------------------------- */
  170. /* Data transfers - pure PIO, pure DMA, or mixed mode */
  171. /*
  172. * This assumes the separate CPPI engine is responding to DMA requests
  173. * from the usb core ... sequenced a bit differently from mentor dma.
  174. */
  175. static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
  176. {
  177. if (can_bulk_split(musb, ep->type))
  178. return ep->hw_ep->max_packet_sz_tx;
  179. else
  180. return ep->packet_sz;
  181. }
  182. /*
  183. * An endpoint is transmitting data. This can be called either from
  184. * the IRQ routine or from ep.queue() to kickstart a request on an
  185. * endpoint.
  186. *
  187. * Context: controller locked, IRQs blocked, endpoint selected
  188. */
  189. static void txstate(struct musb *musb, struct musb_request *req)
  190. {
  191. u8 epnum = req->epnum;
  192. struct musb_ep *musb_ep;
  193. void __iomem *epio = musb->endpoints[epnum].regs;
  194. struct usb_request *request;
  195. u16 fifo_count = 0, csr;
  196. int use_dma = 0;
  197. musb_ep = req->ep;
  198. /* Check if EP is disabled */
  199. if (!musb_ep->desc) {
  200. musb_dbg(musb, "ep:%s disabled - ignore request",
  201. musb_ep->end_point.name);
  202. return;
  203. }
  204. /* we shouldn't get here while DMA is active ... but we do ... */
  205. if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
  206. musb_dbg(musb, "dma pending...");
  207. return;
  208. }
  209. /* read TXCSR before */
  210. csr = musb_readw(epio, MUSB_TXCSR);
  211. request = &req->request;
  212. fifo_count = min(max_ep_writesize(musb, musb_ep),
  213. (int)(request->length - request->actual));
  214. if (csr & MUSB_TXCSR_TXPKTRDY) {
  215. musb_dbg(musb, "%s old packet still ready , txcsr %03x",
  216. musb_ep->end_point.name, csr);
  217. return;
  218. }
  219. if (csr & MUSB_TXCSR_P_SENDSTALL) {
  220. musb_dbg(musb, "%s stalling, txcsr %03x",
  221. musb_ep->end_point.name, csr);
  222. return;
  223. }
  224. musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x",
  225. epnum, musb_ep->packet_sz, fifo_count,
  226. csr);
  227. #ifndef CONFIG_MUSB_PIO_ONLY
  228. if (is_buffer_mapped(req)) {
  229. struct dma_controller *c = musb->dma_controller;
  230. size_t request_size;
  231. /* setup DMA, then program endpoint CSR */
  232. request_size = min_t(size_t, request->length - request->actual,
  233. musb_ep->dma->max_len);
  234. use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
  235. /* MUSB_TXCSR_P_ISO is still set correctly */
  236. if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) {
  237. if (request_size < musb_ep->packet_sz)
  238. musb_ep->dma->desired_mode = 0;
  239. else
  240. musb_ep->dma->desired_mode = 1;
  241. use_dma = use_dma && c->channel_program(
  242. musb_ep->dma, musb_ep->packet_sz,
  243. musb_ep->dma->desired_mode,
  244. request->dma + request->actual, request_size);
  245. if (use_dma) {
  246. if (musb_ep->dma->desired_mode == 0) {
  247. /*
  248. * We must not clear the DMAMODE bit
  249. * before the DMAENAB bit -- and the
  250. * latter doesn't always get cleared
  251. * before we get here...
  252. */
  253. csr &= ~(MUSB_TXCSR_AUTOSET
  254. | MUSB_TXCSR_DMAENAB);
  255. musb_writew(epio, MUSB_TXCSR, csr
  256. | MUSB_TXCSR_P_WZC_BITS);
  257. csr &= ~MUSB_TXCSR_DMAMODE;
  258. csr |= (MUSB_TXCSR_DMAENAB |
  259. MUSB_TXCSR_MODE);
  260. /* against programming guide */
  261. } else {
  262. csr |= (MUSB_TXCSR_DMAENAB
  263. | MUSB_TXCSR_DMAMODE
  264. | MUSB_TXCSR_MODE);
  265. /*
  266. * Enable Autoset according to table
  267. * below
  268. * bulk_split hb_mult Autoset_Enable
  269. * 0 0 Yes(Normal)
  270. * 0 >0 No(High BW ISO)
  271. * 1 0 Yes(HS bulk)
  272. * 1 >0 Yes(FS bulk)
  273. */
  274. if (!musb_ep->hb_mult ||
  275. can_bulk_split(musb,
  276. musb_ep->type))
  277. csr |= MUSB_TXCSR_AUTOSET;
  278. }
  279. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  280. musb_writew(epio, MUSB_TXCSR, csr);
  281. }
  282. }
  283. if (is_cppi_enabled(musb)) {
  284. /* program endpoint CSR first, then setup DMA */
  285. csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
  286. csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
  287. MUSB_TXCSR_MODE;
  288. musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS &
  289. ~MUSB_TXCSR_P_UNDERRUN) | csr);
  290. /* ensure writebuffer is empty */
  291. csr = musb_readw(epio, MUSB_TXCSR);
  292. /*
  293. * NOTE host side sets DMAENAB later than this; both are
  294. * OK since the transfer dma glue (between CPPI and
  295. * Mentor fifos) just tells CPPI it could start. Data
  296. * only moves to the USB TX fifo when both fifos are
  297. * ready.
  298. */
  299. /*
  300. * "mode" is irrelevant here; handle terminating ZLPs
  301. * like PIO does, since the hardware RNDIS mode seems
  302. * unreliable except for the
  303. * last-packet-is-already-short case.
  304. */
  305. use_dma = use_dma && c->channel_program(
  306. musb_ep->dma, musb_ep->packet_sz,
  307. 0,
  308. request->dma + request->actual,
  309. request_size);
  310. if (!use_dma) {
  311. c->channel_release(musb_ep->dma);
  312. musb_ep->dma = NULL;
  313. csr &= ~MUSB_TXCSR_DMAENAB;
  314. musb_writew(epio, MUSB_TXCSR, csr);
  315. /* invariant: prequest->buf is non-null */
  316. }
  317. } else if (tusb_dma_omap(musb))
  318. use_dma = use_dma && c->channel_program(
  319. musb_ep->dma, musb_ep->packet_sz,
  320. request->zero,
  321. request->dma + request->actual,
  322. request_size);
  323. }
  324. #endif
  325. if (!use_dma) {
  326. /*
  327. * Unmap the dma buffer back to cpu if dma channel
  328. * programming fails
  329. */
  330. unmap_dma_buffer(req, musb);
  331. musb_write_fifo(musb_ep->hw_ep, fifo_count,
  332. (u8 *) (request->buf + request->actual));
  333. request->actual += fifo_count;
  334. csr |= MUSB_TXCSR_TXPKTRDY;
  335. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  336. musb_writew(epio, MUSB_TXCSR, csr);
  337. }
  338. /* host may already have the data when this message shows... */
  339. musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d",
  340. musb_ep->end_point.name, use_dma ? "dma" : "pio",
  341. request->actual, request->length,
  342. musb_readw(epio, MUSB_TXCSR),
  343. fifo_count,
  344. musb_readw(epio, MUSB_TXMAXP));
  345. }
  346. /*
  347. * FIFO state update (e.g. data ready).
  348. * Called from IRQ, with controller locked.
  349. */
  350. void musb_g_tx(struct musb *musb, u8 epnum)
  351. {
  352. u16 csr;
  353. struct musb_request *req;
  354. struct usb_request *request;
  355. u8 __iomem *mbase = musb->mregs;
  356. struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
  357. void __iomem *epio = musb->endpoints[epnum].regs;
  358. struct dma_channel *dma;
  359. musb_ep_select(mbase, epnum);
  360. req = next_request(musb_ep);
  361. request = &req->request;
  362. csr = musb_readw(epio, MUSB_TXCSR);
  363. musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr);
  364. dma = is_dma_capable() ? musb_ep->dma : NULL;
  365. /*
  366. * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
  367. * probably rates reporting as a host error.
  368. */
  369. if (csr & MUSB_TXCSR_P_SENTSTALL) {
  370. csr |= MUSB_TXCSR_P_WZC_BITS;
  371. csr &= ~MUSB_TXCSR_P_SENTSTALL;
  372. musb_writew(epio, MUSB_TXCSR, csr);
  373. return;
  374. }
  375. if (csr & MUSB_TXCSR_P_UNDERRUN) {
  376. /* We NAKed, no big deal... little reason to care. */
  377. csr |= MUSB_TXCSR_P_WZC_BITS;
  378. csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
  379. musb_writew(epio, MUSB_TXCSR, csr);
  380. dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
  381. epnum, request);
  382. }
  383. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  384. /*
  385. * SHOULD NOT HAPPEN... has with CPPI though, after
  386. * changing SENDSTALL (and other cases); harmless?
  387. */
  388. musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name);
  389. return;
  390. }
  391. if (request) {
  392. trace_musb_req_tx(req);
  393. if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
  394. csr |= MUSB_TXCSR_P_WZC_BITS;
  395. csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
  396. MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
  397. musb_writew(epio, MUSB_TXCSR, csr);
  398. /* Ensure writebuffer is empty. */
  399. csr = musb_readw(epio, MUSB_TXCSR);
  400. request->actual += musb_ep->dma->actual_len;
  401. musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p",
  402. epnum, csr, musb_ep->dma->actual_len, request);
  403. }
  404. /*
  405. * First, maybe a terminating short packet. Some DMA
  406. * engines might handle this by themselves.
  407. */
  408. if ((request->zero && request->length)
  409. && (request->length % musb_ep->packet_sz == 0)
  410. && (request->actual == request->length)) {
  411. /*
  412. * On DMA completion, FIFO may not be
  413. * available yet...
  414. */
  415. if (csr & MUSB_TXCSR_TXPKTRDY)
  416. return;
  417. musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
  418. | MUSB_TXCSR_TXPKTRDY);
  419. request->zero = 0;
  420. }
  421. if (request->actual == request->length) {
  422. musb_g_giveback(musb_ep, request, 0);
  423. /*
  424. * In the giveback function the MUSB lock is
  425. * released and acquired after sometime. During
  426. * this time period the INDEX register could get
  427. * changed by the gadget_queue function especially
  428. * on SMP systems. Reselect the INDEX to be sure
  429. * we are reading/modifying the right registers
  430. */
  431. musb_ep_select(mbase, epnum);
  432. req = musb_ep->desc ? next_request(musb_ep) : NULL;
  433. if (!req) {
  434. musb_dbg(musb, "%s idle now",
  435. musb_ep->end_point.name);
  436. return;
  437. }
  438. }
  439. txstate(musb, req);
  440. }
  441. }
  442. /* ------------------------------------------------------------ */
  443. /*
  444. * Context: controller locked, IRQs blocked, endpoint selected
  445. */
  446. static void rxstate(struct musb *musb, struct musb_request *req)
  447. {
  448. const u8 epnum = req->epnum;
  449. struct usb_request *request = &req->request;
  450. struct musb_ep *musb_ep;
  451. void __iomem *epio = musb->endpoints[epnum].regs;
  452. unsigned len = 0;
  453. u16 fifo_count;
  454. u16 csr = musb_readw(epio, MUSB_RXCSR);
  455. struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
  456. u8 use_mode_1;
  457. if (hw_ep->is_shared_fifo)
  458. musb_ep = &hw_ep->ep_in;
  459. else
  460. musb_ep = &hw_ep->ep_out;
  461. fifo_count = musb_ep->packet_sz;
  462. /* Check if EP is disabled */
  463. if (!musb_ep->desc) {
  464. musb_dbg(musb, "ep:%s disabled - ignore request",
  465. musb_ep->end_point.name);
  466. return;
  467. }
  468. /* We shouldn't get here while DMA is active, but we do... */
  469. if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
  470. musb_dbg(musb, "DMA pending...");
  471. return;
  472. }
  473. if (csr & MUSB_RXCSR_P_SENDSTALL) {
  474. musb_dbg(musb, "%s stalling, RXCSR %04x",
  475. musb_ep->end_point.name, csr);
  476. return;
  477. }
  478. if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
  479. struct dma_controller *c = musb->dma_controller;
  480. struct dma_channel *channel = musb_ep->dma;
  481. /* NOTE: CPPI won't actually stop advancing the DMA
  482. * queue after short packet transfers, so this is almost
  483. * always going to run as IRQ-per-packet DMA so that
  484. * faults will be handled correctly.
  485. */
  486. if (c->channel_program(channel,
  487. musb_ep->packet_sz,
  488. !request->short_not_ok,
  489. request->dma + request->actual,
  490. request->length - request->actual)) {
  491. /* make sure that if an rxpkt arrived after the irq,
  492. * the cppi engine will be ready to take it as soon
  493. * as DMA is enabled
  494. */
  495. csr &= ~(MUSB_RXCSR_AUTOCLEAR
  496. | MUSB_RXCSR_DMAMODE);
  497. csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
  498. musb_writew(epio, MUSB_RXCSR, csr);
  499. return;
  500. }
  501. }
  502. if (csr & MUSB_RXCSR_RXPKTRDY) {
  503. fifo_count = musb_readw(epio, MUSB_RXCOUNT);
  504. /*
  505. * Enable Mode 1 on RX transfers only when short_not_ok flag
  506. * is set. Currently short_not_ok flag is set only from
  507. * file_storage and f_mass_storage drivers
  508. */
  509. if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
  510. use_mode_1 = 1;
  511. else
  512. use_mode_1 = 0;
  513. if (request->actual < request->length) {
  514. if (!is_buffer_mapped(req))
  515. goto buffer_aint_mapped;
  516. if (musb_dma_inventra(musb)) {
  517. struct dma_controller *c;
  518. struct dma_channel *channel;
  519. int use_dma = 0;
  520. unsigned int transfer_size;
  521. c = musb->dma_controller;
  522. channel = musb_ep->dma;
  523. /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
  524. * mode 0 only. So we do not get endpoint interrupts due to DMA
  525. * completion. We only get interrupts from DMA controller.
  526. *
  527. * We could operate in DMA mode 1 if we knew the size of the tranfer
  528. * in advance. For mass storage class, request->length = what the host
  529. * sends, so that'd work. But for pretty much everything else,
  530. * request->length is routinely more than what the host sends. For
  531. * most these gadgets, end of is signified either by a short packet,
  532. * or filling the last byte of the buffer. (Sending extra data in
  533. * that last pckate should trigger an overflow fault.) But in mode 1,
  534. * we don't get DMA completion interrupt for short packets.
  535. *
  536. * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
  537. * to get endpoint interrupt on every DMA req, but that didn't seem
  538. * to work reliably.
  539. *
  540. * REVISIT an updated g_file_storage can set req->short_not_ok, which
  541. * then becomes usable as a runtime "use mode 1" hint...
  542. */
  543. /* Experimental: Mode1 works with mass storage use cases */
  544. if (use_mode_1) {
  545. csr |= MUSB_RXCSR_AUTOCLEAR;
  546. musb_writew(epio, MUSB_RXCSR, csr);
  547. csr |= MUSB_RXCSR_DMAENAB;
  548. musb_writew(epio, MUSB_RXCSR, csr);
  549. /*
  550. * this special sequence (enabling and then
  551. * disabling MUSB_RXCSR_DMAMODE) is required
  552. * to get DMAReq to activate
  553. */
  554. musb_writew(epio, MUSB_RXCSR,
  555. csr | MUSB_RXCSR_DMAMODE);
  556. musb_writew(epio, MUSB_RXCSR, csr);
  557. transfer_size = min_t(unsigned int,
  558. request->length -
  559. request->actual,
  560. channel->max_len);
  561. musb_ep->dma->desired_mode = 1;
  562. } else {
  563. if (!musb_ep->hb_mult &&
  564. musb_ep->hw_ep->rx_double_buffered)
  565. csr |= MUSB_RXCSR_AUTOCLEAR;
  566. csr |= MUSB_RXCSR_DMAENAB;
  567. musb_writew(epio, MUSB_RXCSR, csr);
  568. transfer_size = min(request->length - request->actual,
  569. (unsigned)fifo_count);
  570. musb_ep->dma->desired_mode = 0;
  571. }
  572. use_dma = c->channel_program(
  573. channel,
  574. musb_ep->packet_sz,
  575. channel->desired_mode,
  576. request->dma
  577. + request->actual,
  578. transfer_size);
  579. if (use_dma)
  580. return;
  581. }
  582. if ((musb_dma_ux500(musb)) &&
  583. (request->actual < request->length)) {
  584. struct dma_controller *c;
  585. struct dma_channel *channel;
  586. unsigned int transfer_size = 0;
  587. c = musb->dma_controller;
  588. channel = musb_ep->dma;
  589. /* In case first packet is short */
  590. if (fifo_count < musb_ep->packet_sz)
  591. transfer_size = fifo_count;
  592. else if (request->short_not_ok)
  593. transfer_size = min_t(unsigned int,
  594. request->length -
  595. request->actual,
  596. channel->max_len);
  597. else
  598. transfer_size = min_t(unsigned int,
  599. request->length -
  600. request->actual,
  601. (unsigned)fifo_count);
  602. csr &= ~MUSB_RXCSR_DMAMODE;
  603. csr |= (MUSB_RXCSR_DMAENAB |
  604. MUSB_RXCSR_AUTOCLEAR);
  605. musb_writew(epio, MUSB_RXCSR, csr);
  606. if (transfer_size <= musb_ep->packet_sz) {
  607. musb_ep->dma->desired_mode = 0;
  608. } else {
  609. musb_ep->dma->desired_mode = 1;
  610. /* Mode must be set after DMAENAB */
  611. csr |= MUSB_RXCSR_DMAMODE;
  612. musb_writew(epio, MUSB_RXCSR, csr);
  613. }
  614. if (c->channel_program(channel,
  615. musb_ep->packet_sz,
  616. channel->desired_mode,
  617. request->dma
  618. + request->actual,
  619. transfer_size))
  620. return;
  621. }
  622. len = request->length - request->actual;
  623. musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d",
  624. musb_ep->end_point.name,
  625. fifo_count, len,
  626. musb_ep->packet_sz);
  627. fifo_count = min_t(unsigned, len, fifo_count);
  628. if (tusb_dma_omap(musb)) {
  629. struct dma_controller *c = musb->dma_controller;
  630. struct dma_channel *channel = musb_ep->dma;
  631. u32 dma_addr = request->dma + request->actual;
  632. int ret;
  633. ret = c->channel_program(channel,
  634. musb_ep->packet_sz,
  635. channel->desired_mode,
  636. dma_addr,
  637. fifo_count);
  638. if (ret)
  639. return;
  640. }
  641. /*
  642. * Unmap the dma buffer back to cpu if dma channel
  643. * programming fails. This buffer is mapped if the
  644. * channel allocation is successful
  645. */
  646. unmap_dma_buffer(req, musb);
  647. /*
  648. * Clear DMAENAB and AUTOCLEAR for the
  649. * PIO mode transfer
  650. */
  651. csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
  652. musb_writew(epio, MUSB_RXCSR, csr);
  653. buffer_aint_mapped:
  654. musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
  655. (request->buf + request->actual));
  656. request->actual += fifo_count;
  657. /* REVISIT if we left anything in the fifo, flush
  658. * it and report -EOVERFLOW
  659. */
  660. /* ack the read! */
  661. csr |= MUSB_RXCSR_P_WZC_BITS;
  662. csr &= ~MUSB_RXCSR_RXPKTRDY;
  663. musb_writew(epio, MUSB_RXCSR, csr);
  664. }
  665. }
  666. /* reach the end or short packet detected */
  667. if (request->actual == request->length ||
  668. fifo_count < musb_ep->packet_sz)
  669. musb_g_giveback(musb_ep, request, 0);
  670. }
  671. /*
  672. * Data ready for a request; called from IRQ
  673. */
  674. void musb_g_rx(struct musb *musb, u8 epnum)
  675. {
  676. u16 csr;
  677. struct musb_request *req;
  678. struct usb_request *request;
  679. void __iomem *mbase = musb->mregs;
  680. struct musb_ep *musb_ep;
  681. void __iomem *epio = musb->endpoints[epnum].regs;
  682. struct dma_channel *dma;
  683. struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
  684. if (hw_ep->is_shared_fifo)
  685. musb_ep = &hw_ep->ep_in;
  686. else
  687. musb_ep = &hw_ep->ep_out;
  688. musb_ep_select(mbase, epnum);
  689. req = next_request(musb_ep);
  690. if (!req)
  691. return;
  692. trace_musb_req_rx(req);
  693. request = &req->request;
  694. csr = musb_readw(epio, MUSB_RXCSR);
  695. dma = is_dma_capable() ? musb_ep->dma : NULL;
  696. musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name,
  697. csr, dma ? " (dma)" : "", request);
  698. if (csr & MUSB_RXCSR_P_SENTSTALL) {
  699. csr |= MUSB_RXCSR_P_WZC_BITS;
  700. csr &= ~MUSB_RXCSR_P_SENTSTALL;
  701. musb_writew(epio, MUSB_RXCSR, csr);
  702. return;
  703. }
  704. if (csr & MUSB_RXCSR_P_OVERRUN) {
  705. /* csr |= MUSB_RXCSR_P_WZC_BITS; */
  706. csr &= ~MUSB_RXCSR_P_OVERRUN;
  707. musb_writew(epio, MUSB_RXCSR, csr);
  708. musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request);
  709. if (request->status == -EINPROGRESS)
  710. request->status = -EOVERFLOW;
  711. }
  712. if (csr & MUSB_RXCSR_INCOMPRX) {
  713. /* REVISIT not necessarily an error */
  714. musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name);
  715. }
  716. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  717. /* "should not happen"; likely RXPKTRDY pending for DMA */
  718. musb_dbg(musb, "%s busy, csr %04x",
  719. musb_ep->end_point.name, csr);
  720. return;
  721. }
  722. if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
  723. csr &= ~(MUSB_RXCSR_AUTOCLEAR
  724. | MUSB_RXCSR_DMAENAB
  725. | MUSB_RXCSR_DMAMODE);
  726. musb_writew(epio, MUSB_RXCSR,
  727. MUSB_RXCSR_P_WZC_BITS | csr);
  728. request->actual += musb_ep->dma->actual_len;
  729. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
  730. defined(CONFIG_USB_UX500_DMA)
  731. /* Autoclear doesn't clear RxPktRdy for short packets */
  732. if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
  733. || (dma->actual_len
  734. & (musb_ep->packet_sz - 1))) {
  735. /* ack the read! */
  736. csr &= ~MUSB_RXCSR_RXPKTRDY;
  737. musb_writew(epio, MUSB_RXCSR, csr);
  738. }
  739. /* incomplete, and not short? wait for next IN packet */
  740. if ((request->actual < request->length)
  741. && (musb_ep->dma->actual_len
  742. == musb_ep->packet_sz)) {
  743. /* In double buffer case, continue to unload fifo if
  744. * there is Rx packet in FIFO.
  745. **/
  746. csr = musb_readw(epio, MUSB_RXCSR);
  747. if ((csr & MUSB_RXCSR_RXPKTRDY) &&
  748. hw_ep->rx_double_buffered)
  749. goto exit;
  750. return;
  751. }
  752. #endif
  753. musb_g_giveback(musb_ep, request, 0);
  754. /*
  755. * In the giveback function the MUSB lock is
  756. * released and acquired after sometime. During
  757. * this time period the INDEX register could get
  758. * changed by the gadget_queue function especially
  759. * on SMP systems. Reselect the INDEX to be sure
  760. * we are reading/modifying the right registers
  761. */
  762. musb_ep_select(mbase, epnum);
  763. req = next_request(musb_ep);
  764. if (!req)
  765. return;
  766. }
  767. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
  768. defined(CONFIG_USB_UX500_DMA)
  769. exit:
  770. #endif
  771. /* Analyze request */
  772. rxstate(musb, req);
  773. }
  774. /* ------------------------------------------------------------ */
  775. static int musb_gadget_enable(struct usb_ep *ep,
  776. const struct usb_endpoint_descriptor *desc)
  777. {
  778. unsigned long flags;
  779. struct musb_ep *musb_ep;
  780. struct musb_hw_ep *hw_ep;
  781. void __iomem *regs;
  782. struct musb *musb;
  783. void __iomem *mbase;
  784. u8 epnum;
  785. u16 csr;
  786. unsigned tmp;
  787. int status = -EINVAL;
  788. if (!ep || !desc)
  789. return -EINVAL;
  790. musb_ep = to_musb_ep(ep);
  791. hw_ep = musb_ep->hw_ep;
  792. regs = hw_ep->regs;
  793. musb = musb_ep->musb;
  794. mbase = musb->mregs;
  795. epnum = musb_ep->current_epnum;
  796. spin_lock_irqsave(&musb->lock, flags);
  797. if (musb_ep->desc) {
  798. status = -EBUSY;
  799. goto fail;
  800. }
  801. musb_ep->type = usb_endpoint_type(desc);
  802. /* check direction and (later) maxpacket size against endpoint */
  803. if (usb_endpoint_num(desc) != epnum)
  804. goto fail;
  805. /* REVISIT this rules out high bandwidth periodic transfers */
  806. tmp = usb_endpoint_maxp_mult(desc) - 1;
  807. if (tmp) {
  808. int ok;
  809. if (usb_endpoint_dir_in(desc))
  810. ok = musb->hb_iso_tx;
  811. else
  812. ok = musb->hb_iso_rx;
  813. if (!ok) {
  814. musb_dbg(musb, "no support for high bandwidth ISO");
  815. goto fail;
  816. }
  817. musb_ep->hb_mult = tmp;
  818. } else {
  819. musb_ep->hb_mult = 0;
  820. }
  821. musb_ep->packet_sz = usb_endpoint_maxp(desc);
  822. tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
  823. /* enable the interrupts for the endpoint, set the endpoint
  824. * packet size (or fail), set the mode, clear the fifo
  825. */
  826. musb_ep_select(mbase, epnum);
  827. if (usb_endpoint_dir_in(desc)) {
  828. if (hw_ep->is_shared_fifo)
  829. musb_ep->is_in = 1;
  830. if (!musb_ep->is_in)
  831. goto fail;
  832. if (tmp > hw_ep->max_packet_sz_tx) {
  833. musb_dbg(musb, "packet size beyond hardware FIFO size");
  834. goto fail;
  835. }
  836. musb->intrtxe |= (1 << epnum);
  837. musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
  838. /* REVISIT if can_bulk_split(), use by updating "tmp";
  839. * likewise high bandwidth periodic tx
  840. */
  841. /* Set TXMAXP with the FIFO size of the endpoint
  842. * to disable double buffering mode.
  843. */
  844. if (can_bulk_split(musb, musb_ep->type))
  845. musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
  846. musb_ep->packet_sz) - 1;
  847. musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
  848. | (musb_ep->hb_mult << 11));
  849. csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
  850. if (musb_readw(regs, MUSB_TXCSR)
  851. & MUSB_TXCSR_FIFONOTEMPTY)
  852. csr |= MUSB_TXCSR_FLUSHFIFO;
  853. if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
  854. csr |= MUSB_TXCSR_P_ISO;
  855. /* set twice in case of double buffering */
  856. musb_writew(regs, MUSB_TXCSR, csr);
  857. /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
  858. musb_writew(regs, MUSB_TXCSR, csr);
  859. } else {
  860. if (hw_ep->is_shared_fifo)
  861. musb_ep->is_in = 0;
  862. if (musb_ep->is_in)
  863. goto fail;
  864. if (tmp > hw_ep->max_packet_sz_rx) {
  865. musb_dbg(musb, "packet size beyond hardware FIFO size");
  866. goto fail;
  867. }
  868. musb->intrrxe |= (1 << epnum);
  869. musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
  870. /* REVISIT if can_bulk_combine() use by updating "tmp"
  871. * likewise high bandwidth periodic rx
  872. */
  873. /* Set RXMAXP with the FIFO size of the endpoint
  874. * to disable double buffering mode.
  875. */
  876. musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
  877. | (musb_ep->hb_mult << 11));
  878. /* force shared fifo to OUT-only mode */
  879. if (hw_ep->is_shared_fifo) {
  880. csr = musb_readw(regs, MUSB_TXCSR);
  881. csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
  882. musb_writew(regs, MUSB_TXCSR, csr);
  883. }
  884. csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
  885. if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
  886. csr |= MUSB_RXCSR_P_ISO;
  887. else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
  888. csr |= MUSB_RXCSR_DISNYET;
  889. /* set twice in case of double buffering */
  890. musb_writew(regs, MUSB_RXCSR, csr);
  891. musb_writew(regs, MUSB_RXCSR, csr);
  892. }
  893. /* NOTE: all the I/O code _should_ work fine without DMA, in case
  894. * for some reason you run out of channels here.
  895. */
  896. if (is_dma_capable() && musb->dma_controller) {
  897. struct dma_controller *c = musb->dma_controller;
  898. musb_ep->dma = c->channel_alloc(c, hw_ep,
  899. (desc->bEndpointAddress & USB_DIR_IN));
  900. } else
  901. musb_ep->dma = NULL;
  902. musb_ep->desc = desc;
  903. musb_ep->busy = 0;
  904. musb_ep->wedged = 0;
  905. status = 0;
  906. pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
  907. musb_driver_name, musb_ep->end_point.name,
  908. musb_ep_xfertype_string(musb_ep->type),
  909. musb_ep->is_in ? "IN" : "OUT",
  910. musb_ep->dma ? "dma, " : "",
  911. musb_ep->packet_sz);
  912. schedule_delayed_work(&musb->irq_work, 0);
  913. fail:
  914. spin_unlock_irqrestore(&musb->lock, flags);
  915. return status;
  916. }
  917. /*
  918. * Disable an endpoint flushing all requests queued.
  919. */
  920. static int musb_gadget_disable(struct usb_ep *ep)
  921. {
  922. unsigned long flags;
  923. struct musb *musb;
  924. u8 epnum;
  925. struct musb_ep *musb_ep;
  926. void __iomem *epio;
  927. musb_ep = to_musb_ep(ep);
  928. musb = musb_ep->musb;
  929. epnum = musb_ep->current_epnum;
  930. epio = musb->endpoints[epnum].regs;
  931. spin_lock_irqsave(&musb->lock, flags);
  932. musb_ep_select(musb->mregs, epnum);
  933. /* zero the endpoint sizes */
  934. if (musb_ep->is_in) {
  935. musb->intrtxe &= ~(1 << epnum);
  936. musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
  937. musb_writew(epio, MUSB_TXMAXP, 0);
  938. } else {
  939. musb->intrrxe &= ~(1 << epnum);
  940. musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
  941. musb_writew(epio, MUSB_RXMAXP, 0);
  942. }
  943. /* abort all pending DMA and requests */
  944. nuke(musb_ep, -ESHUTDOWN);
  945. musb_ep->desc = NULL;
  946. musb_ep->end_point.desc = NULL;
  947. schedule_delayed_work(&musb->irq_work, 0);
  948. spin_unlock_irqrestore(&(musb->lock), flags);
  949. musb_dbg(musb, "%s", musb_ep->end_point.name);
  950. return 0;
  951. }
  952. /*
  953. * Allocate a request for an endpoint.
  954. * Reused by ep0 code.
  955. */
  956. struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  957. {
  958. struct musb_ep *musb_ep = to_musb_ep(ep);
  959. struct musb_request *request = NULL;
  960. request = kzalloc(sizeof *request, gfp_flags);
  961. if (!request)
  962. return NULL;
  963. request->request.dma = DMA_ADDR_INVALID;
  964. request->epnum = musb_ep->current_epnum;
  965. request->ep = musb_ep;
  966. trace_musb_req_alloc(request);
  967. return &request->request;
  968. }
  969. /*
  970. * Free a request
  971. * Reused by ep0 code.
  972. */
  973. void musb_free_request(struct usb_ep *ep, struct usb_request *req)
  974. {
  975. struct musb_request *request = to_musb_request(req);
  976. trace_musb_req_free(request);
  977. kfree(request);
  978. }
  979. static LIST_HEAD(buffers);
  980. struct free_record {
  981. struct list_head list;
  982. struct device *dev;
  983. unsigned bytes;
  984. dma_addr_t dma;
  985. };
  986. /*
  987. * Context: controller locked, IRQs blocked.
  988. */
  989. void musb_ep_restart(struct musb *musb, struct musb_request *req)
  990. {
  991. trace_musb_req_start(req);
  992. musb_ep_select(musb->mregs, req->epnum);
  993. if (req->tx)
  994. txstate(musb, req);
  995. else
  996. rxstate(musb, req);
  997. }
  998. static int musb_ep_restart_resume_work(struct musb *musb, void *data)
  999. {
  1000. struct musb_request *req = data;
  1001. musb_ep_restart(musb, req);
  1002. return 0;
  1003. }
  1004. static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
  1005. gfp_t gfp_flags)
  1006. {
  1007. struct musb_ep *musb_ep;
  1008. struct musb_request *request;
  1009. struct musb *musb;
  1010. int status;
  1011. unsigned long lockflags;
  1012. if (!ep || !req)
  1013. return -EINVAL;
  1014. if (!req->buf)
  1015. return -ENODATA;
  1016. musb_ep = to_musb_ep(ep);
  1017. musb = musb_ep->musb;
  1018. request = to_musb_request(req);
  1019. request->musb = musb;
  1020. if (request->ep != musb_ep)
  1021. return -EINVAL;
  1022. status = pm_runtime_get(musb->controller);
  1023. if ((status != -EINPROGRESS) && status < 0) {
  1024. dev_err(musb->controller,
  1025. "pm runtime get failed in %s\n",
  1026. __func__);
  1027. pm_runtime_put_noidle(musb->controller);
  1028. return status;
  1029. }
  1030. status = 0;
  1031. trace_musb_req_enq(request);
  1032. /* request is mine now... */
  1033. request->request.actual = 0;
  1034. request->request.status = -EINPROGRESS;
  1035. request->epnum = musb_ep->current_epnum;
  1036. request->tx = musb_ep->is_in;
  1037. map_dma_buffer(request, musb, musb_ep);
  1038. spin_lock_irqsave(&musb->lock, lockflags);
  1039. /* don't queue if the ep is down */
  1040. if (!musb_ep->desc) {
  1041. musb_dbg(musb, "req %p queued to %s while ep %s",
  1042. req, ep->name, "disabled");
  1043. status = -ESHUTDOWN;
  1044. unmap_dma_buffer(request, musb);
  1045. goto unlock;
  1046. }
  1047. /* add request to the list */
  1048. list_add_tail(&request->list, &musb_ep->req_list);
  1049. /* it this is the head of the queue, start i/o ... */
  1050. if (!musb_ep->busy && &request->list == musb_ep->req_list.next) {
  1051. status = musb_queue_resume_work(musb,
  1052. musb_ep_restart_resume_work,
  1053. request);
  1054. if (status < 0) {
  1055. dev_err(musb->controller, "%s resume work: %i\n",
  1056. __func__, status);
  1057. list_del(&request->list);
  1058. }
  1059. }
  1060. unlock:
  1061. spin_unlock_irqrestore(&musb->lock, lockflags);
  1062. pm_runtime_mark_last_busy(musb->controller);
  1063. pm_runtime_put_autosuspend(musb->controller);
  1064. return status;
  1065. }
  1066. static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
  1067. {
  1068. struct musb_ep *musb_ep = to_musb_ep(ep);
  1069. struct musb_request *req = to_musb_request(request);
  1070. struct musb_request *r;
  1071. unsigned long flags;
  1072. int status = 0;
  1073. struct musb *musb = musb_ep->musb;
  1074. if (!ep || !request || req->ep != musb_ep)
  1075. return -EINVAL;
  1076. trace_musb_req_deq(req);
  1077. spin_lock_irqsave(&musb->lock, flags);
  1078. list_for_each_entry(r, &musb_ep->req_list, list) {
  1079. if (r == req)
  1080. break;
  1081. }
  1082. if (r != req) {
  1083. dev_err(musb->controller, "request %p not queued to %s\n",
  1084. request, ep->name);
  1085. status = -EINVAL;
  1086. goto done;
  1087. }
  1088. /* if the hardware doesn't have the request, easy ... */
  1089. if (musb_ep->req_list.next != &req->list || musb_ep->busy)
  1090. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1091. /* ... else abort the dma transfer ... */
  1092. else if (is_dma_capable() && musb_ep->dma) {
  1093. struct dma_controller *c = musb->dma_controller;
  1094. musb_ep_select(musb->mregs, musb_ep->current_epnum);
  1095. if (c->channel_abort)
  1096. status = c->channel_abort(musb_ep->dma);
  1097. else
  1098. status = -EBUSY;
  1099. if (status == 0)
  1100. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1101. } else {
  1102. /* NOTE: by sticking to easily tested hardware/driver states,
  1103. * we leave counting of in-flight packets imprecise.
  1104. */
  1105. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1106. }
  1107. done:
  1108. spin_unlock_irqrestore(&musb->lock, flags);
  1109. return status;
  1110. }
  1111. /*
  1112. * Set or clear the halt bit of an endpoint. A halted endpoint won't tx/rx any
  1113. * data but will queue requests.
  1114. *
  1115. * exported to ep0 code
  1116. */
  1117. static int musb_gadget_set_halt(struct usb_ep *ep, int value)
  1118. {
  1119. struct musb_ep *musb_ep = to_musb_ep(ep);
  1120. u8 epnum = musb_ep->current_epnum;
  1121. struct musb *musb = musb_ep->musb;
  1122. void __iomem *epio = musb->endpoints[epnum].regs;
  1123. void __iomem *mbase;
  1124. unsigned long flags;
  1125. u16 csr;
  1126. struct musb_request *request;
  1127. int status = 0;
  1128. if (!ep)
  1129. return -EINVAL;
  1130. mbase = musb->mregs;
  1131. spin_lock_irqsave(&musb->lock, flags);
  1132. if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
  1133. status = -EINVAL;
  1134. goto done;
  1135. }
  1136. musb_ep_select(mbase, epnum);
  1137. request = next_request(musb_ep);
  1138. if (value) {
  1139. if (request) {
  1140. musb_dbg(musb, "request in progress, cannot halt %s",
  1141. ep->name);
  1142. status = -EAGAIN;
  1143. goto done;
  1144. }
  1145. /* Cannot portably stall with non-empty FIFO */
  1146. if (musb_ep->is_in) {
  1147. csr = musb_readw(epio, MUSB_TXCSR);
  1148. if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  1149. musb_dbg(musb, "FIFO busy, cannot halt %s",
  1150. ep->name);
  1151. status = -EAGAIN;
  1152. goto done;
  1153. }
  1154. }
  1155. } else
  1156. musb_ep->wedged = 0;
  1157. /* set/clear the stall and toggle bits */
  1158. musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear");
  1159. if (musb_ep->is_in) {
  1160. csr = musb_readw(epio, MUSB_TXCSR);
  1161. csr |= MUSB_TXCSR_P_WZC_BITS
  1162. | MUSB_TXCSR_CLRDATATOG;
  1163. if (value)
  1164. csr |= MUSB_TXCSR_P_SENDSTALL;
  1165. else
  1166. csr &= ~(MUSB_TXCSR_P_SENDSTALL
  1167. | MUSB_TXCSR_P_SENTSTALL);
  1168. csr &= ~MUSB_TXCSR_TXPKTRDY;
  1169. musb_writew(epio, MUSB_TXCSR, csr);
  1170. } else {
  1171. csr = musb_readw(epio, MUSB_RXCSR);
  1172. csr |= MUSB_RXCSR_P_WZC_BITS
  1173. | MUSB_RXCSR_FLUSHFIFO
  1174. | MUSB_RXCSR_CLRDATATOG;
  1175. if (value)
  1176. csr |= MUSB_RXCSR_P_SENDSTALL;
  1177. else
  1178. csr &= ~(MUSB_RXCSR_P_SENDSTALL
  1179. | MUSB_RXCSR_P_SENTSTALL);
  1180. musb_writew(epio, MUSB_RXCSR, csr);
  1181. }
  1182. /* maybe start the first request in the queue */
  1183. if (!musb_ep->busy && !value && request) {
  1184. musb_dbg(musb, "restarting the request");
  1185. musb_ep_restart(musb, request);
  1186. }
  1187. done:
  1188. spin_unlock_irqrestore(&musb->lock, flags);
  1189. return status;
  1190. }
  1191. /*
  1192. * Sets the halt feature with the clear requests ignored
  1193. */
  1194. static int musb_gadget_set_wedge(struct usb_ep *ep)
  1195. {
  1196. struct musb_ep *musb_ep = to_musb_ep(ep);
  1197. if (!ep)
  1198. return -EINVAL;
  1199. musb_ep->wedged = 1;
  1200. return usb_ep_set_halt(ep);
  1201. }
  1202. static int musb_gadget_fifo_status(struct usb_ep *ep)
  1203. {
  1204. struct musb_ep *musb_ep = to_musb_ep(ep);
  1205. void __iomem *epio = musb_ep->hw_ep->regs;
  1206. int retval = -EINVAL;
  1207. if (musb_ep->desc && !musb_ep->is_in) {
  1208. struct musb *musb = musb_ep->musb;
  1209. int epnum = musb_ep->current_epnum;
  1210. void __iomem *mbase = musb->mregs;
  1211. unsigned long flags;
  1212. spin_lock_irqsave(&musb->lock, flags);
  1213. musb_ep_select(mbase, epnum);
  1214. /* FIXME return zero unless RXPKTRDY is set */
  1215. retval = musb_readw(epio, MUSB_RXCOUNT);
  1216. spin_unlock_irqrestore(&musb->lock, flags);
  1217. }
  1218. return retval;
  1219. }
  1220. static void musb_gadget_fifo_flush(struct usb_ep *ep)
  1221. {
  1222. struct musb_ep *musb_ep = to_musb_ep(ep);
  1223. struct musb *musb = musb_ep->musb;
  1224. u8 epnum = musb_ep->current_epnum;
  1225. void __iomem *epio = musb->endpoints[epnum].regs;
  1226. void __iomem *mbase;
  1227. unsigned long flags;
  1228. u16 csr;
  1229. mbase = musb->mregs;
  1230. spin_lock_irqsave(&musb->lock, flags);
  1231. musb_ep_select(mbase, (u8) epnum);
  1232. /* disable interrupts */
  1233. musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
  1234. if (musb_ep->is_in) {
  1235. csr = musb_readw(epio, MUSB_TXCSR);
  1236. if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  1237. csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
  1238. /*
  1239. * Setting both TXPKTRDY and FLUSHFIFO makes controller
  1240. * to interrupt current FIFO loading, but not flushing
  1241. * the already loaded ones.
  1242. */
  1243. csr &= ~MUSB_TXCSR_TXPKTRDY;
  1244. musb_writew(epio, MUSB_TXCSR, csr);
  1245. /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
  1246. musb_writew(epio, MUSB_TXCSR, csr);
  1247. }
  1248. } else {
  1249. csr = musb_readw(epio, MUSB_RXCSR);
  1250. csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
  1251. musb_writew(epio, MUSB_RXCSR, csr);
  1252. musb_writew(epio, MUSB_RXCSR, csr);
  1253. }
  1254. /* re-enable interrupt */
  1255. musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
  1256. spin_unlock_irqrestore(&musb->lock, flags);
  1257. }
  1258. static const struct usb_ep_ops musb_ep_ops = {
  1259. .enable = musb_gadget_enable,
  1260. .disable = musb_gadget_disable,
  1261. .alloc_request = musb_alloc_request,
  1262. .free_request = musb_free_request,
  1263. .queue = musb_gadget_queue,
  1264. .dequeue = musb_gadget_dequeue,
  1265. .set_halt = musb_gadget_set_halt,
  1266. .set_wedge = musb_gadget_set_wedge,
  1267. .fifo_status = musb_gadget_fifo_status,
  1268. .fifo_flush = musb_gadget_fifo_flush
  1269. };
  1270. /* ----------------------------------------------------------------------- */
  1271. static int musb_gadget_get_frame(struct usb_gadget *gadget)
  1272. {
  1273. struct musb *musb = gadget_to_musb(gadget);
  1274. return (int)musb_readw(musb->mregs, MUSB_FRAME);
  1275. }
  1276. static int musb_gadget_wakeup(struct usb_gadget *gadget)
  1277. {
  1278. struct musb *musb = gadget_to_musb(gadget);
  1279. void __iomem *mregs = musb->mregs;
  1280. unsigned long flags;
  1281. int status = -EINVAL;
  1282. u8 power, devctl;
  1283. int retries;
  1284. spin_lock_irqsave(&musb->lock, flags);
  1285. switch (musb->xceiv->otg->state) {
  1286. case OTG_STATE_B_PERIPHERAL:
  1287. /* NOTE: OTG state machine doesn't include B_SUSPENDED;
  1288. * that's part of the standard usb 1.1 state machine, and
  1289. * doesn't affect OTG transitions.
  1290. */
  1291. if (musb->may_wakeup && musb->is_suspended)
  1292. break;
  1293. goto done;
  1294. case OTG_STATE_B_IDLE:
  1295. /* Start SRP ... OTG not required. */
  1296. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1297. musb_dbg(musb, "Sending SRP: devctl: %02x", devctl);
  1298. devctl |= MUSB_DEVCTL_SESSION;
  1299. musb_writeb(mregs, MUSB_DEVCTL, devctl);
  1300. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1301. retries = 100;
  1302. while (!(devctl & MUSB_DEVCTL_SESSION)) {
  1303. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1304. if (retries-- < 1)
  1305. break;
  1306. }
  1307. retries = 10000;
  1308. while (devctl & MUSB_DEVCTL_SESSION) {
  1309. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1310. if (retries-- < 1)
  1311. break;
  1312. }
  1313. spin_unlock_irqrestore(&musb->lock, flags);
  1314. otg_start_srp(musb->xceiv->otg);
  1315. spin_lock_irqsave(&musb->lock, flags);
  1316. /* Block idling for at least 1s */
  1317. musb_platform_try_idle(musb,
  1318. jiffies + msecs_to_jiffies(1 * HZ));
  1319. status = 0;
  1320. goto done;
  1321. default:
  1322. musb_dbg(musb, "Unhandled wake: %s",
  1323. usb_otg_state_string(musb->xceiv->otg->state));
  1324. goto done;
  1325. }
  1326. status = 0;
  1327. power = musb_readb(mregs, MUSB_POWER);
  1328. power |= MUSB_POWER_RESUME;
  1329. musb_writeb(mregs, MUSB_POWER, power);
  1330. musb_dbg(musb, "issue wakeup");
  1331. /* FIXME do this next chunk in a timer callback, no udelay */
  1332. mdelay(2);
  1333. power = musb_readb(mregs, MUSB_POWER);
  1334. power &= ~MUSB_POWER_RESUME;
  1335. musb_writeb(mregs, MUSB_POWER, power);
  1336. done:
  1337. spin_unlock_irqrestore(&musb->lock, flags);
  1338. return status;
  1339. }
  1340. static int
  1341. musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
  1342. {
  1343. gadget->is_selfpowered = !!is_selfpowered;
  1344. return 0;
  1345. }
  1346. static void musb_pullup(struct musb *musb, int is_on)
  1347. {
  1348. u8 power;
  1349. power = musb_readb(musb->mregs, MUSB_POWER);
  1350. if (is_on)
  1351. power |= MUSB_POWER_SOFTCONN;
  1352. else
  1353. power &= ~MUSB_POWER_SOFTCONN;
  1354. /* FIXME if on, HdrcStart; if off, HdrcStop */
  1355. musb_dbg(musb, "gadget D+ pullup %s",
  1356. is_on ? "on" : "off");
  1357. musb_writeb(musb->mregs, MUSB_POWER, power);
  1358. }
  1359. #if 0
  1360. static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
  1361. {
  1362. musb_dbg(musb, "<= %s =>\n", __func__);
  1363. /*
  1364. * FIXME iff driver's softconnect flag is set (as it is during probe,
  1365. * though that can clear it), just musb_pullup().
  1366. */
  1367. return -EINVAL;
  1368. }
  1369. #endif
  1370. static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1371. {
  1372. struct musb *musb = gadget_to_musb(gadget);
  1373. if (!musb->xceiv->set_power)
  1374. return -EOPNOTSUPP;
  1375. return usb_phy_set_power(musb->xceiv, mA);
  1376. }
  1377. static void musb_gadget_work(struct work_struct *work)
  1378. {
  1379. struct musb *musb;
  1380. unsigned long flags;
  1381. musb = container_of(work, struct musb, gadget_work.work);
  1382. pm_runtime_get_sync(musb->controller);
  1383. spin_lock_irqsave(&musb->lock, flags);
  1384. musb_pullup(musb, musb->softconnect);
  1385. spin_unlock_irqrestore(&musb->lock, flags);
  1386. pm_runtime_mark_last_busy(musb->controller);
  1387. pm_runtime_put_autosuspend(musb->controller);
  1388. }
  1389. static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
  1390. {
  1391. struct musb *musb = gadget_to_musb(gadget);
  1392. unsigned long flags;
  1393. is_on = !!is_on;
  1394. /* NOTE: this assumes we are sensing vbus; we'd rather
  1395. * not pullup unless the B-session is active.
  1396. */
  1397. spin_lock_irqsave(&musb->lock, flags);
  1398. if (is_on != musb->softconnect) {
  1399. musb->softconnect = is_on;
  1400. schedule_delayed_work(&musb->gadget_work, 0);
  1401. }
  1402. spin_unlock_irqrestore(&musb->lock, flags);
  1403. return 0;
  1404. }
  1405. static int musb_gadget_start(struct usb_gadget *g,
  1406. struct usb_gadget_driver *driver);
  1407. static int musb_gadget_stop(struct usb_gadget *g);
  1408. static const struct usb_gadget_ops musb_gadget_operations = {
  1409. .get_frame = musb_gadget_get_frame,
  1410. .wakeup = musb_gadget_wakeup,
  1411. .set_selfpowered = musb_gadget_set_self_powered,
  1412. /* .vbus_session = musb_gadget_vbus_session, */
  1413. .vbus_draw = musb_gadget_vbus_draw,
  1414. .pullup = musb_gadget_pullup,
  1415. .udc_start = musb_gadget_start,
  1416. .udc_stop = musb_gadget_stop,
  1417. };
  1418. /* ----------------------------------------------------------------------- */
  1419. /* Registration */
  1420. /* Only this registration code "knows" the rule (from USB standards)
  1421. * about there being only one external upstream port. It assumes
  1422. * all peripheral ports are external...
  1423. */
  1424. static void
  1425. init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
  1426. {
  1427. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  1428. memset(ep, 0, sizeof *ep);
  1429. ep->current_epnum = epnum;
  1430. ep->musb = musb;
  1431. ep->hw_ep = hw_ep;
  1432. ep->is_in = is_in;
  1433. INIT_LIST_HEAD(&ep->req_list);
  1434. sprintf(ep->name, "ep%d%s", epnum,
  1435. (!epnum || hw_ep->is_shared_fifo) ? "" : (
  1436. is_in ? "in" : "out"));
  1437. ep->end_point.name = ep->name;
  1438. INIT_LIST_HEAD(&ep->end_point.ep_list);
  1439. if (!epnum) {
  1440. usb_ep_set_maxpacket_limit(&ep->end_point, 64);
  1441. ep->end_point.caps.type_control = true;
  1442. ep->end_point.ops = &musb_g_ep0_ops;
  1443. musb->g.ep0 = &ep->end_point;
  1444. } else {
  1445. if (is_in)
  1446. usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx);
  1447. else
  1448. usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx);
  1449. ep->end_point.caps.type_iso = true;
  1450. ep->end_point.caps.type_bulk = true;
  1451. ep->end_point.caps.type_int = true;
  1452. ep->end_point.ops = &musb_ep_ops;
  1453. list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
  1454. }
  1455. if (!epnum || hw_ep->is_shared_fifo) {
  1456. ep->end_point.caps.dir_in = true;
  1457. ep->end_point.caps.dir_out = true;
  1458. } else if (is_in)
  1459. ep->end_point.caps.dir_in = true;
  1460. else
  1461. ep->end_point.caps.dir_out = true;
  1462. }
  1463. /*
  1464. * Initialize the endpoints exposed to peripheral drivers, with backlinks
  1465. * to the rest of the driver state.
  1466. */
  1467. static inline void musb_g_init_endpoints(struct musb *musb)
  1468. {
  1469. u8 epnum;
  1470. struct musb_hw_ep *hw_ep;
  1471. unsigned count = 0;
  1472. /* initialize endpoint list just once */
  1473. INIT_LIST_HEAD(&(musb->g.ep_list));
  1474. for (epnum = 0, hw_ep = musb->endpoints;
  1475. epnum < musb->nr_endpoints;
  1476. epnum++, hw_ep++) {
  1477. if (hw_ep->is_shared_fifo /* || !epnum */) {
  1478. init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
  1479. count++;
  1480. } else {
  1481. if (hw_ep->max_packet_sz_tx) {
  1482. init_peripheral_ep(musb, &hw_ep->ep_in,
  1483. epnum, 1);
  1484. count++;
  1485. }
  1486. if (hw_ep->max_packet_sz_rx) {
  1487. init_peripheral_ep(musb, &hw_ep->ep_out,
  1488. epnum, 0);
  1489. count++;
  1490. }
  1491. }
  1492. }
  1493. }
  1494. /* called once during driver setup to initialize and link into
  1495. * the driver model; memory is zeroed.
  1496. */
  1497. int musb_gadget_setup(struct musb *musb)
  1498. {
  1499. int status;
  1500. /* REVISIT minor race: if (erroneously) setting up two
  1501. * musb peripherals at the same time, only the bus lock
  1502. * is probably held.
  1503. */
  1504. musb->g.ops = &musb_gadget_operations;
  1505. musb->g.max_speed = USB_SPEED_HIGH;
  1506. musb->g.speed = USB_SPEED_UNKNOWN;
  1507. MUSB_DEV_MODE(musb);
  1508. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  1509. /* this "gadget" abstracts/virtualizes the controller */
  1510. musb->g.name = musb_driver_name;
  1511. /* don't support otg protocols */
  1512. musb->g.is_otg = 0;
  1513. INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work);
  1514. musb_g_init_endpoints(musb);
  1515. musb->is_active = 0;
  1516. musb_platform_try_idle(musb, 0);
  1517. status = usb_add_gadget_udc(musb->controller, &musb->g);
  1518. if (status)
  1519. goto err;
  1520. return 0;
  1521. err:
  1522. musb->g.dev.parent = NULL;
  1523. device_unregister(&musb->g.dev);
  1524. return status;
  1525. }
  1526. void musb_gadget_cleanup(struct musb *musb)
  1527. {
  1528. if (musb->port_mode == MUSB_HOST)
  1529. return;
  1530. cancel_delayed_work_sync(&musb->gadget_work);
  1531. usb_del_gadget_udc(&musb->g);
  1532. }
  1533. /*
  1534. * Register the gadget driver. Used by gadget drivers when
  1535. * registering themselves with the controller.
  1536. *
  1537. * -EINVAL something went wrong (not driver)
  1538. * -EBUSY another gadget is already using the controller
  1539. * -ENOMEM no memory to perform the operation
  1540. *
  1541. * @param driver the gadget driver
  1542. * @return <0 if error, 0 if everything is fine
  1543. */
  1544. static int musb_gadget_start(struct usb_gadget *g,
  1545. struct usb_gadget_driver *driver)
  1546. {
  1547. struct musb *musb = gadget_to_musb(g);
  1548. struct usb_otg *otg = musb->xceiv->otg;
  1549. unsigned long flags;
  1550. int retval = 0;
  1551. if (driver->max_speed < USB_SPEED_HIGH) {
  1552. retval = -EINVAL;
  1553. goto err;
  1554. }
  1555. pm_runtime_get_sync(musb->controller);
  1556. musb->softconnect = 0;
  1557. musb->gadget_driver = driver;
  1558. spin_lock_irqsave(&musb->lock, flags);
  1559. musb->is_active = 1;
  1560. otg_set_peripheral(otg, &musb->g);
  1561. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  1562. spin_unlock_irqrestore(&musb->lock, flags);
  1563. musb_start(musb);
  1564. /* REVISIT: funcall to other code, which also
  1565. * handles power budgeting ... this way also
  1566. * ensures HdrcStart is indirectly called.
  1567. */
  1568. if (musb->xceiv->last_event == USB_EVENT_ID)
  1569. musb_platform_set_vbus(musb, 1);
  1570. pm_runtime_mark_last_busy(musb->controller);
  1571. pm_runtime_put_autosuspend(musb->controller);
  1572. return 0;
  1573. err:
  1574. return retval;
  1575. }
  1576. /*
  1577. * Unregister the gadget driver. Used by gadget drivers when
  1578. * unregistering themselves from the controller.
  1579. *
  1580. * @param driver the gadget driver to unregister
  1581. */
  1582. static int musb_gadget_stop(struct usb_gadget *g)
  1583. {
  1584. struct musb *musb = gadget_to_musb(g);
  1585. unsigned long flags;
  1586. pm_runtime_get_sync(musb->controller);
  1587. /*
  1588. * REVISIT always use otg_set_peripheral() here too;
  1589. * this needs to shut down the OTG engine.
  1590. */
  1591. spin_lock_irqsave(&musb->lock, flags);
  1592. musb_hnp_stop(musb);
  1593. (void) musb_gadget_vbus_draw(&musb->g, 0);
  1594. musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
  1595. musb_stop(musb);
  1596. otg_set_peripheral(musb->xceiv->otg, NULL);
  1597. musb->is_active = 0;
  1598. musb->gadget_driver = NULL;
  1599. musb_platform_try_idle(musb, 0);
  1600. spin_unlock_irqrestore(&musb->lock, flags);
  1601. /*
  1602. * FIXME we need to be able to register another
  1603. * gadget driver here and have everything work;
  1604. * that currently misbehaves.
  1605. */
  1606. /* Force check of devctl register for PM runtime */
  1607. schedule_delayed_work(&musb->irq_work, 0);
  1608. pm_runtime_mark_last_busy(musb->controller);
  1609. pm_runtime_put_autosuspend(musb->controller);
  1610. return 0;
  1611. }
  1612. /* ----------------------------------------------------------------------- */
  1613. /* lifecycle operations called through plat_uds.c */
  1614. void musb_g_resume(struct musb *musb)
  1615. {
  1616. musb->is_suspended = 0;
  1617. switch (musb->xceiv->otg->state) {
  1618. case OTG_STATE_B_IDLE:
  1619. break;
  1620. case OTG_STATE_B_WAIT_ACON:
  1621. case OTG_STATE_B_PERIPHERAL:
  1622. musb->is_active = 1;
  1623. if (musb->gadget_driver && musb->gadget_driver->resume) {
  1624. spin_unlock(&musb->lock);
  1625. musb->gadget_driver->resume(&musb->g);
  1626. spin_lock(&musb->lock);
  1627. }
  1628. break;
  1629. default:
  1630. WARNING("unhandled RESUME transition (%s)\n",
  1631. usb_otg_state_string(musb->xceiv->otg->state));
  1632. }
  1633. }
  1634. /* called when SOF packets stop for 3+ msec */
  1635. void musb_g_suspend(struct musb *musb)
  1636. {
  1637. u8 devctl;
  1638. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1639. musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl);
  1640. switch (musb->xceiv->otg->state) {
  1641. case OTG_STATE_B_IDLE:
  1642. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  1643. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  1644. break;
  1645. case OTG_STATE_B_PERIPHERAL:
  1646. musb->is_suspended = 1;
  1647. if (musb->gadget_driver && musb->gadget_driver->suspend) {
  1648. spin_unlock(&musb->lock);
  1649. musb->gadget_driver->suspend(&musb->g);
  1650. spin_lock(&musb->lock);
  1651. }
  1652. break;
  1653. default:
  1654. /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
  1655. * A_PERIPHERAL may need care too
  1656. */
  1657. WARNING("unhandled SUSPEND transition (%s)",
  1658. usb_otg_state_string(musb->xceiv->otg->state));
  1659. }
  1660. }
  1661. /* Called during SRP */
  1662. void musb_g_wakeup(struct musb *musb)
  1663. {
  1664. musb_gadget_wakeup(&musb->g);
  1665. }
  1666. /* called when VBUS drops below session threshold, and in other cases */
  1667. void musb_g_disconnect(struct musb *musb)
  1668. {
  1669. void __iomem *mregs = musb->mregs;
  1670. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  1671. musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl);
  1672. /* clear HR */
  1673. musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
  1674. /* don't draw vbus until new b-default session */
  1675. (void) musb_gadget_vbus_draw(&musb->g, 0);
  1676. musb->g.speed = USB_SPEED_UNKNOWN;
  1677. if (musb->gadget_driver && musb->gadget_driver->disconnect) {
  1678. spin_unlock(&musb->lock);
  1679. musb->gadget_driver->disconnect(&musb->g);
  1680. spin_lock(&musb->lock);
  1681. }
  1682. switch (musb->xceiv->otg->state) {
  1683. default:
  1684. musb_dbg(musb, "Unhandled disconnect %s, setting a_idle",
  1685. usb_otg_state_string(musb->xceiv->otg->state));
  1686. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  1687. MUSB_HST_MODE(musb);
  1688. break;
  1689. case OTG_STATE_A_PERIPHERAL:
  1690. musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
  1691. MUSB_HST_MODE(musb);
  1692. break;
  1693. case OTG_STATE_B_WAIT_ACON:
  1694. case OTG_STATE_B_HOST:
  1695. case OTG_STATE_B_PERIPHERAL:
  1696. case OTG_STATE_B_IDLE:
  1697. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  1698. break;
  1699. case OTG_STATE_B_SRP_INIT:
  1700. break;
  1701. }
  1702. musb->is_active = 0;
  1703. }
  1704. void musb_g_reset(struct musb *musb)
  1705. __releases(musb->lock)
  1706. __acquires(musb->lock)
  1707. {
  1708. void __iomem *mbase = musb->mregs;
  1709. u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
  1710. u8 power;
  1711. musb_dbg(musb, "<== %s driver '%s'",
  1712. (devctl & MUSB_DEVCTL_BDEVICE)
  1713. ? "B-Device" : "A-Device",
  1714. musb->gadget_driver
  1715. ? musb->gadget_driver->driver.name
  1716. : NULL
  1717. );
  1718. /* report reset, if we didn't already (flushing EP state) */
  1719. if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) {
  1720. spin_unlock(&musb->lock);
  1721. usb_gadget_udc_reset(&musb->g, musb->gadget_driver);
  1722. spin_lock(&musb->lock);
  1723. }
  1724. /* clear HR */
  1725. else if (devctl & MUSB_DEVCTL_HR)
  1726. musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
  1727. /* what speed did we negotiate? */
  1728. power = musb_readb(mbase, MUSB_POWER);
  1729. musb->g.speed = (power & MUSB_POWER_HSMODE)
  1730. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  1731. /* start in USB_STATE_DEFAULT */
  1732. musb->is_active = 1;
  1733. musb->is_suspended = 0;
  1734. MUSB_DEV_MODE(musb);
  1735. musb->address = 0;
  1736. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  1737. musb->may_wakeup = 0;
  1738. musb->g.b_hnp_enable = 0;
  1739. musb->g.a_alt_hnp_support = 0;
  1740. musb->g.a_hnp_support = 0;
  1741. musb->g.quirk_zlp_not_supp = 1;
  1742. /* Normal reset, as B-Device;
  1743. * or else after HNP, as A-Device
  1744. */
  1745. if (!musb->g.is_otg) {
  1746. /* USB device controllers that are not OTG compatible
  1747. * may not have DEVCTL register in silicon.
  1748. * In that case, do not rely on devctl for setting
  1749. * peripheral mode.
  1750. */
  1751. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  1752. musb->g.is_a_peripheral = 0;
  1753. } else if (devctl & MUSB_DEVCTL_BDEVICE) {
  1754. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  1755. musb->g.is_a_peripheral = 0;
  1756. } else {
  1757. musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
  1758. musb->g.is_a_peripheral = 1;
  1759. }
  1760. /* start with default limits on VBUS power draw */
  1761. (void) musb_gadget_vbus_draw(&musb->g, 8);
  1762. }