musb_dsps.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments DSPS platforms "glue layer"
  4. *
  5. * Copyright (C) 2012, by Texas Instruments
  6. *
  7. * Based on the am35x "glue layer" code.
  8. *
  9. * This file is part of the Inventra Controller Driver for Linux.
  10. *
  11. * musb_dsps.c will be a common file for all the TI DSPS platforms
  12. * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
  13. * For now only ti81x is using this and in future davinci.c, am35x.c
  14. * da8xx.c would be merged to this file after testing.
  15. */
  16. #include <linux/io.h>
  17. #include <linux/err.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/module.h>
  22. #include <linux/usb/usb_phy_generic.h>
  23. #include <linux/platform_data/usb-omap.h>
  24. #include <linux/sizes.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include <linux/of_address.h>
  28. #include <linux/of_irq.h>
  29. #include <linux/usb/of.h>
  30. #include <linux/debugfs.h>
  31. #include "musb_core.h"
  32. static const struct of_device_id musb_dsps_of_match[];
  33. /*
  34. * DSPS musb wrapper register offset.
  35. * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
  36. * musb ips.
  37. */
  38. struct dsps_musb_wrapper {
  39. u16 revision;
  40. u16 control;
  41. u16 status;
  42. u16 epintr_set;
  43. u16 epintr_clear;
  44. u16 epintr_status;
  45. u16 coreintr_set;
  46. u16 coreintr_clear;
  47. u16 coreintr_status;
  48. u16 phy_utmi;
  49. u16 mode;
  50. u16 tx_mode;
  51. u16 rx_mode;
  52. /* bit positions for control */
  53. unsigned reset:5;
  54. /* bit positions for interrupt */
  55. unsigned usb_shift:5;
  56. u32 usb_mask;
  57. u32 usb_bitmap;
  58. unsigned drvvbus:5;
  59. unsigned txep_shift:5;
  60. u32 txep_mask;
  61. u32 txep_bitmap;
  62. unsigned rxep_shift:5;
  63. u32 rxep_mask;
  64. u32 rxep_bitmap;
  65. /* bit positions for phy_utmi */
  66. unsigned otg_disable:5;
  67. /* bit positions for mode */
  68. unsigned iddig:5;
  69. unsigned iddig_mux:5;
  70. /* miscellaneous stuff */
  71. unsigned poll_timeout;
  72. };
  73. /*
  74. * register shadow for suspend
  75. */
  76. struct dsps_context {
  77. u32 control;
  78. u32 epintr;
  79. u32 coreintr;
  80. u32 phy_utmi;
  81. u32 mode;
  82. u32 tx_mode;
  83. u32 rx_mode;
  84. };
  85. /*
  86. * DSPS glue structure.
  87. */
  88. struct dsps_glue {
  89. struct device *dev;
  90. struct platform_device *musb; /* child musb pdev */
  91. const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
  92. int vbus_irq; /* optional vbus irq */
  93. unsigned long last_timer; /* last timer data for each instance */
  94. bool sw_babble_enabled;
  95. void __iomem *usbss_base;
  96. struct dsps_context context;
  97. struct debugfs_regset32 regset;
  98. struct dentry *dbgfs_root;
  99. };
  100. static const struct debugfs_reg32 dsps_musb_regs[] = {
  101. { "revision", 0x00 },
  102. { "control", 0x14 },
  103. { "status", 0x18 },
  104. { "eoi", 0x24 },
  105. { "intr0_stat", 0x30 },
  106. { "intr1_stat", 0x34 },
  107. { "intr0_set", 0x38 },
  108. { "intr1_set", 0x3c },
  109. { "txmode", 0x70 },
  110. { "rxmode", 0x74 },
  111. { "autoreq", 0xd0 },
  112. { "srpfixtime", 0xd4 },
  113. { "tdown", 0xd8 },
  114. { "phy_utmi", 0xe0 },
  115. { "mode", 0xe8 },
  116. };
  117. static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms)
  118. {
  119. struct musb *musb = platform_get_drvdata(glue->musb);
  120. int wait;
  121. if (wait_ms < 0)
  122. wait = msecs_to_jiffies(glue->wrp->poll_timeout);
  123. else
  124. wait = msecs_to_jiffies(wait_ms);
  125. mod_timer(&musb->dev_timer, jiffies + wait);
  126. }
  127. /*
  128. * If no vbus irq from the PMIC is configured, we need to poll VBUS status.
  129. */
  130. static void dsps_mod_timer_optional(struct dsps_glue *glue)
  131. {
  132. if (glue->vbus_irq)
  133. return;
  134. dsps_mod_timer(glue, -1);
  135. }
  136. /* USBSS / USB AM335x */
  137. #define USBSS_IRQ_STATUS 0x28
  138. #define USBSS_IRQ_ENABLER 0x2c
  139. #define USBSS_IRQ_CLEARR 0x30
  140. #define USBSS_IRQ_PD_COMP (1 << 2)
  141. /*
  142. * dsps_musb_enable - enable interrupts
  143. */
  144. static void dsps_musb_enable(struct musb *musb)
  145. {
  146. struct device *dev = musb->controller;
  147. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  148. const struct dsps_musb_wrapper *wrp = glue->wrp;
  149. void __iomem *reg_base = musb->ctrl_base;
  150. u32 epmask, coremask;
  151. /* Workaround: setup IRQs through both register sets. */
  152. epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
  153. ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
  154. coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
  155. musb_writel(reg_base, wrp->epintr_set, epmask);
  156. musb_writel(reg_base, wrp->coreintr_set, coremask);
  157. /*
  158. * start polling for runtime PM active and idle,
  159. * and for ID change in dual-role idle mode.
  160. */
  161. if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
  162. dsps_mod_timer(glue, -1);
  163. }
  164. /*
  165. * dsps_musb_disable - disable HDRC and flush interrupts
  166. */
  167. static void dsps_musb_disable(struct musb *musb)
  168. {
  169. struct device *dev = musb->controller;
  170. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  171. const struct dsps_musb_wrapper *wrp = glue->wrp;
  172. void __iomem *reg_base = musb->ctrl_base;
  173. musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
  174. musb_writel(reg_base, wrp->epintr_clear,
  175. wrp->txep_bitmap | wrp->rxep_bitmap);
  176. del_timer_sync(&musb->dev_timer);
  177. }
  178. /* Caller must take musb->lock */
  179. static int dsps_check_status(struct musb *musb, void *unused)
  180. {
  181. void __iomem *mregs = musb->mregs;
  182. struct device *dev = musb->controller;
  183. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  184. const struct dsps_musb_wrapper *wrp = glue->wrp;
  185. u8 devctl;
  186. int skip_session = 0;
  187. if (glue->vbus_irq)
  188. del_timer(&musb->dev_timer);
  189. /*
  190. * We poll because DSPS IP's won't expose several OTG-critical
  191. * status change events (from the transceiver) otherwise.
  192. */
  193. devctl = musb_readb(mregs, MUSB_DEVCTL);
  194. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  195. usb_otg_state_string(musb->xceiv->otg->state));
  196. switch (musb->xceiv->otg->state) {
  197. case OTG_STATE_A_WAIT_VRISE:
  198. if (musb->port_mode == MUSB_HOST) {
  199. musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
  200. dsps_mod_timer_optional(glue);
  201. break;
  202. }
  203. fallthrough;
  204. case OTG_STATE_A_WAIT_BCON:
  205. /* keep VBUS on for host-only mode */
  206. if (musb->port_mode == MUSB_HOST) {
  207. dsps_mod_timer_optional(glue);
  208. break;
  209. }
  210. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  211. skip_session = 1;
  212. fallthrough;
  213. case OTG_STATE_A_IDLE:
  214. case OTG_STATE_B_IDLE:
  215. if (!glue->vbus_irq) {
  216. if (devctl & MUSB_DEVCTL_BDEVICE) {
  217. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  218. MUSB_DEV_MODE(musb);
  219. } else {
  220. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  221. MUSB_HST_MODE(musb);
  222. }
  223. if (musb->port_mode == MUSB_PERIPHERAL)
  224. skip_session = 1;
  225. if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
  226. musb_writeb(mregs, MUSB_DEVCTL,
  227. MUSB_DEVCTL_SESSION);
  228. }
  229. dsps_mod_timer_optional(glue);
  230. break;
  231. case OTG_STATE_A_WAIT_VFALL:
  232. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  233. musb_writel(musb->ctrl_base, wrp->coreintr_set,
  234. MUSB_INTR_VBUSERROR << wrp->usb_shift);
  235. break;
  236. default:
  237. break;
  238. }
  239. return 0;
  240. }
  241. static void otg_timer(struct timer_list *t)
  242. {
  243. struct musb *musb = from_timer(musb, t, dev_timer);
  244. struct device *dev = musb->controller;
  245. unsigned long flags;
  246. int err;
  247. err = pm_runtime_get(dev);
  248. if ((err != -EINPROGRESS) && err < 0) {
  249. dev_err(dev, "Poll could not pm_runtime_get: %i\n", err);
  250. pm_runtime_put_noidle(dev);
  251. return;
  252. }
  253. spin_lock_irqsave(&musb->lock, flags);
  254. err = musb_queue_resume_work(musb, dsps_check_status, NULL);
  255. if (err < 0)
  256. dev_err(dev, "%s resume work: %i\n", __func__, err);
  257. spin_unlock_irqrestore(&musb->lock, flags);
  258. pm_runtime_mark_last_busy(dev);
  259. pm_runtime_put_autosuspend(dev);
  260. }
  261. static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum)
  262. {
  263. u32 epintr;
  264. struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
  265. const struct dsps_musb_wrapper *wrp = glue->wrp;
  266. /* musb->lock might already been held */
  267. epintr = (1 << epnum) << wrp->rxep_shift;
  268. musb_writel(musb->ctrl_base, wrp->epintr_status, epintr);
  269. }
  270. static irqreturn_t dsps_interrupt(int irq, void *hci)
  271. {
  272. struct musb *musb = hci;
  273. void __iomem *reg_base = musb->ctrl_base;
  274. struct device *dev = musb->controller;
  275. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  276. const struct dsps_musb_wrapper *wrp = glue->wrp;
  277. unsigned long flags;
  278. irqreturn_t ret = IRQ_NONE;
  279. u32 epintr, usbintr;
  280. spin_lock_irqsave(&musb->lock, flags);
  281. /* Get endpoint interrupts */
  282. epintr = musb_readl(reg_base, wrp->epintr_status);
  283. musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
  284. musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
  285. if (epintr)
  286. musb_writel(reg_base, wrp->epintr_status, epintr);
  287. /* Get usb core interrupts */
  288. usbintr = musb_readl(reg_base, wrp->coreintr_status);
  289. if (!usbintr && !epintr)
  290. goto out;
  291. musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
  292. if (usbintr)
  293. musb_writel(reg_base, wrp->coreintr_status, usbintr);
  294. dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
  295. usbintr, epintr);
  296. if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
  297. int drvvbus = musb_readl(reg_base, wrp->status);
  298. void __iomem *mregs = musb->mregs;
  299. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  300. int err;
  301. err = musb->int_usb & MUSB_INTR_VBUSERROR;
  302. if (err) {
  303. /*
  304. * The Mentor core doesn't debounce VBUS as needed
  305. * to cope with device connect current spikes. This
  306. * means it's not uncommon for bus-powered devices
  307. * to get VBUS errors during enumeration.
  308. *
  309. * This is a workaround, but newer RTL from Mentor
  310. * seems to allow a better one: "re"-starting sessions
  311. * without waiting for VBUS to stop registering in
  312. * devctl.
  313. */
  314. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  315. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
  316. dsps_mod_timer_optional(glue);
  317. WARNING("VBUS error workaround (delay coming)\n");
  318. } else if (drvvbus) {
  319. MUSB_HST_MODE(musb);
  320. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  321. dsps_mod_timer_optional(glue);
  322. } else {
  323. musb->is_active = 0;
  324. MUSB_DEV_MODE(musb);
  325. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  326. }
  327. /* NOTE: this must complete power-on within 100 ms. */
  328. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  329. drvvbus ? "on" : "off",
  330. usb_otg_state_string(musb->xceiv->otg->state),
  331. err ? " ERROR" : "",
  332. devctl);
  333. ret = IRQ_HANDLED;
  334. }
  335. if (musb->int_tx || musb->int_rx || musb->int_usb)
  336. ret |= musb_interrupt(musb);
  337. /* Poll for ID change and connect */
  338. switch (musb->xceiv->otg->state) {
  339. case OTG_STATE_B_IDLE:
  340. case OTG_STATE_A_WAIT_BCON:
  341. dsps_mod_timer_optional(glue);
  342. break;
  343. default:
  344. break;
  345. }
  346. out:
  347. spin_unlock_irqrestore(&musb->lock, flags);
  348. return ret;
  349. }
  350. static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
  351. {
  352. struct dentry *root;
  353. char buf[128];
  354. sprintf(buf, "%s.dsps", dev_name(musb->controller));
  355. root = debugfs_create_dir(buf, usb_debug_root);
  356. glue->dbgfs_root = root;
  357. glue->regset.regs = dsps_musb_regs;
  358. glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
  359. glue->regset.base = musb->ctrl_base;
  360. debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
  361. return 0;
  362. }
  363. static int dsps_musb_init(struct musb *musb)
  364. {
  365. struct device *dev = musb->controller;
  366. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  367. struct platform_device *parent = to_platform_device(dev->parent);
  368. const struct dsps_musb_wrapper *wrp = glue->wrp;
  369. void __iomem *reg_base;
  370. struct resource *r;
  371. u32 rev, val;
  372. int ret;
  373. r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
  374. reg_base = devm_ioremap_resource(dev, r);
  375. if (IS_ERR(reg_base))
  376. return PTR_ERR(reg_base);
  377. musb->ctrl_base = reg_base;
  378. /* NOP driver needs change if supporting dual instance */
  379. musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
  380. if (IS_ERR(musb->xceiv))
  381. return PTR_ERR(musb->xceiv);
  382. musb->phy = devm_phy_get(dev->parent, "usb2-phy");
  383. /* Returns zero if e.g. not clocked */
  384. rev = musb_readl(reg_base, wrp->revision);
  385. if (!rev)
  386. return -ENODEV;
  387. if (IS_ERR(musb->phy)) {
  388. musb->phy = NULL;
  389. } else {
  390. ret = phy_init(musb->phy);
  391. if (ret < 0)
  392. return ret;
  393. ret = phy_power_on(musb->phy);
  394. if (ret) {
  395. phy_exit(musb->phy);
  396. return ret;
  397. }
  398. }
  399. timer_setup(&musb->dev_timer, otg_timer, 0);
  400. /* Reset the musb */
  401. musb_writel(reg_base, wrp->control, (1 << wrp->reset));
  402. musb->isr = dsps_interrupt;
  403. /* reset the otgdisable bit, needed for host mode to work */
  404. val = musb_readl(reg_base, wrp->phy_utmi);
  405. val &= ~(1 << wrp->otg_disable);
  406. musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
  407. /*
  408. * Check whether the dsps version has babble control enabled.
  409. * In latest silicon revision the babble control logic is enabled.
  410. * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
  411. * logic enabled.
  412. */
  413. val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
  414. if (val & MUSB_BABBLE_RCV_DISABLE) {
  415. glue->sw_babble_enabled = true;
  416. val |= MUSB_BABBLE_SW_SESSION_CTRL;
  417. musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
  418. }
  419. dsps_mod_timer(glue, -1);
  420. return dsps_musb_dbg_init(musb, glue);
  421. }
  422. static int dsps_musb_exit(struct musb *musb)
  423. {
  424. struct device *dev = musb->controller;
  425. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  426. del_timer_sync(&musb->dev_timer);
  427. phy_power_off(musb->phy);
  428. phy_exit(musb->phy);
  429. debugfs_remove_recursive(glue->dbgfs_root);
  430. return 0;
  431. }
  432. static int dsps_musb_set_mode(struct musb *musb, u8 mode)
  433. {
  434. struct device *dev = musb->controller;
  435. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  436. const struct dsps_musb_wrapper *wrp = glue->wrp;
  437. void __iomem *ctrl_base = musb->ctrl_base;
  438. u32 reg;
  439. reg = musb_readl(ctrl_base, wrp->mode);
  440. switch (mode) {
  441. case MUSB_HOST:
  442. reg &= ~(1 << wrp->iddig);
  443. /*
  444. * if we're setting mode to host-only or device-only, we're
  445. * going to ignore whatever the PHY sends us and just force
  446. * ID pin status by SW
  447. */
  448. reg |= (1 << wrp->iddig_mux);
  449. musb_writel(ctrl_base, wrp->mode, reg);
  450. musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
  451. break;
  452. case MUSB_PERIPHERAL:
  453. reg |= (1 << wrp->iddig);
  454. /*
  455. * if we're setting mode to host-only or device-only, we're
  456. * going to ignore whatever the PHY sends us and just force
  457. * ID pin status by SW
  458. */
  459. reg |= (1 << wrp->iddig_mux);
  460. musb_writel(ctrl_base, wrp->mode, reg);
  461. break;
  462. case MUSB_OTG:
  463. musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
  464. break;
  465. default:
  466. dev_err(glue->dev, "unsupported mode %d\n", mode);
  467. return -EINVAL;
  468. }
  469. return 0;
  470. }
  471. static bool dsps_sw_babble_control(struct musb *musb)
  472. {
  473. u8 babble_ctl;
  474. bool session_restart = false;
  475. babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
  476. dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
  477. babble_ctl);
  478. /*
  479. * check line monitor flag to check whether babble is
  480. * due to noise
  481. */
  482. dev_dbg(musb->controller, "STUCK_J is %s\n",
  483. babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset");
  484. if (babble_ctl & MUSB_BABBLE_STUCK_J) {
  485. int timeout = 10;
  486. /*
  487. * babble is due to noise, then set transmit idle (d7 bit)
  488. * to resume normal operation
  489. */
  490. babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
  491. babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
  492. musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
  493. /* wait till line monitor flag cleared */
  494. dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
  495. do {
  496. babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
  497. udelay(1);
  498. } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
  499. /* check whether stuck_at_j bit cleared */
  500. if (babble_ctl & MUSB_BABBLE_STUCK_J) {
  501. /*
  502. * real babble condition has occurred
  503. * restart the controller to start the
  504. * session again
  505. */
  506. dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
  507. babble_ctl);
  508. session_restart = true;
  509. }
  510. } else {
  511. session_restart = true;
  512. }
  513. return session_restart;
  514. }
  515. static int dsps_musb_recover(struct musb *musb)
  516. {
  517. struct device *dev = musb->controller;
  518. struct dsps_glue *glue = dev_get_drvdata(dev->parent);
  519. int session_restart = 0;
  520. if (glue->sw_babble_enabled)
  521. session_restart = dsps_sw_babble_control(musb);
  522. else
  523. session_restart = 1;
  524. return session_restart ? 0 : -EPIPE;
  525. }
  526. /* Similar to am35x, dm81xx support only 32-bit read operation */
  527. static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  528. {
  529. void __iomem *fifo = hw_ep->fifo;
  530. if (len >= 4) {
  531. ioread32_rep(fifo, dst, len >> 2);
  532. dst += len & ~0x03;
  533. len &= 0x03;
  534. }
  535. /* Read any remaining 1 to 3 bytes */
  536. if (len > 0) {
  537. u32 val = musb_readl(fifo, 0);
  538. memcpy(dst, &val, len);
  539. }
  540. }
  541. #ifdef CONFIG_USB_TI_CPPI41_DMA
  542. static void dsps_dma_controller_callback(struct dma_controller *c)
  543. {
  544. struct musb *musb = c->musb;
  545. struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
  546. void __iomem *usbss_base = glue->usbss_base;
  547. u32 status;
  548. status = musb_readl(usbss_base, USBSS_IRQ_STATUS);
  549. if (status & USBSS_IRQ_PD_COMP)
  550. musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP);
  551. }
  552. static struct dma_controller *
  553. dsps_dma_controller_create(struct musb *musb, void __iomem *base)
  554. {
  555. struct dma_controller *controller;
  556. struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
  557. void __iomem *usbss_base = glue->usbss_base;
  558. controller = cppi41_dma_controller_create(musb, base);
  559. if (IS_ERR_OR_NULL(controller))
  560. return controller;
  561. musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
  562. controller->dma_callback = dsps_dma_controller_callback;
  563. return controller;
  564. }
  565. #ifdef CONFIG_PM_SLEEP
  566. static void dsps_dma_controller_suspend(struct dsps_glue *glue)
  567. {
  568. void __iomem *usbss_base = glue->usbss_base;
  569. musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
  570. }
  571. static void dsps_dma_controller_resume(struct dsps_glue *glue)
  572. {
  573. void __iomem *usbss_base = glue->usbss_base;
  574. musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
  575. }
  576. #endif
  577. #else /* CONFIG_USB_TI_CPPI41_DMA */
  578. #ifdef CONFIG_PM_SLEEP
  579. static void dsps_dma_controller_suspend(struct dsps_glue *glue) {}
  580. static void dsps_dma_controller_resume(struct dsps_glue *glue) {}
  581. #endif
  582. #endif /* CONFIG_USB_TI_CPPI41_DMA */
  583. static struct musb_platform_ops dsps_ops = {
  584. .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
  585. .init = dsps_musb_init,
  586. .exit = dsps_musb_exit,
  587. #ifdef CONFIG_USB_TI_CPPI41_DMA
  588. .dma_init = dsps_dma_controller_create,
  589. .dma_exit = cppi41_dma_controller_destroy,
  590. #endif
  591. .enable = dsps_musb_enable,
  592. .disable = dsps_musb_disable,
  593. .set_mode = dsps_musb_set_mode,
  594. .recover = dsps_musb_recover,
  595. .clear_ep_rxintr = dsps_musb_clear_ep_rxintr,
  596. };
  597. static u64 musb_dmamask = DMA_BIT_MASK(32);
  598. static int get_int_prop(struct device_node *dn, const char *s)
  599. {
  600. int ret;
  601. u32 val;
  602. ret = of_property_read_u32(dn, s, &val);
  603. if (ret)
  604. return 0;
  605. return val;
  606. }
  607. static int dsps_create_musb_pdev(struct dsps_glue *glue,
  608. struct platform_device *parent)
  609. {
  610. struct musb_hdrc_platform_data pdata;
  611. struct resource resources[2];
  612. struct resource *res;
  613. struct device *dev = &parent->dev;
  614. struct musb_hdrc_config *config;
  615. struct platform_device *musb;
  616. struct device_node *dn = parent->dev.of_node;
  617. int ret, val;
  618. memset(resources, 0, sizeof(resources));
  619. res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
  620. if (!res) {
  621. dev_err(dev, "failed to get memory.\n");
  622. return -EINVAL;
  623. }
  624. resources[0] = *res;
  625. res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
  626. if (!res) {
  627. dev_err(dev, "failed to get irq.\n");
  628. return -EINVAL;
  629. }
  630. resources[1] = *res;
  631. /* allocate the child platform device */
  632. musb = platform_device_alloc("musb-hdrc",
  633. (resources[0].start & 0xFFF) == 0x400 ? 0 : 1);
  634. if (!musb) {
  635. dev_err(dev, "failed to allocate musb device\n");
  636. return -ENOMEM;
  637. }
  638. musb->dev.parent = dev;
  639. musb->dev.dma_mask = &musb_dmamask;
  640. musb->dev.coherent_dma_mask = musb_dmamask;
  641. device_set_of_node_from_dev(&musb->dev, &parent->dev);
  642. glue->musb = musb;
  643. ret = platform_device_add_resources(musb, resources,
  644. ARRAY_SIZE(resources));
  645. if (ret) {
  646. dev_err(dev, "failed to add resources\n");
  647. goto err;
  648. }
  649. config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
  650. if (!config) {
  651. ret = -ENOMEM;
  652. goto err;
  653. }
  654. pdata.config = config;
  655. pdata.platform_ops = &dsps_ops;
  656. config->num_eps = get_int_prop(dn, "mentor,num-eps");
  657. config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
  658. config->host_port_deassert_reset_at_resume = 1;
  659. pdata.mode = musb_get_mode(dev);
  660. /* DT keeps this entry in mA, musb expects it as per USB spec */
  661. pdata.power = get_int_prop(dn, "mentor,power") / 2;
  662. ret = of_property_read_u32(dn, "mentor,multipoint", &val);
  663. if (!ret && val)
  664. config->multipoint = true;
  665. config->maximum_speed = usb_get_maximum_speed(&parent->dev);
  666. switch (config->maximum_speed) {
  667. case USB_SPEED_LOW:
  668. case USB_SPEED_FULL:
  669. break;
  670. case USB_SPEED_SUPER:
  671. dev_warn(dev, "ignore incorrect maximum_speed "
  672. "(super-speed) setting in dts");
  673. fallthrough;
  674. default:
  675. config->maximum_speed = USB_SPEED_HIGH;
  676. }
  677. ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
  678. if (ret) {
  679. dev_err(dev, "failed to add platform_data\n");
  680. goto err;
  681. }
  682. ret = platform_device_add(musb);
  683. if (ret) {
  684. dev_err(dev, "failed to register musb device\n");
  685. goto err;
  686. }
  687. return 0;
  688. err:
  689. platform_device_put(musb);
  690. return ret;
  691. }
  692. static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv)
  693. {
  694. struct dsps_glue *glue = priv;
  695. struct musb *musb = platform_get_drvdata(glue->musb);
  696. if (!musb)
  697. return IRQ_NONE;
  698. dev_dbg(glue->dev, "VBUS interrupt\n");
  699. dsps_mod_timer(glue, 0);
  700. return IRQ_HANDLED;
  701. }
  702. static int dsps_setup_optional_vbus_irq(struct platform_device *pdev,
  703. struct dsps_glue *glue)
  704. {
  705. int error;
  706. glue->vbus_irq = platform_get_irq_byname(pdev, "vbus");
  707. if (glue->vbus_irq == -EPROBE_DEFER)
  708. return -EPROBE_DEFER;
  709. if (glue->vbus_irq <= 0) {
  710. glue->vbus_irq = 0;
  711. return 0;
  712. }
  713. error = devm_request_threaded_irq(glue->dev, glue->vbus_irq,
  714. NULL, dsps_vbus_threaded_irq,
  715. IRQF_ONESHOT,
  716. "vbus", glue);
  717. if (error) {
  718. glue->vbus_irq = 0;
  719. return error;
  720. }
  721. dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq);
  722. return 0;
  723. }
  724. static int dsps_probe(struct platform_device *pdev)
  725. {
  726. const struct of_device_id *match;
  727. const struct dsps_musb_wrapper *wrp;
  728. struct dsps_glue *glue;
  729. int ret;
  730. if (!strcmp(pdev->name, "musb-hdrc"))
  731. return -ENODEV;
  732. match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
  733. if (!match) {
  734. dev_err(&pdev->dev, "fail to get matching of_match struct\n");
  735. return -EINVAL;
  736. }
  737. wrp = match->data;
  738. if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816"))
  739. dsps_ops.read_fifo = dsps_read_fifo32;
  740. /* allocate glue */
  741. glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
  742. if (!glue)
  743. return -ENOMEM;
  744. glue->dev = &pdev->dev;
  745. glue->wrp = wrp;
  746. glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0);
  747. if (!glue->usbss_base)
  748. return -ENXIO;
  749. platform_set_drvdata(pdev, glue);
  750. pm_runtime_enable(&pdev->dev);
  751. ret = dsps_create_musb_pdev(glue, pdev);
  752. if (ret)
  753. goto err;
  754. if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) {
  755. ret = dsps_setup_optional_vbus_irq(pdev, glue);
  756. if (ret)
  757. goto unregister_pdev;
  758. }
  759. return 0;
  760. unregister_pdev:
  761. platform_device_unregister(glue->musb);
  762. err:
  763. pm_runtime_disable(&pdev->dev);
  764. iounmap(glue->usbss_base);
  765. return ret;
  766. }
  767. static int dsps_remove(struct platform_device *pdev)
  768. {
  769. struct dsps_glue *glue = platform_get_drvdata(pdev);
  770. platform_device_unregister(glue->musb);
  771. pm_runtime_disable(&pdev->dev);
  772. iounmap(glue->usbss_base);
  773. return 0;
  774. }
  775. static const struct dsps_musb_wrapper am33xx_driver_data = {
  776. .revision = 0x00,
  777. .control = 0x14,
  778. .status = 0x18,
  779. .epintr_set = 0x38,
  780. .epintr_clear = 0x40,
  781. .epintr_status = 0x30,
  782. .coreintr_set = 0x3c,
  783. .coreintr_clear = 0x44,
  784. .coreintr_status = 0x34,
  785. .phy_utmi = 0xe0,
  786. .mode = 0xe8,
  787. .tx_mode = 0x70,
  788. .rx_mode = 0x74,
  789. .reset = 0,
  790. .otg_disable = 21,
  791. .iddig = 8,
  792. .iddig_mux = 7,
  793. .usb_shift = 0,
  794. .usb_mask = 0x1ff,
  795. .usb_bitmap = (0x1ff << 0),
  796. .drvvbus = 8,
  797. .txep_shift = 0,
  798. .txep_mask = 0xffff,
  799. .txep_bitmap = (0xffff << 0),
  800. .rxep_shift = 16,
  801. .rxep_mask = 0xfffe,
  802. .rxep_bitmap = (0xfffe << 16),
  803. .poll_timeout = 2000, /* ms */
  804. };
  805. static const struct of_device_id musb_dsps_of_match[] = {
  806. { .compatible = "ti,musb-am33xx",
  807. .data = &am33xx_driver_data, },
  808. { .compatible = "ti,musb-dm816",
  809. .data = &am33xx_driver_data, },
  810. { },
  811. };
  812. MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
  813. #ifdef CONFIG_PM_SLEEP
  814. static int dsps_suspend(struct device *dev)
  815. {
  816. struct dsps_glue *glue = dev_get_drvdata(dev);
  817. const struct dsps_musb_wrapper *wrp = glue->wrp;
  818. struct musb *musb = platform_get_drvdata(glue->musb);
  819. void __iomem *mbase;
  820. int ret;
  821. if (!musb)
  822. /* This can happen if the musb device is in -EPROBE_DEFER */
  823. return 0;
  824. ret = pm_runtime_get_sync(dev);
  825. if (ret < 0) {
  826. pm_runtime_put_noidle(dev);
  827. return ret;
  828. }
  829. del_timer_sync(&musb->dev_timer);
  830. mbase = musb->ctrl_base;
  831. glue->context.control = musb_readl(mbase, wrp->control);
  832. glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
  833. glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
  834. glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
  835. glue->context.mode = musb_readl(mbase, wrp->mode);
  836. glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
  837. glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
  838. dsps_dma_controller_suspend(glue);
  839. return 0;
  840. }
  841. static int dsps_resume(struct device *dev)
  842. {
  843. struct dsps_glue *glue = dev_get_drvdata(dev);
  844. const struct dsps_musb_wrapper *wrp = glue->wrp;
  845. struct musb *musb = platform_get_drvdata(glue->musb);
  846. void __iomem *mbase;
  847. if (!musb)
  848. return 0;
  849. dsps_dma_controller_resume(glue);
  850. mbase = musb->ctrl_base;
  851. musb_writel(mbase, wrp->control, glue->context.control);
  852. musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
  853. musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
  854. musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
  855. musb_writel(mbase, wrp->mode, glue->context.mode);
  856. musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
  857. musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
  858. if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
  859. musb->port_mode == MUSB_OTG)
  860. dsps_mod_timer(glue, -1);
  861. pm_runtime_put(dev);
  862. return 0;
  863. }
  864. #endif
  865. static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
  866. static struct platform_driver dsps_usbss_driver = {
  867. .probe = dsps_probe,
  868. .remove = dsps_remove,
  869. .driver = {
  870. .name = "musb-dsps",
  871. .pm = &dsps_pm_ops,
  872. .of_match_table = musb_dsps_of_match,
  873. },
  874. };
  875. MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
  876. MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
  877. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  878. MODULE_LICENSE("GPL v2");
  879. module_platform_driver(dsps_usbss_driver);