musb_dma.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * MUSB OTG driver DMA controller abstraction
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. */
  9. #ifndef __MUSB_DMA_H__
  10. #define __MUSB_DMA_H__
  11. struct musb_hw_ep;
  12. /*
  13. * DMA Controller Abstraction
  14. *
  15. * DMA Controllers are abstracted to allow use of a variety of different
  16. * implementations of DMA, as allowed by the Inventra USB cores. On the
  17. * host side, usbcore sets up the DMA mappings and flushes caches; on the
  18. * peripheral side, the gadget controller driver does. Responsibilities
  19. * of a DMA controller driver include:
  20. *
  21. * - Handling the details of moving multiple USB packets
  22. * in cooperation with the Inventra USB core, including especially
  23. * the correct RX side treatment of short packets and buffer-full
  24. * states (both of which terminate transfers).
  25. *
  26. * - Knowing the correlation between dma channels and the
  27. * Inventra core's local endpoint resources and data direction.
  28. *
  29. * - Maintaining a list of allocated/available channels.
  30. *
  31. * - Updating channel status on interrupts,
  32. * whether shared with the Inventra core or separate.
  33. */
  34. #define MUSB_HSDMA_BASE 0x200
  35. #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
  36. #define MUSB_HSDMA_CONTROL 0x4
  37. #define MUSB_HSDMA_ADDRESS 0x8
  38. #define MUSB_HSDMA_COUNT 0xc
  39. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  40. #ifdef CONFIG_MUSB_PIO_ONLY
  41. #define is_dma_capable() (0)
  42. #else
  43. #define is_dma_capable() (1)
  44. #endif
  45. #ifdef CONFIG_USB_UX500_DMA
  46. #define musb_dma_ux500(musb) (musb->ops->quirks & MUSB_DMA_UX500)
  47. #else
  48. #define musb_dma_ux500(musb) 0
  49. #endif
  50. #ifdef CONFIG_USB_TI_CPPI41_DMA
  51. #define musb_dma_cppi41(musb) (musb->ops->quirks & MUSB_DMA_CPPI41)
  52. #else
  53. #define musb_dma_cppi41(musb) 0
  54. #endif
  55. #ifdef CONFIG_USB_TI_CPPI_DMA
  56. #define musb_dma_cppi(musb) (musb->ops->quirks & MUSB_DMA_CPPI)
  57. #else
  58. #define musb_dma_cppi(musb) 0
  59. #endif
  60. #ifdef CONFIG_USB_TUSB_OMAP_DMA
  61. #define tusb_dma_omap(musb) (musb->ops->quirks & MUSB_DMA_TUSB_OMAP)
  62. #else
  63. #define tusb_dma_omap(musb) 0
  64. #endif
  65. #ifdef CONFIG_USB_INVENTRA_DMA
  66. #define musb_dma_inventra(musb) (musb->ops->quirks & MUSB_DMA_INVENTRA)
  67. #else
  68. #define musb_dma_inventra(musb) 0
  69. #endif
  70. #if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
  71. #define is_cppi_enabled(musb) \
  72. (musb_dma_cppi(musb) || musb_dma_cppi41(musb))
  73. #else
  74. #define is_cppi_enabled(musb) 0
  75. #endif
  76. /*
  77. * DMA channel status ... updated by the dma controller driver whenever that
  78. * status changes, and protected by the overall controller spinlock.
  79. */
  80. enum dma_channel_status {
  81. /* unallocated */
  82. MUSB_DMA_STATUS_UNKNOWN,
  83. /* allocated ... but not busy, no errors */
  84. MUSB_DMA_STATUS_FREE,
  85. /* busy ... transactions are active */
  86. MUSB_DMA_STATUS_BUSY,
  87. /* transaction(s) aborted due to ... dma or memory bus error */
  88. MUSB_DMA_STATUS_BUS_ABORT,
  89. /* transaction(s) aborted due to ... core error or USB fault */
  90. MUSB_DMA_STATUS_CORE_ABORT
  91. };
  92. struct dma_controller;
  93. /**
  94. * struct dma_channel - A DMA channel.
  95. * @private_data: channel-private data
  96. * @max_len: the maximum number of bytes the channel can move in one
  97. * transaction (typically representing many USB maximum-sized packets)
  98. * @actual_len: how many bytes have been transferred
  99. * @status: current channel status (updated e.g. on interrupt)
  100. * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
  101. *
  102. * channels are associated with an endpoint for the duration of at least
  103. * one usb transfer.
  104. */
  105. struct dma_channel {
  106. void *private_data;
  107. /* FIXME not void* private_data, but a dma_controller * */
  108. size_t max_len;
  109. size_t actual_len;
  110. enum dma_channel_status status;
  111. bool desired_mode;
  112. bool rx_packet_done;
  113. };
  114. /*
  115. * dma_channel_status - return status of dma channel
  116. * @c: the channel
  117. *
  118. * Returns the software's view of the channel status. If that status is BUSY
  119. * then it's possible that the hardware has completed (or aborted) a transfer,
  120. * so the driver needs to update that status.
  121. */
  122. static inline enum dma_channel_status
  123. dma_channel_status(struct dma_channel *c)
  124. {
  125. return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
  126. }
  127. /**
  128. * struct dma_controller - A DMA Controller.
  129. * @musb: the usb controller
  130. * @start: call this to start a DMA controller;
  131. * return 0 on success, else negative errno
  132. * @stop: call this to stop a DMA controller
  133. * return 0 on success, else negative errno
  134. * @channel_alloc: call this to allocate a DMA channel
  135. * @channel_release: call this to release a DMA channel
  136. * @channel_abort: call this to abort a pending DMA transaction,
  137. * returning it to FREE (but allocated) state
  138. * @dma_callback: invoked on DMA completion, useful to run platform
  139. * code such IRQ acknowledgment.
  140. *
  141. * Controllers manage dma channels.
  142. */
  143. struct dma_controller {
  144. struct musb *musb;
  145. struct dma_channel *(*channel_alloc)(struct dma_controller *,
  146. struct musb_hw_ep *, u8 is_tx);
  147. void (*channel_release)(struct dma_channel *);
  148. int (*channel_program)(struct dma_channel *channel,
  149. u16 maxpacket, u8 mode,
  150. dma_addr_t dma_addr,
  151. u32 length);
  152. int (*channel_abort)(struct dma_channel *);
  153. int (*is_compatible)(struct dma_channel *channel,
  154. u16 maxpacket,
  155. void *buf, u32 length);
  156. void (*dma_callback)(struct dma_controller *);
  157. };
  158. /* called after channel_program(), may indicate a fault */
  159. extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
  160. #ifdef CONFIG_MUSB_PIO_ONLY
  161. static inline struct dma_controller *
  162. musb_dma_controller_create(struct musb *m, void __iomem *io)
  163. {
  164. return NULL;
  165. }
  166. static inline void musb_dma_controller_destroy(struct dma_controller *d) { }
  167. #else
  168. extern struct dma_controller *
  169. (*musb_dma_controller_create)(struct musb *, void __iomem *);
  170. extern void (*musb_dma_controller_destroy)(struct dma_controller *);
  171. #endif
  172. /* Platform specific DMA functions */
  173. extern struct dma_controller *
  174. musbhs_dma_controller_create(struct musb *musb, void __iomem *base);
  175. extern void musbhs_dma_controller_destroy(struct dma_controller *c);
  176. extern struct dma_controller *
  177. musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base);
  178. extern irqreturn_t dma_controller_irq(int irq, void *private_data);
  179. extern struct dma_controller *
  180. tusb_dma_controller_create(struct musb *musb, void __iomem *base);
  181. extern void tusb_dma_controller_destroy(struct dma_controller *c);
  182. extern struct dma_controller *
  183. cppi_dma_controller_create(struct musb *musb, void __iomem *base);
  184. extern void cppi_dma_controller_destroy(struct dma_controller *c);
  185. extern struct dma_controller *
  186. cppi41_dma_controller_create(struct musb *musb, void __iomem *base);
  187. extern void cppi41_dma_controller_destroy(struct dma_controller *c);
  188. extern struct dma_controller *
  189. ux500_dma_controller_create(struct musb *musb, void __iomem *base);
  190. extern void ux500_dma_controller_destroy(struct dma_controller *c);
  191. #endif /* __MUSB_DMA_H__ */