musb_core.c 79 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver core code
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. */
  9. /*
  10. * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
  11. *
  12. * This consists of a Host Controller Driver (HCD) and a peripheral
  13. * controller driver implementing the "Gadget" API; OTG support is
  14. * in the works. These are normal Linux-USB controller drivers which
  15. * use IRQs and have no dedicated thread.
  16. *
  17. * This version of the driver has only been used with products from
  18. * Texas Instruments. Those products integrate the Inventra logic
  19. * with other DMA, IRQ, and bus modules, as well as other logic that
  20. * needs to be reflected in this driver.
  21. *
  22. *
  23. * NOTE: the original Mentor code here was pretty much a collection
  24. * of mechanisms that don't seem to have been fully integrated/working
  25. * for *any* Linux kernel version. This version aims at Linux 2.6.now,
  26. * Key open issues include:
  27. *
  28. * - Lack of host-side transaction scheduling, for all transfer types.
  29. * The hardware doesn't do it; instead, software must.
  30. *
  31. * This is not an issue for OTG devices that don't support external
  32. * hubs, but for more "normal" USB hosts it's a user issue that the
  33. * "multipoint" support doesn't scale in the expected ways. That
  34. * includes DaVinci EVM in a common non-OTG mode.
  35. *
  36. * * Control and bulk use dedicated endpoints, and there's as
  37. * yet no mechanism to either (a) reclaim the hardware when
  38. * peripherals are NAKing, which gets complicated with bulk
  39. * endpoints, or (b) use more than a single bulk endpoint in
  40. * each direction.
  41. *
  42. * RESULT: one device may be perceived as blocking another one.
  43. *
  44. * * Interrupt and isochronous will dynamically allocate endpoint
  45. * hardware, but (a) there's no record keeping for bandwidth;
  46. * (b) in the common case that few endpoints are available, there
  47. * is no mechanism to reuse endpoints to talk to multiple devices.
  48. *
  49. * RESULT: At one extreme, bandwidth can be overcommitted in
  50. * some hardware configurations, no faults will be reported.
  51. * At the other extreme, the bandwidth capabilities which do
  52. * exist tend to be severely undercommitted. You can't yet hook
  53. * up both a keyboard and a mouse to an external USB hub.
  54. */
  55. /*
  56. * This gets many kinds of configuration information:
  57. * - Kconfig for everything user-configurable
  58. * - platform_device for addressing, irq, and platform_data
  59. * - platform_data is mostly for board-specific information
  60. * (plus recentrly, SOC or family details)
  61. *
  62. * Most of the conditional compilation will (someday) vanish.
  63. */
  64. #include <linux/module.h>
  65. #include <linux/kernel.h>
  66. #include <linux/sched.h>
  67. #include <linux/slab.h>
  68. #include <linux/list.h>
  69. #include <linux/kobject.h>
  70. #include <linux/prefetch.h>
  71. #include <linux/platform_device.h>
  72. #include <linux/io.h>
  73. #include <linux/iopoll.h>
  74. #include <linux/dma-mapping.h>
  75. #include <linux/usb.h>
  76. #include <linux/usb/of.h>
  77. #include "musb_core.h"
  78. #include "musb_trace.h"
  79. #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
  80. #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
  81. #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
  82. #define MUSB_VERSION "6.0"
  83. #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
  84. #define MUSB_DRIVER_NAME "musb-hdrc"
  85. const char musb_driver_name[] = MUSB_DRIVER_NAME;
  86. MODULE_DESCRIPTION(DRIVER_INFO);
  87. MODULE_AUTHOR(DRIVER_AUTHOR);
  88. MODULE_LICENSE("GPL");
  89. MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
  90. /*-------------------------------------------------------------------------*/
  91. static inline struct musb *dev_to_musb(struct device *dev)
  92. {
  93. return dev_get_drvdata(dev);
  94. }
  95. enum musb_mode musb_get_mode(struct device *dev)
  96. {
  97. enum usb_dr_mode mode;
  98. mode = usb_get_dr_mode(dev);
  99. switch (mode) {
  100. case USB_DR_MODE_HOST:
  101. return MUSB_HOST;
  102. case USB_DR_MODE_PERIPHERAL:
  103. return MUSB_PERIPHERAL;
  104. case USB_DR_MODE_OTG:
  105. case USB_DR_MODE_UNKNOWN:
  106. default:
  107. return MUSB_OTG;
  108. }
  109. }
  110. EXPORT_SYMBOL_GPL(musb_get_mode);
  111. /*-------------------------------------------------------------------------*/
  112. static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
  113. {
  114. void __iomem *addr = phy->io_priv;
  115. int i = 0;
  116. u8 r;
  117. u8 power;
  118. int ret;
  119. pm_runtime_get_sync(phy->io_dev);
  120. /* Make sure the transceiver is not in low power mode */
  121. power = musb_readb(addr, MUSB_POWER);
  122. power &= ~MUSB_POWER_SUSPENDM;
  123. musb_writeb(addr, MUSB_POWER, power);
  124. /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
  125. * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
  126. */
  127. musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
  128. musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
  129. MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
  130. while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
  131. & MUSB_ULPI_REG_CMPLT)) {
  132. i++;
  133. if (i == 10000) {
  134. ret = -ETIMEDOUT;
  135. goto out;
  136. }
  137. }
  138. r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
  139. r &= ~MUSB_ULPI_REG_CMPLT;
  140. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
  141. ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
  142. out:
  143. pm_runtime_put(phy->io_dev);
  144. return ret;
  145. }
  146. static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
  147. {
  148. void __iomem *addr = phy->io_priv;
  149. int i = 0;
  150. u8 r = 0;
  151. u8 power;
  152. int ret = 0;
  153. pm_runtime_get_sync(phy->io_dev);
  154. /* Make sure the transceiver is not in low power mode */
  155. power = musb_readb(addr, MUSB_POWER);
  156. power &= ~MUSB_POWER_SUSPENDM;
  157. musb_writeb(addr, MUSB_POWER, power);
  158. musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
  159. musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
  160. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
  161. while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
  162. & MUSB_ULPI_REG_CMPLT)) {
  163. i++;
  164. if (i == 10000) {
  165. ret = -ETIMEDOUT;
  166. goto out;
  167. }
  168. }
  169. r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
  170. r &= ~MUSB_ULPI_REG_CMPLT;
  171. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
  172. out:
  173. pm_runtime_put(phy->io_dev);
  174. return ret;
  175. }
  176. static struct usb_phy_io_ops musb_ulpi_access = {
  177. .read = musb_ulpi_read,
  178. .write = musb_ulpi_write,
  179. };
  180. /*-------------------------------------------------------------------------*/
  181. static u32 musb_default_fifo_offset(u8 epnum)
  182. {
  183. return 0x20 + (epnum * 4);
  184. }
  185. /* "flat" mapping: each endpoint has its own i/o address */
  186. static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
  187. {
  188. }
  189. static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
  190. {
  191. return 0x100 + (0x10 * epnum) + offset;
  192. }
  193. /* "indexed" mapping: INDEX register controls register bank select */
  194. static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
  195. {
  196. musb_writeb(mbase, MUSB_INDEX, epnum);
  197. }
  198. static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
  199. {
  200. return 0x10 + offset;
  201. }
  202. static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
  203. {
  204. return 0x80 + (0x08 * epnum) + offset;
  205. }
  206. static u8 musb_default_readb(void __iomem *addr, u32 offset)
  207. {
  208. u8 data = __raw_readb(addr + offset);
  209. trace_musb_readb(__builtin_return_address(0), addr, offset, data);
  210. return data;
  211. }
  212. static void musb_default_writeb(void __iomem *addr, u32 offset, u8 data)
  213. {
  214. trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
  215. __raw_writeb(data, addr + offset);
  216. }
  217. static u16 musb_default_readw(void __iomem *addr, u32 offset)
  218. {
  219. u16 data = __raw_readw(addr + offset);
  220. trace_musb_readw(__builtin_return_address(0), addr, offset, data);
  221. return data;
  222. }
  223. static void musb_default_writew(void __iomem *addr, u32 offset, u16 data)
  224. {
  225. trace_musb_writew(__builtin_return_address(0), addr, offset, data);
  226. __raw_writew(data, addr + offset);
  227. }
  228. static u16 musb_default_get_toggle(struct musb_qh *qh, int is_out)
  229. {
  230. void __iomem *epio = qh->hw_ep->regs;
  231. u16 csr;
  232. if (is_out)
  233. csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
  234. else
  235. csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
  236. return csr;
  237. }
  238. static u16 musb_default_set_toggle(struct musb_qh *qh, int is_out,
  239. struct urb *urb)
  240. {
  241. u16 csr;
  242. u16 toggle;
  243. toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
  244. if (is_out)
  245. csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE
  246. | MUSB_TXCSR_H_DATATOGGLE)
  247. : MUSB_TXCSR_CLRDATATOG;
  248. else
  249. csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE
  250. | MUSB_RXCSR_H_DATATOGGLE) : 0;
  251. return csr;
  252. }
  253. /*
  254. * Load an endpoint's FIFO
  255. */
  256. static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
  257. const u8 *src)
  258. {
  259. struct musb *musb = hw_ep->musb;
  260. void __iomem *fifo = hw_ep->fifo;
  261. if (unlikely(len == 0))
  262. return;
  263. prefetch((u8 *)src);
  264. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  265. 'T', hw_ep->epnum, fifo, len, src);
  266. /* we can't assume unaligned reads work */
  267. if (likely((0x01 & (unsigned long) src) == 0)) {
  268. u16 index = 0;
  269. /* best case is 32bit-aligned source address */
  270. if ((0x02 & (unsigned long) src) == 0) {
  271. if (len >= 4) {
  272. iowrite32_rep(fifo, src + index, len >> 2);
  273. index += len & ~0x03;
  274. }
  275. if (len & 0x02) {
  276. __raw_writew(*(u16 *)&src[index], fifo);
  277. index += 2;
  278. }
  279. } else {
  280. if (len >= 2) {
  281. iowrite16_rep(fifo, src + index, len >> 1);
  282. index += len & ~0x01;
  283. }
  284. }
  285. if (len & 0x01)
  286. __raw_writeb(src[index], fifo);
  287. } else {
  288. /* byte aligned */
  289. iowrite8_rep(fifo, src, len);
  290. }
  291. }
  292. /*
  293. * Unload an endpoint's FIFO
  294. */
  295. static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  296. {
  297. struct musb *musb = hw_ep->musb;
  298. void __iomem *fifo = hw_ep->fifo;
  299. if (unlikely(len == 0))
  300. return;
  301. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  302. 'R', hw_ep->epnum, fifo, len, dst);
  303. /* we can't assume unaligned writes work */
  304. if (likely((0x01 & (unsigned long) dst) == 0)) {
  305. u16 index = 0;
  306. /* best case is 32bit-aligned destination address */
  307. if ((0x02 & (unsigned long) dst) == 0) {
  308. if (len >= 4) {
  309. ioread32_rep(fifo, dst, len >> 2);
  310. index = len & ~0x03;
  311. }
  312. if (len & 0x02) {
  313. *(u16 *)&dst[index] = __raw_readw(fifo);
  314. index += 2;
  315. }
  316. } else {
  317. if (len >= 2) {
  318. ioread16_rep(fifo, dst, len >> 1);
  319. index = len & ~0x01;
  320. }
  321. }
  322. if (len & 0x01)
  323. dst[index] = __raw_readb(fifo);
  324. } else {
  325. /* byte aligned */
  326. ioread8_rep(fifo, dst, len);
  327. }
  328. }
  329. /*
  330. * Old style IO functions
  331. */
  332. u8 (*musb_readb)(void __iomem *addr, u32 offset);
  333. EXPORT_SYMBOL_GPL(musb_readb);
  334. void (*musb_writeb)(void __iomem *addr, u32 offset, u8 data);
  335. EXPORT_SYMBOL_GPL(musb_writeb);
  336. u8 (*musb_clearb)(void __iomem *addr, u32 offset);
  337. EXPORT_SYMBOL_GPL(musb_clearb);
  338. u16 (*musb_readw)(void __iomem *addr, u32 offset);
  339. EXPORT_SYMBOL_GPL(musb_readw);
  340. void (*musb_writew)(void __iomem *addr, u32 offset, u16 data);
  341. EXPORT_SYMBOL_GPL(musb_writew);
  342. u16 (*musb_clearw)(void __iomem *addr, u32 offset);
  343. EXPORT_SYMBOL_GPL(musb_clearw);
  344. u32 musb_readl(void __iomem *addr, u32 offset)
  345. {
  346. u32 data = __raw_readl(addr + offset);
  347. trace_musb_readl(__builtin_return_address(0), addr, offset, data);
  348. return data;
  349. }
  350. EXPORT_SYMBOL_GPL(musb_readl);
  351. void musb_writel(void __iomem *addr, u32 offset, u32 data)
  352. {
  353. trace_musb_writel(__builtin_return_address(0), addr, offset, data);
  354. __raw_writel(data, addr + offset);
  355. }
  356. EXPORT_SYMBOL_GPL(musb_writel);
  357. #ifndef CONFIG_MUSB_PIO_ONLY
  358. struct dma_controller *
  359. (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
  360. EXPORT_SYMBOL(musb_dma_controller_create);
  361. void (*musb_dma_controller_destroy)(struct dma_controller *c);
  362. EXPORT_SYMBOL(musb_dma_controller_destroy);
  363. #endif
  364. /*
  365. * New style IO functions
  366. */
  367. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  368. {
  369. return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
  370. }
  371. void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  372. {
  373. return hw_ep->musb->io.write_fifo(hw_ep, len, src);
  374. }
  375. static u8 musb_read_devctl(struct musb *musb)
  376. {
  377. return musb_readb(musb->mregs, MUSB_DEVCTL);
  378. }
  379. /**
  380. * musb_set_host - set and initialize host mode
  381. * @musb: musb controller driver data
  382. *
  383. * At least some musb revisions need to enable devctl session bit in
  384. * peripheral mode to switch to host mode. Initializes things to host
  385. * mode and sets A_IDLE. SoC glue needs to advance state further
  386. * based on phy provided VBUS state.
  387. *
  388. * Note that the SoC glue code may need to wait for musb to settle
  389. * on enable before calling this to avoid babble.
  390. */
  391. int musb_set_host(struct musb *musb)
  392. {
  393. int error = 0;
  394. u8 devctl;
  395. if (!musb)
  396. return -EINVAL;
  397. devctl = musb_read_devctl(musb);
  398. if (!(devctl & MUSB_DEVCTL_BDEVICE)) {
  399. dev_info(musb->controller,
  400. "%s: already in host mode: %02x\n",
  401. __func__, devctl);
  402. goto init_data;
  403. }
  404. devctl |= MUSB_DEVCTL_SESSION;
  405. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  406. error = readx_poll_timeout(musb_read_devctl, musb, devctl,
  407. !(devctl & MUSB_DEVCTL_BDEVICE), 5000,
  408. 1000000);
  409. if (error) {
  410. dev_err(musb->controller, "%s: could not set host: %02x\n",
  411. __func__, devctl);
  412. return error;
  413. }
  414. init_data:
  415. musb->is_active = 1;
  416. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  417. MUSB_HST_MODE(musb);
  418. return error;
  419. }
  420. EXPORT_SYMBOL_GPL(musb_set_host);
  421. /**
  422. * musb_set_peripheral - set and initialize peripheral mode
  423. * @musb: musb controller driver data
  424. *
  425. * Clears devctl session bit and initializes things for peripheral
  426. * mode and sets B_IDLE. SoC glue needs to advance state further
  427. * based on phy provided VBUS state.
  428. */
  429. int musb_set_peripheral(struct musb *musb)
  430. {
  431. int error = 0;
  432. u8 devctl;
  433. if (!musb)
  434. return -EINVAL;
  435. devctl = musb_read_devctl(musb);
  436. if (devctl & MUSB_DEVCTL_BDEVICE) {
  437. dev_info(musb->controller,
  438. "%s: already in peripheral mode: %02x\n",
  439. __func__, devctl);
  440. goto init_data;
  441. }
  442. devctl &= ~MUSB_DEVCTL_SESSION;
  443. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  444. error = readx_poll_timeout(musb_read_devctl, musb, devctl,
  445. devctl & MUSB_DEVCTL_BDEVICE, 5000,
  446. 1000000);
  447. if (error) {
  448. dev_err(musb->controller, "%s: could not set peripheral: %02x\n",
  449. __func__, devctl);
  450. return error;
  451. }
  452. init_data:
  453. musb->is_active = 0;
  454. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  455. MUSB_DEV_MODE(musb);
  456. return error;
  457. }
  458. EXPORT_SYMBOL_GPL(musb_set_peripheral);
  459. /*-------------------------------------------------------------------------*/
  460. /* for high speed test mode; see USB 2.0 spec 7.1.20 */
  461. static const u8 musb_test_packet[53] = {
  462. /* implicit SYNC then DATA0 to start */
  463. /* JKJKJKJK x9 */
  464. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  465. /* JJKKJJKK x8 */
  466. 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
  467. /* JJJJKKKK x8 */
  468. 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
  469. /* JJJJJJJKKKKKKK x8 */
  470. 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  471. /* JJJJJJJK x8 */
  472. 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
  473. /* JKKKKKKK x10, JK */
  474. 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
  475. /* implicit CRC16 then EOP to end */
  476. };
  477. void musb_load_testpacket(struct musb *musb)
  478. {
  479. void __iomem *regs = musb->endpoints[0].regs;
  480. musb_ep_select(musb->mregs, 0);
  481. musb_write_fifo(musb->control_ep,
  482. sizeof(musb_test_packet), musb_test_packet);
  483. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
  484. }
  485. /*-------------------------------------------------------------------------*/
  486. /*
  487. * Handles OTG hnp timeouts, such as b_ase0_brst
  488. */
  489. static void musb_otg_timer_func(struct timer_list *t)
  490. {
  491. struct musb *musb = from_timer(musb, t, otg_timer);
  492. unsigned long flags;
  493. spin_lock_irqsave(&musb->lock, flags);
  494. switch (musb->xceiv->otg->state) {
  495. case OTG_STATE_B_WAIT_ACON:
  496. musb_dbg(musb,
  497. "HNP: b_wait_acon timeout; back to b_peripheral");
  498. musb_g_disconnect(musb);
  499. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  500. musb->is_active = 0;
  501. break;
  502. case OTG_STATE_A_SUSPEND:
  503. case OTG_STATE_A_WAIT_BCON:
  504. musb_dbg(musb, "HNP: %s timeout",
  505. usb_otg_state_string(musb->xceiv->otg->state));
  506. musb_platform_set_vbus(musb, 0);
  507. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
  508. break;
  509. default:
  510. musb_dbg(musb, "HNP: Unhandled mode %s",
  511. usb_otg_state_string(musb->xceiv->otg->state));
  512. }
  513. spin_unlock_irqrestore(&musb->lock, flags);
  514. }
  515. /*
  516. * Stops the HNP transition. Caller must take care of locking.
  517. */
  518. void musb_hnp_stop(struct musb *musb)
  519. {
  520. struct usb_hcd *hcd = musb->hcd;
  521. void __iomem *mbase = musb->mregs;
  522. u8 reg;
  523. musb_dbg(musb, "HNP: stop from %s",
  524. usb_otg_state_string(musb->xceiv->otg->state));
  525. switch (musb->xceiv->otg->state) {
  526. case OTG_STATE_A_PERIPHERAL:
  527. musb_g_disconnect(musb);
  528. musb_dbg(musb, "HNP: back to %s",
  529. usb_otg_state_string(musb->xceiv->otg->state));
  530. break;
  531. case OTG_STATE_B_HOST:
  532. musb_dbg(musb, "HNP: Disabling HR");
  533. if (hcd)
  534. hcd->self.is_b_host = 0;
  535. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  536. MUSB_DEV_MODE(musb);
  537. reg = musb_readb(mbase, MUSB_POWER);
  538. reg |= MUSB_POWER_SUSPENDM;
  539. musb_writeb(mbase, MUSB_POWER, reg);
  540. /* REVISIT: Start SESSION_REQUEST here? */
  541. break;
  542. default:
  543. musb_dbg(musb, "HNP: Stopping in unknown state %s",
  544. usb_otg_state_string(musb->xceiv->otg->state));
  545. }
  546. /*
  547. * When returning to A state after HNP, avoid hub_port_rebounce(),
  548. * which cause occasional OPT A "Did not receive reset after connect"
  549. * errors.
  550. */
  551. musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
  552. }
  553. static void musb_recover_from_babble(struct musb *musb);
  554. static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
  555. {
  556. musb_dbg(musb, "RESUME (%s)",
  557. usb_otg_state_string(musb->xceiv->otg->state));
  558. if (devctl & MUSB_DEVCTL_HM) {
  559. switch (musb->xceiv->otg->state) {
  560. case OTG_STATE_A_SUSPEND:
  561. /* remote wakeup? */
  562. musb->port1_status |=
  563. (USB_PORT_STAT_C_SUSPEND << 16)
  564. | MUSB_PORT_STAT_RESUME;
  565. musb->rh_timer = jiffies
  566. + msecs_to_jiffies(USB_RESUME_TIMEOUT);
  567. musb->xceiv->otg->state = OTG_STATE_A_HOST;
  568. musb->is_active = 1;
  569. musb_host_resume_root_hub(musb);
  570. schedule_delayed_work(&musb->finish_resume_work,
  571. msecs_to_jiffies(USB_RESUME_TIMEOUT));
  572. break;
  573. case OTG_STATE_B_WAIT_ACON:
  574. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  575. musb->is_active = 1;
  576. MUSB_DEV_MODE(musb);
  577. break;
  578. default:
  579. WARNING("bogus %s RESUME (%s)\n",
  580. "host",
  581. usb_otg_state_string(musb->xceiv->otg->state));
  582. }
  583. } else {
  584. switch (musb->xceiv->otg->state) {
  585. case OTG_STATE_A_SUSPEND:
  586. /* possibly DISCONNECT is upcoming */
  587. musb->xceiv->otg->state = OTG_STATE_A_HOST;
  588. musb_host_resume_root_hub(musb);
  589. break;
  590. case OTG_STATE_B_WAIT_ACON:
  591. case OTG_STATE_B_PERIPHERAL:
  592. /* disconnect while suspended? we may
  593. * not get a disconnect irq...
  594. */
  595. if ((devctl & MUSB_DEVCTL_VBUS)
  596. != (3 << MUSB_DEVCTL_VBUS_SHIFT)
  597. ) {
  598. musb->int_usb |= MUSB_INTR_DISCONNECT;
  599. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  600. break;
  601. }
  602. musb_g_resume(musb);
  603. break;
  604. case OTG_STATE_B_IDLE:
  605. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  606. break;
  607. default:
  608. WARNING("bogus %s RESUME (%s)\n",
  609. "peripheral",
  610. usb_otg_state_string(musb->xceiv->otg->state));
  611. }
  612. }
  613. }
  614. /* return IRQ_HANDLED to tell the caller to return immediately */
  615. static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
  616. {
  617. void __iomem *mbase = musb->mregs;
  618. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
  619. && (devctl & MUSB_DEVCTL_BDEVICE)) {
  620. musb_dbg(musb, "SessReq while on B state");
  621. return IRQ_HANDLED;
  622. }
  623. musb_dbg(musb, "SESSION_REQUEST (%s)",
  624. usb_otg_state_string(musb->xceiv->otg->state));
  625. /* IRQ arrives from ID pin sense or (later, if VBUS power
  626. * is removed) SRP. responses are time critical:
  627. * - turn on VBUS (with silicon-specific mechanism)
  628. * - go through A_WAIT_VRISE
  629. * - ... to A_WAIT_BCON.
  630. * a_wait_vrise_tmout triggers VBUS_ERROR transitions
  631. */
  632. musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
  633. musb->ep0_stage = MUSB_EP0_START;
  634. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  635. MUSB_HST_MODE(musb);
  636. musb_platform_set_vbus(musb, 1);
  637. return IRQ_NONE;
  638. }
  639. static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
  640. {
  641. int ignore = 0;
  642. /* During connection as an A-Device, we may see a short
  643. * current spikes causing voltage drop, because of cable
  644. * and peripheral capacitance combined with vbus draw.
  645. * (So: less common with truly self-powered devices, where
  646. * vbus doesn't act like a power supply.)
  647. *
  648. * Such spikes are short; usually less than ~500 usec, max
  649. * of ~2 msec. That is, they're not sustained overcurrent
  650. * errors, though they're reported using VBUSERROR irqs.
  651. *
  652. * Workarounds: (a) hardware: use self powered devices.
  653. * (b) software: ignore non-repeated VBUS errors.
  654. *
  655. * REVISIT: do delays from lots of DEBUG_KERNEL checks
  656. * make trouble here, keeping VBUS < 4.4V ?
  657. */
  658. switch (musb->xceiv->otg->state) {
  659. case OTG_STATE_A_HOST:
  660. /* recovery is dicey once we've gotten past the
  661. * initial stages of enumeration, but if VBUS
  662. * stayed ok at the other end of the link, and
  663. * another reset is due (at least for high speed,
  664. * to redo the chirp etc), it might work OK...
  665. */
  666. case OTG_STATE_A_WAIT_BCON:
  667. case OTG_STATE_A_WAIT_VRISE:
  668. if (musb->vbuserr_retry) {
  669. void __iomem *mbase = musb->mregs;
  670. musb->vbuserr_retry--;
  671. ignore = 1;
  672. devctl |= MUSB_DEVCTL_SESSION;
  673. musb_writeb(mbase, MUSB_DEVCTL, devctl);
  674. } else {
  675. musb->port1_status |=
  676. USB_PORT_STAT_OVERCURRENT
  677. | (USB_PORT_STAT_C_OVERCURRENT << 16);
  678. }
  679. break;
  680. default:
  681. break;
  682. }
  683. dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
  684. "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
  685. usb_otg_state_string(musb->xceiv->otg->state),
  686. devctl,
  687. ({ char *s;
  688. switch (devctl & MUSB_DEVCTL_VBUS) {
  689. case 0 << MUSB_DEVCTL_VBUS_SHIFT:
  690. s = "<SessEnd"; break;
  691. case 1 << MUSB_DEVCTL_VBUS_SHIFT:
  692. s = "<AValid"; break;
  693. case 2 << MUSB_DEVCTL_VBUS_SHIFT:
  694. s = "<VBusValid"; break;
  695. /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
  696. default:
  697. s = "VALID"; break;
  698. } s; }),
  699. VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
  700. musb->port1_status);
  701. /* go through A_WAIT_VFALL then start a new session */
  702. if (!ignore)
  703. musb_platform_set_vbus(musb, 0);
  704. }
  705. static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
  706. {
  707. musb_dbg(musb, "SUSPEND (%s) devctl %02x",
  708. usb_otg_state_string(musb->xceiv->otg->state), devctl);
  709. switch (musb->xceiv->otg->state) {
  710. case OTG_STATE_A_PERIPHERAL:
  711. /* We also come here if the cable is removed, since
  712. * this silicon doesn't report ID-no-longer-grounded.
  713. *
  714. * We depend on T(a_wait_bcon) to shut us down, and
  715. * hope users don't do anything dicey during this
  716. * undesired detour through A_WAIT_BCON.
  717. */
  718. musb_hnp_stop(musb);
  719. musb_host_resume_root_hub(musb);
  720. musb_root_disconnect(musb);
  721. musb_platform_try_idle(musb, jiffies
  722. + msecs_to_jiffies(musb->a_wait_bcon
  723. ? : OTG_TIME_A_WAIT_BCON));
  724. break;
  725. case OTG_STATE_B_IDLE:
  726. if (!musb->is_active)
  727. break;
  728. fallthrough;
  729. case OTG_STATE_B_PERIPHERAL:
  730. musb_g_suspend(musb);
  731. musb->is_active = musb->g.b_hnp_enable;
  732. if (musb->is_active) {
  733. musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
  734. musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
  735. mod_timer(&musb->otg_timer, jiffies
  736. + msecs_to_jiffies(
  737. OTG_TIME_B_ASE0_BRST));
  738. }
  739. break;
  740. case OTG_STATE_A_WAIT_BCON:
  741. if (musb->a_wait_bcon != 0)
  742. musb_platform_try_idle(musb, jiffies
  743. + msecs_to_jiffies(musb->a_wait_bcon));
  744. break;
  745. case OTG_STATE_A_HOST:
  746. musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
  747. musb->is_active = musb->hcd->self.b_hnp_enable;
  748. break;
  749. case OTG_STATE_B_HOST:
  750. /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
  751. musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
  752. break;
  753. default:
  754. /* "should not happen" */
  755. musb->is_active = 0;
  756. break;
  757. }
  758. }
  759. static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
  760. {
  761. struct usb_hcd *hcd = musb->hcd;
  762. musb->is_active = 1;
  763. musb->ep0_stage = MUSB_EP0_START;
  764. musb->intrtxe = musb->epmask;
  765. musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
  766. musb->intrrxe = musb->epmask & 0xfffe;
  767. musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
  768. musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
  769. musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
  770. |USB_PORT_STAT_HIGH_SPEED
  771. |USB_PORT_STAT_ENABLE
  772. );
  773. musb->port1_status |= USB_PORT_STAT_CONNECTION
  774. |(USB_PORT_STAT_C_CONNECTION << 16);
  775. /* high vs full speed is just a guess until after reset */
  776. if (devctl & MUSB_DEVCTL_LSDEV)
  777. musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
  778. /* indicate new connection to OTG machine */
  779. switch (musb->xceiv->otg->state) {
  780. case OTG_STATE_B_PERIPHERAL:
  781. if (int_usb & MUSB_INTR_SUSPEND) {
  782. musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
  783. int_usb &= ~MUSB_INTR_SUSPEND;
  784. goto b_host;
  785. } else
  786. musb_dbg(musb, "CONNECT as b_peripheral???");
  787. break;
  788. case OTG_STATE_B_WAIT_ACON:
  789. musb_dbg(musb, "HNP: CONNECT, now b_host");
  790. b_host:
  791. musb->xceiv->otg->state = OTG_STATE_B_HOST;
  792. if (musb->hcd)
  793. musb->hcd->self.is_b_host = 1;
  794. del_timer(&musb->otg_timer);
  795. break;
  796. default:
  797. if ((devctl & MUSB_DEVCTL_VBUS)
  798. == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
  799. musb->xceiv->otg->state = OTG_STATE_A_HOST;
  800. if (hcd)
  801. hcd->self.is_b_host = 0;
  802. }
  803. break;
  804. }
  805. musb_host_poke_root_hub(musb);
  806. musb_dbg(musb, "CONNECT (%s) devctl %02x",
  807. usb_otg_state_string(musb->xceiv->otg->state), devctl);
  808. }
  809. static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
  810. {
  811. musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
  812. usb_otg_state_string(musb->xceiv->otg->state),
  813. MUSB_MODE(musb), devctl);
  814. switch (musb->xceiv->otg->state) {
  815. case OTG_STATE_A_HOST:
  816. case OTG_STATE_A_SUSPEND:
  817. musb_host_resume_root_hub(musb);
  818. musb_root_disconnect(musb);
  819. if (musb->a_wait_bcon != 0)
  820. musb_platform_try_idle(musb, jiffies
  821. + msecs_to_jiffies(musb->a_wait_bcon));
  822. break;
  823. case OTG_STATE_B_HOST:
  824. /* REVISIT this behaves for "real disconnect"
  825. * cases; make sure the other transitions from
  826. * from B_HOST act right too. The B_HOST code
  827. * in hnp_stop() is currently not used...
  828. */
  829. musb_root_disconnect(musb);
  830. if (musb->hcd)
  831. musb->hcd->self.is_b_host = 0;
  832. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  833. MUSB_DEV_MODE(musb);
  834. musb_g_disconnect(musb);
  835. break;
  836. case OTG_STATE_A_PERIPHERAL:
  837. musb_hnp_stop(musb);
  838. musb_root_disconnect(musb);
  839. fallthrough;
  840. case OTG_STATE_B_WAIT_ACON:
  841. case OTG_STATE_B_PERIPHERAL:
  842. case OTG_STATE_B_IDLE:
  843. musb_g_disconnect(musb);
  844. break;
  845. default:
  846. WARNING("unhandled DISCONNECT transition (%s)\n",
  847. usb_otg_state_string(musb->xceiv->otg->state));
  848. break;
  849. }
  850. }
  851. /*
  852. * mentor saves a bit: bus reset and babble share the same irq.
  853. * only host sees babble; only peripheral sees bus reset.
  854. */
  855. static void musb_handle_intr_reset(struct musb *musb)
  856. {
  857. if (is_host_active(musb)) {
  858. /*
  859. * When BABBLE happens what we can depends on which
  860. * platform MUSB is running, because some platforms
  861. * implemented proprietary means for 'recovering' from
  862. * Babble conditions. One such platform is AM335x. In
  863. * most cases, however, the only thing we can do is
  864. * drop the session.
  865. */
  866. dev_err(musb->controller, "Babble\n");
  867. musb_recover_from_babble(musb);
  868. } else {
  869. musb_dbg(musb, "BUS RESET as %s",
  870. usb_otg_state_string(musb->xceiv->otg->state));
  871. switch (musb->xceiv->otg->state) {
  872. case OTG_STATE_A_SUSPEND:
  873. musb_g_reset(musb);
  874. fallthrough;
  875. case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
  876. /* never use invalid T(a_wait_bcon) */
  877. musb_dbg(musb, "HNP: in %s, %d msec timeout",
  878. usb_otg_state_string(musb->xceiv->otg->state),
  879. TA_WAIT_BCON(musb));
  880. mod_timer(&musb->otg_timer, jiffies
  881. + msecs_to_jiffies(TA_WAIT_BCON(musb)));
  882. break;
  883. case OTG_STATE_A_PERIPHERAL:
  884. del_timer(&musb->otg_timer);
  885. musb_g_reset(musb);
  886. break;
  887. case OTG_STATE_B_WAIT_ACON:
  888. musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
  889. usb_otg_state_string(musb->xceiv->otg->state));
  890. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  891. musb_g_reset(musb);
  892. break;
  893. case OTG_STATE_B_IDLE:
  894. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  895. fallthrough;
  896. case OTG_STATE_B_PERIPHERAL:
  897. musb_g_reset(musb);
  898. break;
  899. default:
  900. musb_dbg(musb, "Unhandled BUS RESET as %s",
  901. usb_otg_state_string(musb->xceiv->otg->state));
  902. }
  903. }
  904. }
  905. /*
  906. * Interrupt Service Routine to record USB "global" interrupts.
  907. * Since these do not happen often and signify things of
  908. * paramount importance, it seems OK to check them individually;
  909. * the order of the tests is specified in the manual
  910. *
  911. * @param musb instance pointer
  912. * @param int_usb register contents
  913. * @param devctl
  914. */
  915. static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
  916. u8 devctl)
  917. {
  918. irqreturn_t handled = IRQ_NONE;
  919. musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
  920. /* in host mode, the peripheral may issue remote wakeup.
  921. * in peripheral mode, the host may resume the link.
  922. * spurious RESUME irqs happen too, paired with SUSPEND.
  923. */
  924. if (int_usb & MUSB_INTR_RESUME) {
  925. musb_handle_intr_resume(musb, devctl);
  926. handled = IRQ_HANDLED;
  927. }
  928. /* see manual for the order of the tests */
  929. if (int_usb & MUSB_INTR_SESSREQ) {
  930. if (musb_handle_intr_sessreq(musb, devctl))
  931. return IRQ_HANDLED;
  932. handled = IRQ_HANDLED;
  933. }
  934. if (int_usb & MUSB_INTR_VBUSERROR) {
  935. musb_handle_intr_vbuserr(musb, devctl);
  936. handled = IRQ_HANDLED;
  937. }
  938. if (int_usb & MUSB_INTR_SUSPEND) {
  939. musb_handle_intr_suspend(musb, devctl);
  940. handled = IRQ_HANDLED;
  941. }
  942. if (int_usb & MUSB_INTR_CONNECT) {
  943. musb_handle_intr_connect(musb, devctl, int_usb);
  944. handled = IRQ_HANDLED;
  945. }
  946. if (int_usb & MUSB_INTR_DISCONNECT) {
  947. musb_handle_intr_disconnect(musb, devctl);
  948. handled = IRQ_HANDLED;
  949. }
  950. if (int_usb & MUSB_INTR_RESET) {
  951. musb_handle_intr_reset(musb);
  952. handled = IRQ_HANDLED;
  953. }
  954. #if 0
  955. /* REVISIT ... this would be for multiplexing periodic endpoints, or
  956. * supporting transfer phasing to prevent exceeding ISO bandwidth
  957. * limits of a given frame or microframe.
  958. *
  959. * It's not needed for peripheral side, which dedicates endpoints;
  960. * though it _might_ use SOF irqs for other purposes.
  961. *
  962. * And it's not currently needed for host side, which also dedicates
  963. * endpoints, relies on TX/RX interval registers, and isn't claimed
  964. * to support ISO transfers yet.
  965. */
  966. if (int_usb & MUSB_INTR_SOF) {
  967. void __iomem *mbase = musb->mregs;
  968. struct musb_hw_ep *ep;
  969. u8 epnum;
  970. u16 frame;
  971. dev_dbg(musb->controller, "START_OF_FRAME\n");
  972. handled = IRQ_HANDLED;
  973. /* start any periodic Tx transfers waiting for current frame */
  974. frame = musb_readw(mbase, MUSB_FRAME);
  975. ep = musb->endpoints;
  976. for (epnum = 1; (epnum < musb->nr_endpoints)
  977. && (musb->epmask >= (1 << epnum));
  978. epnum++, ep++) {
  979. /*
  980. * FIXME handle framecounter wraps (12 bits)
  981. * eliminate duplicated StartUrb logic
  982. */
  983. if (ep->dwWaitFrame >= frame) {
  984. ep->dwWaitFrame = 0;
  985. pr_debug("SOF --> periodic TX%s on %d\n",
  986. ep->tx_channel ? " DMA" : "",
  987. epnum);
  988. if (!ep->tx_channel)
  989. musb_h_tx_start(musb, epnum);
  990. else
  991. cppi_hostdma_start(musb, epnum);
  992. }
  993. } /* end of for loop */
  994. }
  995. #endif
  996. schedule_delayed_work(&musb->irq_work, 0);
  997. return handled;
  998. }
  999. /*-------------------------------------------------------------------------*/
  1000. static void musb_disable_interrupts(struct musb *musb)
  1001. {
  1002. void __iomem *mbase = musb->mregs;
  1003. /* disable interrupts */
  1004. musb_writeb(mbase, MUSB_INTRUSBE, 0);
  1005. musb->intrtxe = 0;
  1006. musb_writew(mbase, MUSB_INTRTXE, 0);
  1007. musb->intrrxe = 0;
  1008. musb_writew(mbase, MUSB_INTRRXE, 0);
  1009. /* flush pending interrupts */
  1010. musb_clearb(mbase, MUSB_INTRUSB);
  1011. musb_clearw(mbase, MUSB_INTRTX);
  1012. musb_clearw(mbase, MUSB_INTRRX);
  1013. }
  1014. static void musb_enable_interrupts(struct musb *musb)
  1015. {
  1016. void __iomem *regs = musb->mregs;
  1017. /* Set INT enable registers, enable interrupts */
  1018. musb->intrtxe = musb->epmask;
  1019. musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
  1020. musb->intrrxe = musb->epmask & 0xfffe;
  1021. musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
  1022. musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
  1023. }
  1024. /*
  1025. * Program the HDRC to start (enable interrupts, dma, etc.).
  1026. */
  1027. void musb_start(struct musb *musb)
  1028. {
  1029. void __iomem *regs = musb->mregs;
  1030. u8 devctl = musb_readb(regs, MUSB_DEVCTL);
  1031. u8 power;
  1032. musb_dbg(musb, "<== devctl %02x", devctl);
  1033. musb_enable_interrupts(musb);
  1034. musb_writeb(regs, MUSB_TESTMODE, 0);
  1035. power = MUSB_POWER_ISOUPDATE;
  1036. /*
  1037. * treating UNKNOWN as unspecified maximum speed, in which case
  1038. * we will default to high-speed.
  1039. */
  1040. if (musb->config->maximum_speed == USB_SPEED_HIGH ||
  1041. musb->config->maximum_speed == USB_SPEED_UNKNOWN)
  1042. power |= MUSB_POWER_HSENAB;
  1043. musb_writeb(regs, MUSB_POWER, power);
  1044. musb->is_active = 0;
  1045. devctl = musb_readb(regs, MUSB_DEVCTL);
  1046. devctl &= ~MUSB_DEVCTL_SESSION;
  1047. /* session started after:
  1048. * (a) ID-grounded irq, host mode;
  1049. * (b) vbus present/connect IRQ, peripheral mode;
  1050. * (c) peripheral initiates, using SRP
  1051. */
  1052. if (musb->port_mode != MUSB_HOST &&
  1053. musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
  1054. (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
  1055. musb->is_active = 1;
  1056. } else {
  1057. devctl |= MUSB_DEVCTL_SESSION;
  1058. }
  1059. musb_platform_enable(musb);
  1060. musb_writeb(regs, MUSB_DEVCTL, devctl);
  1061. }
  1062. /*
  1063. * Make the HDRC stop (disable interrupts, etc.);
  1064. * reversible by musb_start
  1065. * called on gadget driver unregister
  1066. * with controller locked, irqs blocked
  1067. * acts as a NOP unless some role activated the hardware
  1068. */
  1069. void musb_stop(struct musb *musb)
  1070. {
  1071. /* stop IRQs, timers, ... */
  1072. musb_platform_disable(musb);
  1073. musb_disable_interrupts(musb);
  1074. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  1075. /* FIXME
  1076. * - mark host and/or peripheral drivers unusable/inactive
  1077. * - disable DMA (and enable it in HdrcStart)
  1078. * - make sure we can musb_start() after musb_stop(); with
  1079. * OTG mode, gadget driver module rmmod/modprobe cycles that
  1080. * - ...
  1081. */
  1082. musb_platform_try_idle(musb, 0);
  1083. }
  1084. /*-------------------------------------------------------------------------*/
  1085. /*
  1086. * The silicon either has hard-wired endpoint configurations, or else
  1087. * "dynamic fifo" sizing. The driver has support for both, though at this
  1088. * writing only the dynamic sizing is very well tested. Since we switched
  1089. * away from compile-time hardware parameters, we can no longer rely on
  1090. * dead code elimination to leave only the relevant one in the object file.
  1091. *
  1092. * We don't currently use dynamic fifo setup capability to do anything
  1093. * more than selecting one of a bunch of predefined configurations.
  1094. */
  1095. static ushort fifo_mode;
  1096. /* "modprobe ... fifo_mode=1" etc */
  1097. module_param(fifo_mode, ushort, 0);
  1098. MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
  1099. /*
  1100. * tables defining fifo_mode values. define more if you like.
  1101. * for host side, make sure both halves of ep1 are set up.
  1102. */
  1103. /* mode 0 - fits in 2KB */
  1104. static struct musb_fifo_cfg mode_0_cfg[] = {
  1105. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1106. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1107. { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
  1108. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  1109. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  1110. };
  1111. /* mode 1 - fits in 4KB */
  1112. static struct musb_fifo_cfg mode_1_cfg[] = {
  1113. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1114. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1115. { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1116. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  1117. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  1118. };
  1119. /* mode 2 - fits in 4KB */
  1120. static struct musb_fifo_cfg mode_2_cfg[] = {
  1121. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1122. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1123. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1124. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1125. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
  1126. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
  1127. };
  1128. /* mode 3 - fits in 4KB */
  1129. static struct musb_fifo_cfg mode_3_cfg[] = {
  1130. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1131. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1132. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1133. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1134. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  1135. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  1136. };
  1137. /* mode 4 - fits in 16KB */
  1138. static struct musb_fifo_cfg mode_4_cfg[] = {
  1139. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1140. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1141. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1142. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1143. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  1144. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  1145. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  1146. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  1147. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  1148. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  1149. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
  1150. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
  1151. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
  1152. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
  1153. { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
  1154. { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
  1155. { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
  1156. { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
  1157. { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
  1158. { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
  1159. { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
  1160. { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
  1161. { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
  1162. { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
  1163. { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
  1164. { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
  1165. { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
  1166. };
  1167. /* mode 5 - fits in 8KB */
  1168. static struct musb_fifo_cfg mode_5_cfg[] = {
  1169. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1170. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1171. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1172. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1173. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  1174. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  1175. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  1176. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  1177. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  1178. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  1179. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
  1180. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
  1181. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
  1182. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
  1183. { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
  1184. { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
  1185. { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
  1186. { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
  1187. { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
  1188. { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
  1189. { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
  1190. { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
  1191. { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
  1192. { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
  1193. { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
  1194. { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
  1195. { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
  1196. };
  1197. /*
  1198. * configure a fifo; for non-shared endpoints, this may be called
  1199. * once for a tx fifo and once for an rx fifo.
  1200. *
  1201. * returns negative errno or offset for next fifo.
  1202. */
  1203. static int
  1204. fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
  1205. const struct musb_fifo_cfg *cfg, u16 offset)
  1206. {
  1207. void __iomem *mbase = musb->mregs;
  1208. int size = 0;
  1209. u16 maxpacket = cfg->maxpacket;
  1210. u16 c_off = offset >> 3;
  1211. u8 c_size;
  1212. /* expect hw_ep has already been zero-initialized */
  1213. size = ffs(max(maxpacket, (u16) 8)) - 1;
  1214. maxpacket = 1 << size;
  1215. c_size = size - 3;
  1216. if (cfg->mode == BUF_DOUBLE) {
  1217. if ((offset + (maxpacket << 1)) >
  1218. (1 << (musb->config->ram_bits + 2)))
  1219. return -EMSGSIZE;
  1220. c_size |= MUSB_FIFOSZ_DPB;
  1221. } else {
  1222. if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
  1223. return -EMSGSIZE;
  1224. }
  1225. /* configure the FIFO */
  1226. musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
  1227. /* EP0 reserved endpoint for control, bidirectional;
  1228. * EP1 reserved for bulk, two unidirectional halves.
  1229. */
  1230. if (hw_ep->epnum == 1)
  1231. musb->bulk_ep = hw_ep;
  1232. /* REVISIT error check: be sure ep0 can both rx and tx ... */
  1233. switch (cfg->style) {
  1234. case FIFO_TX:
  1235. musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
  1236. musb_writew(mbase, MUSB_TXFIFOADD, c_off);
  1237. hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1238. hw_ep->max_packet_sz_tx = maxpacket;
  1239. break;
  1240. case FIFO_RX:
  1241. musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
  1242. musb_writew(mbase, MUSB_RXFIFOADD, c_off);
  1243. hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1244. hw_ep->max_packet_sz_rx = maxpacket;
  1245. break;
  1246. case FIFO_RXTX:
  1247. musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
  1248. musb_writew(mbase, MUSB_TXFIFOADD, c_off);
  1249. hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1250. hw_ep->max_packet_sz_rx = maxpacket;
  1251. musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
  1252. musb_writew(mbase, MUSB_RXFIFOADD, c_off);
  1253. hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
  1254. hw_ep->max_packet_sz_tx = maxpacket;
  1255. hw_ep->is_shared_fifo = true;
  1256. break;
  1257. }
  1258. /* NOTE rx and tx endpoint irqs aren't managed separately,
  1259. * which happens to be ok
  1260. */
  1261. musb->epmask |= (1 << hw_ep->epnum);
  1262. return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
  1263. }
  1264. static struct musb_fifo_cfg ep0_cfg = {
  1265. .style = FIFO_RXTX, .maxpacket = 64,
  1266. };
  1267. static int ep_config_from_table(struct musb *musb)
  1268. {
  1269. const struct musb_fifo_cfg *cfg;
  1270. unsigned i, n;
  1271. int offset;
  1272. struct musb_hw_ep *hw_ep = musb->endpoints;
  1273. if (musb->config->fifo_cfg) {
  1274. cfg = musb->config->fifo_cfg;
  1275. n = musb->config->fifo_cfg_size;
  1276. goto done;
  1277. }
  1278. switch (fifo_mode) {
  1279. default:
  1280. fifo_mode = 0;
  1281. fallthrough;
  1282. case 0:
  1283. cfg = mode_0_cfg;
  1284. n = ARRAY_SIZE(mode_0_cfg);
  1285. break;
  1286. case 1:
  1287. cfg = mode_1_cfg;
  1288. n = ARRAY_SIZE(mode_1_cfg);
  1289. break;
  1290. case 2:
  1291. cfg = mode_2_cfg;
  1292. n = ARRAY_SIZE(mode_2_cfg);
  1293. break;
  1294. case 3:
  1295. cfg = mode_3_cfg;
  1296. n = ARRAY_SIZE(mode_3_cfg);
  1297. break;
  1298. case 4:
  1299. cfg = mode_4_cfg;
  1300. n = ARRAY_SIZE(mode_4_cfg);
  1301. break;
  1302. case 5:
  1303. cfg = mode_5_cfg;
  1304. n = ARRAY_SIZE(mode_5_cfg);
  1305. break;
  1306. }
  1307. pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
  1308. done:
  1309. offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
  1310. /* assert(offset > 0) */
  1311. /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
  1312. * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
  1313. */
  1314. for (i = 0; i < n; i++) {
  1315. u8 epn = cfg->hw_ep_num;
  1316. if (epn >= musb->config->num_eps) {
  1317. pr_debug("%s: invalid ep %d\n",
  1318. musb_driver_name, epn);
  1319. return -EINVAL;
  1320. }
  1321. offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
  1322. if (offset < 0) {
  1323. pr_debug("%s: mem overrun, ep %d\n",
  1324. musb_driver_name, epn);
  1325. return offset;
  1326. }
  1327. epn++;
  1328. musb->nr_endpoints = max(epn, musb->nr_endpoints);
  1329. }
  1330. pr_debug("%s: %d/%d max ep, %d/%d memory\n",
  1331. musb_driver_name,
  1332. n + 1, musb->config->num_eps * 2 - 1,
  1333. offset, (1 << (musb->config->ram_bits + 2)));
  1334. if (!musb->bulk_ep) {
  1335. pr_debug("%s: missing bulk\n", musb_driver_name);
  1336. return -EINVAL;
  1337. }
  1338. return 0;
  1339. }
  1340. /*
  1341. * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
  1342. * @param musb the controller
  1343. */
  1344. static int ep_config_from_hw(struct musb *musb)
  1345. {
  1346. u8 epnum = 0;
  1347. struct musb_hw_ep *hw_ep;
  1348. void __iomem *mbase = musb->mregs;
  1349. int ret = 0;
  1350. musb_dbg(musb, "<== static silicon ep config");
  1351. /* FIXME pick up ep0 maxpacket size */
  1352. for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
  1353. musb_ep_select(mbase, epnum);
  1354. hw_ep = musb->endpoints + epnum;
  1355. ret = musb_read_fifosize(musb, hw_ep, epnum);
  1356. if (ret < 0)
  1357. break;
  1358. /* FIXME set up hw_ep->{rx,tx}_double_buffered */
  1359. /* pick an RX/TX endpoint for bulk */
  1360. if (hw_ep->max_packet_sz_tx < 512
  1361. || hw_ep->max_packet_sz_rx < 512)
  1362. continue;
  1363. /* REVISIT: this algorithm is lazy, we should at least
  1364. * try to pick a double buffered endpoint.
  1365. */
  1366. if (musb->bulk_ep)
  1367. continue;
  1368. musb->bulk_ep = hw_ep;
  1369. }
  1370. if (!musb->bulk_ep) {
  1371. pr_debug("%s: missing bulk\n", musb_driver_name);
  1372. return -EINVAL;
  1373. }
  1374. return 0;
  1375. }
  1376. enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
  1377. /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
  1378. * configure endpoints, or take their config from silicon
  1379. */
  1380. static int musb_core_init(u16 musb_type, struct musb *musb)
  1381. {
  1382. u8 reg;
  1383. char *type;
  1384. char aInfo[90];
  1385. void __iomem *mbase = musb->mregs;
  1386. int status = 0;
  1387. int i;
  1388. /* log core options (read using indexed model) */
  1389. reg = musb_read_configdata(mbase);
  1390. strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
  1391. if (reg & MUSB_CONFIGDATA_DYNFIFO) {
  1392. strcat(aInfo, ", dyn FIFOs");
  1393. musb->dyn_fifo = true;
  1394. }
  1395. if (reg & MUSB_CONFIGDATA_MPRXE) {
  1396. strcat(aInfo, ", bulk combine");
  1397. musb->bulk_combine = true;
  1398. }
  1399. if (reg & MUSB_CONFIGDATA_MPTXE) {
  1400. strcat(aInfo, ", bulk split");
  1401. musb->bulk_split = true;
  1402. }
  1403. if (reg & MUSB_CONFIGDATA_HBRXE) {
  1404. strcat(aInfo, ", HB-ISO Rx");
  1405. musb->hb_iso_rx = true;
  1406. }
  1407. if (reg & MUSB_CONFIGDATA_HBTXE) {
  1408. strcat(aInfo, ", HB-ISO Tx");
  1409. musb->hb_iso_tx = true;
  1410. }
  1411. if (reg & MUSB_CONFIGDATA_SOFTCONE)
  1412. strcat(aInfo, ", SoftConn");
  1413. pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
  1414. if (MUSB_CONTROLLER_MHDRC == musb_type) {
  1415. musb->is_multipoint = 1;
  1416. type = "M";
  1417. } else {
  1418. musb->is_multipoint = 0;
  1419. type = "";
  1420. if (IS_ENABLED(CONFIG_USB) &&
  1421. !IS_ENABLED(CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB)) {
  1422. pr_err("%s: kernel must disable external hubs, please fix the configuration\n",
  1423. musb_driver_name);
  1424. }
  1425. }
  1426. /* log release info */
  1427. musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
  1428. pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
  1429. musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
  1430. MUSB_HWVERS_MINOR(musb->hwvers),
  1431. (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
  1432. /* configure ep0 */
  1433. musb_configure_ep0(musb);
  1434. /* discover endpoint configuration */
  1435. musb->nr_endpoints = 1;
  1436. musb->epmask = 1;
  1437. if (musb->dyn_fifo)
  1438. status = ep_config_from_table(musb);
  1439. else
  1440. status = ep_config_from_hw(musb);
  1441. if (status < 0)
  1442. return status;
  1443. /* finish init, and print endpoint config */
  1444. for (i = 0; i < musb->nr_endpoints; i++) {
  1445. struct musb_hw_ep *hw_ep = musb->endpoints + i;
  1446. hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
  1447. #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
  1448. if (musb->ops->quirks & MUSB_IN_TUSB) {
  1449. hw_ep->fifo_async = musb->async + 0x400 +
  1450. musb->io.fifo_offset(i);
  1451. hw_ep->fifo_sync = musb->sync + 0x400 +
  1452. musb->io.fifo_offset(i);
  1453. hw_ep->fifo_sync_va =
  1454. musb->sync_va + 0x400 + musb->io.fifo_offset(i);
  1455. if (i == 0)
  1456. hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
  1457. else
  1458. hw_ep->conf = mbase + 0x400 +
  1459. (((i - 1) & 0xf) << 2);
  1460. }
  1461. #endif
  1462. hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
  1463. hw_ep->rx_reinit = 1;
  1464. hw_ep->tx_reinit = 1;
  1465. if (hw_ep->max_packet_sz_tx) {
  1466. musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
  1467. musb_driver_name, i,
  1468. hw_ep->is_shared_fifo ? "shared" : "tx",
  1469. hw_ep->tx_double_buffered
  1470. ? "doublebuffer, " : "",
  1471. hw_ep->max_packet_sz_tx);
  1472. }
  1473. if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
  1474. musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
  1475. musb_driver_name, i,
  1476. "rx",
  1477. hw_ep->rx_double_buffered
  1478. ? "doublebuffer, " : "",
  1479. hw_ep->max_packet_sz_rx);
  1480. }
  1481. if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
  1482. musb_dbg(musb, "hw_ep %d not configured", i);
  1483. }
  1484. return 0;
  1485. }
  1486. /*-------------------------------------------------------------------------*/
  1487. /*
  1488. * handle all the irqs defined by the HDRC core. for now we expect: other
  1489. * irq sources (phy, dma, etc) will be handled first, musb->int_* values
  1490. * will be assigned, and the irq will already have been acked.
  1491. *
  1492. * called in irq context with spinlock held, irqs blocked
  1493. */
  1494. irqreturn_t musb_interrupt(struct musb *musb)
  1495. {
  1496. irqreturn_t retval = IRQ_NONE;
  1497. unsigned long status;
  1498. unsigned long epnum;
  1499. u8 devctl;
  1500. if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
  1501. return IRQ_NONE;
  1502. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1503. trace_musb_isr(musb);
  1504. /**
  1505. * According to Mentor Graphics' documentation, flowchart on page 98,
  1506. * IRQ should be handled as follows:
  1507. *
  1508. * . Resume IRQ
  1509. * . Session Request IRQ
  1510. * . VBUS Error IRQ
  1511. * . Suspend IRQ
  1512. * . Connect IRQ
  1513. * . Disconnect IRQ
  1514. * . Reset/Babble IRQ
  1515. * . SOF IRQ (we're not using this one)
  1516. * . Endpoint 0 IRQ
  1517. * . TX Endpoints
  1518. * . RX Endpoints
  1519. *
  1520. * We will be following that flowchart in order to avoid any problems
  1521. * that might arise with internal Finite State Machine.
  1522. */
  1523. if (musb->int_usb)
  1524. retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
  1525. if (musb->int_tx & 1) {
  1526. if (is_host_active(musb))
  1527. retval |= musb_h_ep0_irq(musb);
  1528. else
  1529. retval |= musb_g_ep0_irq(musb);
  1530. /* we have just handled endpoint 0 IRQ, clear it */
  1531. musb->int_tx &= ~BIT(0);
  1532. }
  1533. status = musb->int_tx;
  1534. for_each_set_bit(epnum, &status, 16) {
  1535. retval = IRQ_HANDLED;
  1536. if (is_host_active(musb))
  1537. musb_host_tx(musb, epnum);
  1538. else
  1539. musb_g_tx(musb, epnum);
  1540. }
  1541. status = musb->int_rx;
  1542. for_each_set_bit(epnum, &status, 16) {
  1543. retval = IRQ_HANDLED;
  1544. if (is_host_active(musb))
  1545. musb_host_rx(musb, epnum);
  1546. else
  1547. musb_g_rx(musb, epnum);
  1548. }
  1549. return retval;
  1550. }
  1551. EXPORT_SYMBOL_GPL(musb_interrupt);
  1552. #ifndef CONFIG_MUSB_PIO_ONLY
  1553. static bool use_dma = true;
  1554. /* "modprobe ... use_dma=0" etc */
  1555. module_param(use_dma, bool, 0644);
  1556. MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
  1557. void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
  1558. {
  1559. /* called with controller lock already held */
  1560. if (!epnum) {
  1561. if (!is_cppi_enabled(musb)) {
  1562. /* endpoint 0 */
  1563. if (is_host_active(musb))
  1564. musb_h_ep0_irq(musb);
  1565. else
  1566. musb_g_ep0_irq(musb);
  1567. }
  1568. } else {
  1569. /* endpoints 1..15 */
  1570. if (transmit) {
  1571. if (is_host_active(musb))
  1572. musb_host_tx(musb, epnum);
  1573. else
  1574. musb_g_tx(musb, epnum);
  1575. } else {
  1576. /* receive */
  1577. if (is_host_active(musb))
  1578. musb_host_rx(musb, epnum);
  1579. else
  1580. musb_g_rx(musb, epnum);
  1581. }
  1582. }
  1583. }
  1584. EXPORT_SYMBOL_GPL(musb_dma_completion);
  1585. #else
  1586. #define use_dma 0
  1587. #endif
  1588. static int (*musb_phy_callback)(enum musb_vbus_id_status status);
  1589. /*
  1590. * musb_mailbox - optional phy notifier function
  1591. * @status phy state change
  1592. *
  1593. * Optionally gets called from the USB PHY. Note that the USB PHY must be
  1594. * disabled at the point the phy_callback is registered or unregistered.
  1595. */
  1596. int musb_mailbox(enum musb_vbus_id_status status)
  1597. {
  1598. if (musb_phy_callback)
  1599. return musb_phy_callback(status);
  1600. return -ENODEV;
  1601. };
  1602. EXPORT_SYMBOL_GPL(musb_mailbox);
  1603. /*-------------------------------------------------------------------------*/
  1604. static ssize_t
  1605. mode_show(struct device *dev, struct device_attribute *attr, char *buf)
  1606. {
  1607. struct musb *musb = dev_to_musb(dev);
  1608. unsigned long flags;
  1609. int ret;
  1610. spin_lock_irqsave(&musb->lock, flags);
  1611. ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
  1612. spin_unlock_irqrestore(&musb->lock, flags);
  1613. return ret;
  1614. }
  1615. static ssize_t
  1616. mode_store(struct device *dev, struct device_attribute *attr,
  1617. const char *buf, size_t n)
  1618. {
  1619. struct musb *musb = dev_to_musb(dev);
  1620. unsigned long flags;
  1621. int status;
  1622. spin_lock_irqsave(&musb->lock, flags);
  1623. if (sysfs_streq(buf, "host"))
  1624. status = musb_platform_set_mode(musb, MUSB_HOST);
  1625. else if (sysfs_streq(buf, "peripheral"))
  1626. status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
  1627. else if (sysfs_streq(buf, "otg"))
  1628. status = musb_platform_set_mode(musb, MUSB_OTG);
  1629. else
  1630. status = -EINVAL;
  1631. spin_unlock_irqrestore(&musb->lock, flags);
  1632. return (status == 0) ? n : status;
  1633. }
  1634. static DEVICE_ATTR_RW(mode);
  1635. static ssize_t
  1636. vbus_store(struct device *dev, struct device_attribute *attr,
  1637. const char *buf, size_t n)
  1638. {
  1639. struct musb *musb = dev_to_musb(dev);
  1640. unsigned long flags;
  1641. unsigned long val;
  1642. if (sscanf(buf, "%lu", &val) < 1) {
  1643. dev_err(dev, "Invalid VBUS timeout ms value\n");
  1644. return -EINVAL;
  1645. }
  1646. spin_lock_irqsave(&musb->lock, flags);
  1647. /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
  1648. musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
  1649. if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
  1650. musb->is_active = 0;
  1651. musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
  1652. spin_unlock_irqrestore(&musb->lock, flags);
  1653. return n;
  1654. }
  1655. static ssize_t
  1656. vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
  1657. {
  1658. struct musb *musb = dev_to_musb(dev);
  1659. unsigned long flags;
  1660. unsigned long val;
  1661. int vbus;
  1662. u8 devctl;
  1663. pm_runtime_get_sync(dev);
  1664. spin_lock_irqsave(&musb->lock, flags);
  1665. val = musb->a_wait_bcon;
  1666. vbus = musb_platform_get_vbus_status(musb);
  1667. if (vbus < 0) {
  1668. /* Use default MUSB method by means of DEVCTL register */
  1669. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1670. if ((devctl & MUSB_DEVCTL_VBUS)
  1671. == (3 << MUSB_DEVCTL_VBUS_SHIFT))
  1672. vbus = 1;
  1673. else
  1674. vbus = 0;
  1675. }
  1676. spin_unlock_irqrestore(&musb->lock, flags);
  1677. pm_runtime_put_sync(dev);
  1678. return sprintf(buf, "Vbus %s, timeout %lu msec\n",
  1679. vbus ? "on" : "off", val);
  1680. }
  1681. static DEVICE_ATTR_RW(vbus);
  1682. /* Gadget drivers can't know that a host is connected so they might want
  1683. * to start SRP, but users can. This allows userspace to trigger SRP.
  1684. */
  1685. static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
  1686. const char *buf, size_t n)
  1687. {
  1688. struct musb *musb = dev_to_musb(dev);
  1689. unsigned short srp;
  1690. if (sscanf(buf, "%hu", &srp) != 1
  1691. || (srp != 1)) {
  1692. dev_err(dev, "SRP: Value must be 1\n");
  1693. return -EINVAL;
  1694. }
  1695. if (srp == 1)
  1696. musb_g_wakeup(musb);
  1697. return n;
  1698. }
  1699. static DEVICE_ATTR_WO(srp);
  1700. static struct attribute *musb_attrs[] = {
  1701. &dev_attr_mode.attr,
  1702. &dev_attr_vbus.attr,
  1703. &dev_attr_srp.attr,
  1704. NULL
  1705. };
  1706. ATTRIBUTE_GROUPS(musb);
  1707. #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
  1708. (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
  1709. MUSB_DEVCTL_SESSION)
  1710. #define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \
  1711. (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
  1712. MUSB_DEVCTL_SESSION)
  1713. #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
  1714. MUSB_DEVCTL_SESSION)
  1715. /*
  1716. * Check the musb devctl session bit to determine if we want to
  1717. * allow PM runtime for the device. In general, we want to keep things
  1718. * active when the session bit is set except after host disconnect.
  1719. *
  1720. * Only called from musb_irq_work. If this ever needs to get called
  1721. * elsewhere, proper locking must be implemented for musb->session.
  1722. */
  1723. static void musb_pm_runtime_check_session(struct musb *musb)
  1724. {
  1725. u8 devctl, s;
  1726. int error;
  1727. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1728. /* Handle session status quirks first */
  1729. s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
  1730. MUSB_DEVCTL_HR;
  1731. switch (devctl & ~s) {
  1732. case MUSB_QUIRK_B_DISCONNECT_99:
  1733. if (musb->quirk_retries && !musb->flush_irq_work) {
  1734. musb_dbg(musb, "Poll devctl in case of suspend after disconnect\n");
  1735. schedule_delayed_work(&musb->irq_work,
  1736. msecs_to_jiffies(1000));
  1737. musb->quirk_retries--;
  1738. }
  1739. break;
  1740. case MUSB_QUIRK_B_INVALID_VBUS_91:
  1741. if (musb->quirk_retries && !musb->flush_irq_work) {
  1742. musb_dbg(musb,
  1743. "Poll devctl on invalid vbus, assume no session");
  1744. schedule_delayed_work(&musb->irq_work,
  1745. msecs_to_jiffies(1000));
  1746. musb->quirk_retries--;
  1747. return;
  1748. }
  1749. fallthrough;
  1750. case MUSB_QUIRK_A_DISCONNECT_19:
  1751. if (musb->quirk_retries && !musb->flush_irq_work) {
  1752. musb_dbg(musb,
  1753. "Poll devctl on possible host mode disconnect");
  1754. schedule_delayed_work(&musb->irq_work,
  1755. msecs_to_jiffies(1000));
  1756. musb->quirk_retries--;
  1757. return;
  1758. }
  1759. if (!musb->session)
  1760. break;
  1761. musb_dbg(musb, "Allow PM on possible host mode disconnect");
  1762. pm_runtime_mark_last_busy(musb->controller);
  1763. pm_runtime_put_autosuspend(musb->controller);
  1764. musb->session = false;
  1765. return;
  1766. default:
  1767. break;
  1768. }
  1769. /* No need to do anything if session has not changed */
  1770. s = devctl & MUSB_DEVCTL_SESSION;
  1771. if (s == musb->session)
  1772. return;
  1773. /* Block PM or allow PM? */
  1774. if (s) {
  1775. musb_dbg(musb, "Block PM on active session: %02x", devctl);
  1776. error = pm_runtime_get_sync(musb->controller);
  1777. if (error < 0)
  1778. dev_err(musb->controller, "Could not enable: %i\n",
  1779. error);
  1780. musb->quirk_retries = 3;
  1781. } else {
  1782. musb_dbg(musb, "Allow PM with no session: %02x", devctl);
  1783. pm_runtime_mark_last_busy(musb->controller);
  1784. pm_runtime_put_autosuspend(musb->controller);
  1785. }
  1786. musb->session = s;
  1787. }
  1788. /* Only used to provide driver mode change events */
  1789. static void musb_irq_work(struct work_struct *data)
  1790. {
  1791. struct musb *musb = container_of(data, struct musb, irq_work.work);
  1792. int error;
  1793. error = pm_runtime_resume_and_get(musb->controller);
  1794. if (error < 0) {
  1795. dev_err(musb->controller, "Could not enable: %i\n", error);
  1796. return;
  1797. }
  1798. musb_pm_runtime_check_session(musb);
  1799. if (musb->xceiv->otg->state != musb->xceiv_old_state) {
  1800. musb->xceiv_old_state = musb->xceiv->otg->state;
  1801. sysfs_notify(&musb->controller->kobj, NULL, "mode");
  1802. }
  1803. pm_runtime_mark_last_busy(musb->controller);
  1804. pm_runtime_put_autosuspend(musb->controller);
  1805. }
  1806. static void musb_recover_from_babble(struct musb *musb)
  1807. {
  1808. int ret;
  1809. u8 devctl;
  1810. musb_disable_interrupts(musb);
  1811. /*
  1812. * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
  1813. * it some slack and wait for 10us.
  1814. */
  1815. udelay(10);
  1816. ret = musb_platform_recover(musb);
  1817. if (ret) {
  1818. musb_enable_interrupts(musb);
  1819. return;
  1820. }
  1821. /* drop session bit */
  1822. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1823. devctl &= ~MUSB_DEVCTL_SESSION;
  1824. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  1825. /* tell usbcore about it */
  1826. musb_root_disconnect(musb);
  1827. /*
  1828. * When a babble condition occurs, the musb controller
  1829. * removes the session bit and the endpoint config is lost.
  1830. */
  1831. if (musb->dyn_fifo)
  1832. ret = ep_config_from_table(musb);
  1833. else
  1834. ret = ep_config_from_hw(musb);
  1835. /* restart session */
  1836. if (ret == 0)
  1837. musb_start(musb);
  1838. }
  1839. /* --------------------------------------------------------------------------
  1840. * Init support
  1841. */
  1842. static struct musb *allocate_instance(struct device *dev,
  1843. const struct musb_hdrc_config *config, void __iomem *mbase)
  1844. {
  1845. struct musb *musb;
  1846. struct musb_hw_ep *ep;
  1847. int epnum;
  1848. int ret;
  1849. musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
  1850. if (!musb)
  1851. return NULL;
  1852. INIT_LIST_HEAD(&musb->control);
  1853. INIT_LIST_HEAD(&musb->in_bulk);
  1854. INIT_LIST_HEAD(&musb->out_bulk);
  1855. INIT_LIST_HEAD(&musb->pending_list);
  1856. musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
  1857. musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
  1858. musb->mregs = mbase;
  1859. musb->ctrl_base = mbase;
  1860. musb->nIrq = -ENODEV;
  1861. musb->config = config;
  1862. BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
  1863. for (epnum = 0, ep = musb->endpoints;
  1864. epnum < musb->config->num_eps;
  1865. epnum++, ep++) {
  1866. ep->musb = musb;
  1867. ep->epnum = epnum;
  1868. }
  1869. musb->controller = dev;
  1870. ret = musb_host_alloc(musb);
  1871. if (ret < 0)
  1872. goto err_free;
  1873. dev_set_drvdata(dev, musb);
  1874. return musb;
  1875. err_free:
  1876. return NULL;
  1877. }
  1878. static void musb_free(struct musb *musb)
  1879. {
  1880. /* this has multiple entry modes. it handles fault cleanup after
  1881. * probe(), where things may be partially set up, as well as rmmod
  1882. * cleanup after everything's been de-activated.
  1883. */
  1884. if (musb->nIrq >= 0) {
  1885. if (musb->irq_wake)
  1886. disable_irq_wake(musb->nIrq);
  1887. free_irq(musb->nIrq, musb);
  1888. }
  1889. musb_host_free(musb);
  1890. }
  1891. struct musb_pending_work {
  1892. int (*callback)(struct musb *musb, void *data);
  1893. void *data;
  1894. struct list_head node;
  1895. };
  1896. #ifdef CONFIG_PM
  1897. /*
  1898. * Called from musb_runtime_resume(), musb_resume(), and
  1899. * musb_queue_resume_work(). Callers must take musb->lock.
  1900. */
  1901. static int musb_run_resume_work(struct musb *musb)
  1902. {
  1903. struct musb_pending_work *w, *_w;
  1904. unsigned long flags;
  1905. int error = 0;
  1906. spin_lock_irqsave(&musb->list_lock, flags);
  1907. list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
  1908. if (w->callback) {
  1909. error = w->callback(musb, w->data);
  1910. if (error < 0) {
  1911. dev_err(musb->controller,
  1912. "resume callback %p failed: %i\n",
  1913. w->callback, error);
  1914. }
  1915. }
  1916. list_del(&w->node);
  1917. devm_kfree(musb->controller, w);
  1918. }
  1919. spin_unlock_irqrestore(&musb->list_lock, flags);
  1920. return error;
  1921. }
  1922. #endif
  1923. /*
  1924. * Called to run work if device is active or else queue the work to happen
  1925. * on resume. Caller must take musb->lock and must hold an RPM reference.
  1926. *
  1927. * Note that we cowardly refuse queuing work after musb PM runtime
  1928. * resume is done calling musb_run_resume_work() and return -EINPROGRESS
  1929. * instead.
  1930. */
  1931. int musb_queue_resume_work(struct musb *musb,
  1932. int (*callback)(struct musb *musb, void *data),
  1933. void *data)
  1934. {
  1935. struct musb_pending_work *w;
  1936. unsigned long flags;
  1937. bool is_suspended;
  1938. int error;
  1939. if (WARN_ON(!callback))
  1940. return -EINVAL;
  1941. spin_lock_irqsave(&musb->list_lock, flags);
  1942. is_suspended = musb->is_runtime_suspended;
  1943. if (is_suspended) {
  1944. w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
  1945. if (!w) {
  1946. error = -ENOMEM;
  1947. goto out_unlock;
  1948. }
  1949. w->callback = callback;
  1950. w->data = data;
  1951. list_add_tail(&w->node, &musb->pending_list);
  1952. error = 0;
  1953. }
  1954. out_unlock:
  1955. spin_unlock_irqrestore(&musb->list_lock, flags);
  1956. if (!is_suspended)
  1957. error = callback(musb, data);
  1958. return error;
  1959. }
  1960. EXPORT_SYMBOL_GPL(musb_queue_resume_work);
  1961. static void musb_deassert_reset(struct work_struct *work)
  1962. {
  1963. struct musb *musb;
  1964. unsigned long flags;
  1965. musb = container_of(work, struct musb, deassert_reset_work.work);
  1966. spin_lock_irqsave(&musb->lock, flags);
  1967. if (musb->port1_status & USB_PORT_STAT_RESET)
  1968. musb_port_reset(musb, false);
  1969. spin_unlock_irqrestore(&musb->lock, flags);
  1970. }
  1971. /*
  1972. * Perform generic per-controller initialization.
  1973. *
  1974. * @dev: the controller (already clocked, etc)
  1975. * @nIrq: IRQ number
  1976. * @ctrl: virtual address of controller registers,
  1977. * not yet corrected for platform-specific offsets
  1978. */
  1979. static int
  1980. musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
  1981. {
  1982. int status;
  1983. struct musb *musb;
  1984. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  1985. /* The driver might handle more features than the board; OK.
  1986. * Fail when the board needs a feature that's not enabled.
  1987. */
  1988. if (!plat) {
  1989. dev_err(dev, "no platform_data?\n");
  1990. status = -ENODEV;
  1991. goto fail0;
  1992. }
  1993. /* allocate */
  1994. musb = allocate_instance(dev, plat->config, ctrl);
  1995. if (!musb) {
  1996. status = -ENOMEM;
  1997. goto fail0;
  1998. }
  1999. spin_lock_init(&musb->lock);
  2000. spin_lock_init(&musb->list_lock);
  2001. musb->board_set_power = plat->set_power;
  2002. musb->min_power = plat->min_power;
  2003. musb->ops = plat->platform_ops;
  2004. musb->port_mode = plat->mode;
  2005. /*
  2006. * Initialize the default IO functions. At least omap2430 needs
  2007. * these early. We initialize the platform specific IO functions
  2008. * later on.
  2009. */
  2010. musb_readb = musb_default_readb;
  2011. musb_writeb = musb_default_writeb;
  2012. musb_readw = musb_default_readw;
  2013. musb_writew = musb_default_writew;
  2014. /* The musb_platform_init() call:
  2015. * - adjusts musb->mregs
  2016. * - sets the musb->isr
  2017. * - may initialize an integrated transceiver
  2018. * - initializes musb->xceiv, usually by otg_get_phy()
  2019. * - stops powering VBUS
  2020. *
  2021. * There are various transceiver configurations.
  2022. * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
  2023. * external/discrete ones in various flavors (twl4030 family,
  2024. * isp1504, non-OTG, etc) mostly hooking up through ULPI.
  2025. */
  2026. status = musb_platform_init(musb);
  2027. if (status < 0)
  2028. goto fail1;
  2029. if (!musb->isr) {
  2030. status = -ENODEV;
  2031. goto fail2;
  2032. }
  2033. /* Most devices use indexed offset or flat offset */
  2034. if (musb->ops->quirks & MUSB_INDEXED_EP) {
  2035. musb->io.ep_offset = musb_indexed_ep_offset;
  2036. musb->io.ep_select = musb_indexed_ep_select;
  2037. } else {
  2038. musb->io.ep_offset = musb_flat_ep_offset;
  2039. musb->io.ep_select = musb_flat_ep_select;
  2040. }
  2041. if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
  2042. musb->g.quirk_avoids_skb_reserve = 1;
  2043. /* At least tusb6010 has its own offsets */
  2044. if (musb->ops->ep_offset)
  2045. musb->io.ep_offset = musb->ops->ep_offset;
  2046. if (musb->ops->ep_select)
  2047. musb->io.ep_select = musb->ops->ep_select;
  2048. if (musb->ops->fifo_mode)
  2049. fifo_mode = musb->ops->fifo_mode;
  2050. else
  2051. fifo_mode = 4;
  2052. if (musb->ops->fifo_offset)
  2053. musb->io.fifo_offset = musb->ops->fifo_offset;
  2054. else
  2055. musb->io.fifo_offset = musb_default_fifo_offset;
  2056. if (musb->ops->busctl_offset)
  2057. musb->io.busctl_offset = musb->ops->busctl_offset;
  2058. else
  2059. musb->io.busctl_offset = musb_default_busctl_offset;
  2060. if (musb->ops->readb)
  2061. musb_readb = musb->ops->readb;
  2062. if (musb->ops->writeb)
  2063. musb_writeb = musb->ops->writeb;
  2064. if (musb->ops->clearb)
  2065. musb_clearb = musb->ops->clearb;
  2066. else
  2067. musb_clearb = musb_readb;
  2068. if (musb->ops->readw)
  2069. musb_readw = musb->ops->readw;
  2070. if (musb->ops->writew)
  2071. musb_writew = musb->ops->writew;
  2072. if (musb->ops->clearw)
  2073. musb_clearw = musb->ops->clearw;
  2074. else
  2075. musb_clearw = musb_readw;
  2076. #ifndef CONFIG_MUSB_PIO_ONLY
  2077. if (!musb->ops->dma_init || !musb->ops->dma_exit) {
  2078. dev_err(dev, "DMA controller not set\n");
  2079. status = -ENODEV;
  2080. goto fail2;
  2081. }
  2082. musb_dma_controller_create = musb->ops->dma_init;
  2083. musb_dma_controller_destroy = musb->ops->dma_exit;
  2084. #endif
  2085. if (musb->ops->read_fifo)
  2086. musb->io.read_fifo = musb->ops->read_fifo;
  2087. else
  2088. musb->io.read_fifo = musb_default_read_fifo;
  2089. if (musb->ops->write_fifo)
  2090. musb->io.write_fifo = musb->ops->write_fifo;
  2091. else
  2092. musb->io.write_fifo = musb_default_write_fifo;
  2093. if (musb->ops->get_toggle)
  2094. musb->io.get_toggle = musb->ops->get_toggle;
  2095. else
  2096. musb->io.get_toggle = musb_default_get_toggle;
  2097. if (musb->ops->set_toggle)
  2098. musb->io.set_toggle = musb->ops->set_toggle;
  2099. else
  2100. musb->io.set_toggle = musb_default_set_toggle;
  2101. if (!musb->xceiv->io_ops) {
  2102. musb->xceiv->io_dev = musb->controller;
  2103. musb->xceiv->io_priv = musb->mregs;
  2104. musb->xceiv->io_ops = &musb_ulpi_access;
  2105. }
  2106. if (musb->ops->phy_callback)
  2107. musb_phy_callback = musb->ops->phy_callback;
  2108. /*
  2109. * We need musb_read/write functions initialized for PM.
  2110. * Note that at least 2430 glue needs autosuspend delay
  2111. * somewhere above 300 ms for the hardware to idle properly
  2112. * after disconnecting the cable in host mode. Let's use
  2113. * 500 ms for some margin.
  2114. */
  2115. pm_runtime_use_autosuspend(musb->controller);
  2116. pm_runtime_set_autosuspend_delay(musb->controller, 500);
  2117. pm_runtime_enable(musb->controller);
  2118. pm_runtime_get_sync(musb->controller);
  2119. status = usb_phy_init(musb->xceiv);
  2120. if (status < 0)
  2121. goto err_usb_phy_init;
  2122. if (use_dma && dev->dma_mask) {
  2123. musb->dma_controller =
  2124. musb_dma_controller_create(musb, musb->mregs);
  2125. if (IS_ERR(musb->dma_controller)) {
  2126. status = PTR_ERR(musb->dma_controller);
  2127. goto fail2_5;
  2128. }
  2129. }
  2130. /* be sure interrupts are disabled before connecting ISR */
  2131. musb_platform_disable(musb);
  2132. musb_disable_interrupts(musb);
  2133. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  2134. /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
  2135. musb_writeb(musb->mregs, MUSB_POWER, 0);
  2136. /* Init IRQ workqueue before request_irq */
  2137. INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
  2138. INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
  2139. INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
  2140. /* setup musb parts of the core (especially endpoints) */
  2141. status = musb_core_init(plat->config->multipoint
  2142. ? MUSB_CONTROLLER_MHDRC
  2143. : MUSB_CONTROLLER_HDRC, musb);
  2144. if (status < 0)
  2145. goto fail3;
  2146. timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
  2147. /* attach to the IRQ */
  2148. if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
  2149. dev_err(dev, "request_irq %d failed!\n", nIrq);
  2150. status = -ENODEV;
  2151. goto fail3;
  2152. }
  2153. musb->nIrq = nIrq;
  2154. /* FIXME this handles wakeup irqs wrong */
  2155. if (enable_irq_wake(nIrq) == 0) {
  2156. musb->irq_wake = 1;
  2157. device_init_wakeup(dev, 1);
  2158. } else {
  2159. musb->irq_wake = 0;
  2160. }
  2161. /* program PHY to use external vBus if required */
  2162. if (plat->extvbus) {
  2163. u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
  2164. busctl |= MUSB_ULPI_USE_EXTVBUS;
  2165. musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
  2166. }
  2167. MUSB_DEV_MODE(musb);
  2168. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  2169. switch (musb->port_mode) {
  2170. case MUSB_HOST:
  2171. status = musb_host_setup(musb, plat->power);
  2172. if (status < 0)
  2173. goto fail3;
  2174. status = musb_platform_set_mode(musb, MUSB_HOST);
  2175. break;
  2176. case MUSB_PERIPHERAL:
  2177. status = musb_gadget_setup(musb);
  2178. if (status < 0)
  2179. goto fail3;
  2180. status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
  2181. break;
  2182. case MUSB_OTG:
  2183. status = musb_host_setup(musb, plat->power);
  2184. if (status < 0)
  2185. goto fail3;
  2186. status = musb_gadget_setup(musb);
  2187. if (status) {
  2188. musb_host_cleanup(musb);
  2189. goto fail3;
  2190. }
  2191. status = musb_platform_set_mode(musb, MUSB_OTG);
  2192. break;
  2193. default:
  2194. dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
  2195. break;
  2196. }
  2197. if (status < 0)
  2198. goto fail3;
  2199. musb_init_debugfs(musb);
  2200. musb->is_initialized = 1;
  2201. pm_runtime_mark_last_busy(musb->controller);
  2202. pm_runtime_put_autosuspend(musb->controller);
  2203. return 0;
  2204. fail3:
  2205. cancel_delayed_work_sync(&musb->irq_work);
  2206. cancel_delayed_work_sync(&musb->finish_resume_work);
  2207. cancel_delayed_work_sync(&musb->deassert_reset_work);
  2208. if (musb->dma_controller)
  2209. musb_dma_controller_destroy(musb->dma_controller);
  2210. fail2_5:
  2211. usb_phy_shutdown(musb->xceiv);
  2212. err_usb_phy_init:
  2213. pm_runtime_dont_use_autosuspend(musb->controller);
  2214. pm_runtime_put_sync(musb->controller);
  2215. pm_runtime_disable(musb->controller);
  2216. fail2:
  2217. if (musb->irq_wake)
  2218. device_init_wakeup(dev, 0);
  2219. musb_platform_exit(musb);
  2220. fail1:
  2221. if (status != -EPROBE_DEFER)
  2222. dev_err(musb->controller,
  2223. "%s failed with status %d\n", __func__, status);
  2224. musb_free(musb);
  2225. fail0:
  2226. return status;
  2227. }
  2228. /*-------------------------------------------------------------------------*/
  2229. /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
  2230. * bridge to a platform device; this driver then suffices.
  2231. */
  2232. static int musb_probe(struct platform_device *pdev)
  2233. {
  2234. struct device *dev = &pdev->dev;
  2235. int irq = platform_get_irq_byname(pdev, "mc");
  2236. void __iomem *base;
  2237. if (irq <= 0)
  2238. return -ENODEV;
  2239. base = devm_platform_ioremap_resource(pdev, 0);
  2240. if (IS_ERR(base))
  2241. return PTR_ERR(base);
  2242. return musb_init_controller(dev, irq, base);
  2243. }
  2244. static int musb_remove(struct platform_device *pdev)
  2245. {
  2246. struct device *dev = &pdev->dev;
  2247. struct musb *musb = dev_to_musb(dev);
  2248. unsigned long flags;
  2249. /* this gets called on rmmod.
  2250. * - Host mode: host may still be active
  2251. * - Peripheral mode: peripheral is deactivated (or never-activated)
  2252. * - OTG mode: both roles are deactivated (or never-activated)
  2253. */
  2254. musb_exit_debugfs(musb);
  2255. cancel_delayed_work_sync(&musb->irq_work);
  2256. cancel_delayed_work_sync(&musb->finish_resume_work);
  2257. cancel_delayed_work_sync(&musb->deassert_reset_work);
  2258. pm_runtime_get_sync(musb->controller);
  2259. musb_host_cleanup(musb);
  2260. musb_gadget_cleanup(musb);
  2261. musb_platform_disable(musb);
  2262. spin_lock_irqsave(&musb->lock, flags);
  2263. musb_disable_interrupts(musb);
  2264. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  2265. spin_unlock_irqrestore(&musb->lock, flags);
  2266. musb_platform_exit(musb);
  2267. pm_runtime_dont_use_autosuspend(musb->controller);
  2268. pm_runtime_put_sync(musb->controller);
  2269. pm_runtime_disable(musb->controller);
  2270. musb_phy_callback = NULL;
  2271. if (musb->dma_controller)
  2272. musb_dma_controller_destroy(musb->dma_controller);
  2273. usb_phy_shutdown(musb->xceiv);
  2274. musb_free(musb);
  2275. device_init_wakeup(dev, 0);
  2276. return 0;
  2277. }
  2278. #ifdef CONFIG_PM
  2279. static void musb_save_context(struct musb *musb)
  2280. {
  2281. int i;
  2282. void __iomem *musb_base = musb->mregs;
  2283. void __iomem *epio;
  2284. musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
  2285. musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
  2286. musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
  2287. musb->context.power = musb_readb(musb_base, MUSB_POWER);
  2288. musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
  2289. musb->context.index = musb_readb(musb_base, MUSB_INDEX);
  2290. musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
  2291. for (i = 0; i < musb->config->num_eps; ++i) {
  2292. struct musb_hw_ep *hw_ep;
  2293. hw_ep = &musb->endpoints[i];
  2294. if (!hw_ep)
  2295. continue;
  2296. epio = hw_ep->regs;
  2297. if (!epio)
  2298. continue;
  2299. musb_writeb(musb_base, MUSB_INDEX, i);
  2300. musb->context.index_regs[i].txmaxp =
  2301. musb_readw(epio, MUSB_TXMAXP);
  2302. musb->context.index_regs[i].txcsr =
  2303. musb_readw(epio, MUSB_TXCSR);
  2304. musb->context.index_regs[i].rxmaxp =
  2305. musb_readw(epio, MUSB_RXMAXP);
  2306. musb->context.index_regs[i].rxcsr =
  2307. musb_readw(epio, MUSB_RXCSR);
  2308. if (musb->dyn_fifo) {
  2309. musb->context.index_regs[i].txfifoadd =
  2310. musb_readw(musb_base, MUSB_TXFIFOADD);
  2311. musb->context.index_regs[i].rxfifoadd =
  2312. musb_readw(musb_base, MUSB_RXFIFOADD);
  2313. musb->context.index_regs[i].txfifosz =
  2314. musb_readb(musb_base, MUSB_TXFIFOSZ);
  2315. musb->context.index_regs[i].rxfifosz =
  2316. musb_readb(musb_base, MUSB_RXFIFOSZ);
  2317. }
  2318. musb->context.index_regs[i].txtype =
  2319. musb_readb(epio, MUSB_TXTYPE);
  2320. musb->context.index_regs[i].txinterval =
  2321. musb_readb(epio, MUSB_TXINTERVAL);
  2322. musb->context.index_regs[i].rxtype =
  2323. musb_readb(epio, MUSB_RXTYPE);
  2324. musb->context.index_regs[i].rxinterval =
  2325. musb_readb(epio, MUSB_RXINTERVAL);
  2326. musb->context.index_regs[i].txfunaddr =
  2327. musb_read_txfunaddr(musb, i);
  2328. musb->context.index_regs[i].txhubaddr =
  2329. musb_read_txhubaddr(musb, i);
  2330. musb->context.index_regs[i].txhubport =
  2331. musb_read_txhubport(musb, i);
  2332. musb->context.index_regs[i].rxfunaddr =
  2333. musb_read_rxfunaddr(musb, i);
  2334. musb->context.index_regs[i].rxhubaddr =
  2335. musb_read_rxhubaddr(musb, i);
  2336. musb->context.index_regs[i].rxhubport =
  2337. musb_read_rxhubport(musb, i);
  2338. }
  2339. }
  2340. static void musb_restore_context(struct musb *musb)
  2341. {
  2342. int i;
  2343. void __iomem *musb_base = musb->mregs;
  2344. void __iomem *epio;
  2345. u8 power;
  2346. musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
  2347. musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
  2348. musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
  2349. /* Don't affect SUSPENDM/RESUME bits in POWER reg */
  2350. power = musb_readb(musb_base, MUSB_POWER);
  2351. power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
  2352. musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
  2353. power |= musb->context.power;
  2354. musb_writeb(musb_base, MUSB_POWER, power);
  2355. musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
  2356. musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
  2357. musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
  2358. if (musb->context.devctl & MUSB_DEVCTL_SESSION)
  2359. musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
  2360. for (i = 0; i < musb->config->num_eps; ++i) {
  2361. struct musb_hw_ep *hw_ep;
  2362. hw_ep = &musb->endpoints[i];
  2363. if (!hw_ep)
  2364. continue;
  2365. epio = hw_ep->regs;
  2366. if (!epio)
  2367. continue;
  2368. musb_writeb(musb_base, MUSB_INDEX, i);
  2369. musb_writew(epio, MUSB_TXMAXP,
  2370. musb->context.index_regs[i].txmaxp);
  2371. musb_writew(epio, MUSB_TXCSR,
  2372. musb->context.index_regs[i].txcsr);
  2373. musb_writew(epio, MUSB_RXMAXP,
  2374. musb->context.index_regs[i].rxmaxp);
  2375. musb_writew(epio, MUSB_RXCSR,
  2376. musb->context.index_regs[i].rxcsr);
  2377. if (musb->dyn_fifo) {
  2378. musb_writeb(musb_base, MUSB_TXFIFOSZ,
  2379. musb->context.index_regs[i].txfifosz);
  2380. musb_writeb(musb_base, MUSB_RXFIFOSZ,
  2381. musb->context.index_regs[i].rxfifosz);
  2382. musb_writew(musb_base, MUSB_TXFIFOADD,
  2383. musb->context.index_regs[i].txfifoadd);
  2384. musb_writew(musb_base, MUSB_RXFIFOADD,
  2385. musb->context.index_regs[i].rxfifoadd);
  2386. }
  2387. musb_writeb(epio, MUSB_TXTYPE,
  2388. musb->context.index_regs[i].txtype);
  2389. musb_writeb(epio, MUSB_TXINTERVAL,
  2390. musb->context.index_regs[i].txinterval);
  2391. musb_writeb(epio, MUSB_RXTYPE,
  2392. musb->context.index_regs[i].rxtype);
  2393. musb_writeb(epio, MUSB_RXINTERVAL,
  2394. musb->context.index_regs[i].rxinterval);
  2395. musb_write_txfunaddr(musb, i,
  2396. musb->context.index_regs[i].txfunaddr);
  2397. musb_write_txhubaddr(musb, i,
  2398. musb->context.index_regs[i].txhubaddr);
  2399. musb_write_txhubport(musb, i,
  2400. musb->context.index_regs[i].txhubport);
  2401. musb_write_rxfunaddr(musb, i,
  2402. musb->context.index_regs[i].rxfunaddr);
  2403. musb_write_rxhubaddr(musb, i,
  2404. musb->context.index_regs[i].rxhubaddr);
  2405. musb_write_rxhubport(musb, i,
  2406. musb->context.index_regs[i].rxhubport);
  2407. }
  2408. musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
  2409. }
  2410. static int musb_suspend(struct device *dev)
  2411. {
  2412. struct musb *musb = dev_to_musb(dev);
  2413. unsigned long flags;
  2414. int ret;
  2415. ret = pm_runtime_get_sync(dev);
  2416. if (ret < 0) {
  2417. pm_runtime_put_noidle(dev);
  2418. return ret;
  2419. }
  2420. musb_platform_disable(musb);
  2421. musb_disable_interrupts(musb);
  2422. musb->flush_irq_work = true;
  2423. while (flush_delayed_work(&musb->irq_work))
  2424. ;
  2425. musb->flush_irq_work = false;
  2426. if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
  2427. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  2428. WARN_ON(!list_empty(&musb->pending_list));
  2429. spin_lock_irqsave(&musb->lock, flags);
  2430. if (is_peripheral_active(musb)) {
  2431. /* FIXME force disconnect unless we know USB will wake
  2432. * the system up quickly enough to respond ...
  2433. */
  2434. } else if (is_host_active(musb)) {
  2435. /* we know all the children are suspended; sometimes
  2436. * they will even be wakeup-enabled.
  2437. */
  2438. }
  2439. musb_save_context(musb);
  2440. spin_unlock_irqrestore(&musb->lock, flags);
  2441. return 0;
  2442. }
  2443. static int musb_resume(struct device *dev)
  2444. {
  2445. struct musb *musb = dev_to_musb(dev);
  2446. unsigned long flags;
  2447. int error;
  2448. u8 devctl;
  2449. u8 mask;
  2450. /*
  2451. * For static cmos like DaVinci, register values were preserved
  2452. * unless for some reason the whole soc powered down or the USB
  2453. * module got reset through the PSC (vs just being disabled).
  2454. *
  2455. * For the DSPS glue layer though, a full register restore has to
  2456. * be done. As it shouldn't harm other platforms, we do it
  2457. * unconditionally.
  2458. */
  2459. musb_restore_context(musb);
  2460. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  2461. mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
  2462. if ((devctl & mask) != (musb->context.devctl & mask))
  2463. musb->port1_status = 0;
  2464. musb_enable_interrupts(musb);
  2465. musb_platform_enable(musb);
  2466. /* session might be disabled in suspend */
  2467. if (musb->port_mode == MUSB_HOST &&
  2468. !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
  2469. devctl |= MUSB_DEVCTL_SESSION;
  2470. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  2471. }
  2472. spin_lock_irqsave(&musb->lock, flags);
  2473. error = musb_run_resume_work(musb);
  2474. if (error)
  2475. dev_err(musb->controller, "resume work failed with %i\n",
  2476. error);
  2477. spin_unlock_irqrestore(&musb->lock, flags);
  2478. pm_runtime_mark_last_busy(dev);
  2479. pm_runtime_put_autosuspend(dev);
  2480. return 0;
  2481. }
  2482. static int musb_runtime_suspend(struct device *dev)
  2483. {
  2484. struct musb *musb = dev_to_musb(dev);
  2485. musb_save_context(musb);
  2486. musb->is_runtime_suspended = 1;
  2487. return 0;
  2488. }
  2489. static int musb_runtime_resume(struct device *dev)
  2490. {
  2491. struct musb *musb = dev_to_musb(dev);
  2492. unsigned long flags;
  2493. int error;
  2494. /*
  2495. * When pm_runtime_get_sync called for the first time in driver
  2496. * init, some of the structure is still not initialized which is
  2497. * used in restore function. But clock needs to be
  2498. * enabled before any register access, so
  2499. * pm_runtime_get_sync has to be called.
  2500. * Also context restore without save does not make
  2501. * any sense
  2502. */
  2503. if (!musb->is_initialized)
  2504. return 0;
  2505. musb_restore_context(musb);
  2506. spin_lock_irqsave(&musb->lock, flags);
  2507. error = musb_run_resume_work(musb);
  2508. if (error)
  2509. dev_err(musb->controller, "resume work failed with %i\n",
  2510. error);
  2511. musb->is_runtime_suspended = 0;
  2512. spin_unlock_irqrestore(&musb->lock, flags);
  2513. return 0;
  2514. }
  2515. static const struct dev_pm_ops musb_dev_pm_ops = {
  2516. .suspend = musb_suspend,
  2517. .resume = musb_resume,
  2518. .runtime_suspend = musb_runtime_suspend,
  2519. .runtime_resume = musb_runtime_resume,
  2520. };
  2521. #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
  2522. #else
  2523. #define MUSB_DEV_PM_OPS NULL
  2524. #endif
  2525. static struct platform_driver musb_driver = {
  2526. .driver = {
  2527. .name = musb_driver_name,
  2528. .bus = &platform_bus_type,
  2529. .pm = MUSB_DEV_PM_OPS,
  2530. .dev_groups = musb_groups,
  2531. },
  2532. .probe = musb_probe,
  2533. .remove = musb_remove,
  2534. };
  2535. module_platform_driver(musb_driver);