cppi_dma.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright (C) 2005-2006 by Texas Instruments */
  3. #ifndef _CPPI_DMA_H_
  4. #define _CPPI_DMA_H_
  5. #include <linux/slab.h>
  6. #include <linux/list.h>
  7. #include <linux/errno.h>
  8. #include <linux/dmapool.h>
  9. #include <linux/dmaengine.h>
  10. #include "musb_core.h"
  11. #include "musb_dma.h"
  12. /* CPPI RX/TX state RAM */
  13. struct cppi_tx_stateram {
  14. u32 tx_head; /* "DMA packet" head descriptor */
  15. u32 tx_buf;
  16. u32 tx_current; /* current descriptor */
  17. u32 tx_buf_current;
  18. u32 tx_info; /* flags, remaining buflen */
  19. u32 tx_rem_len;
  20. u32 tx_dummy; /* unused */
  21. u32 tx_complete;
  22. };
  23. struct cppi_rx_stateram {
  24. u32 rx_skipbytes;
  25. u32 rx_head;
  26. u32 rx_sop; /* "DMA packet" head descriptor */
  27. u32 rx_current; /* current descriptor */
  28. u32 rx_buf_current;
  29. u32 rx_len_len;
  30. u32 rx_cnt_cnt;
  31. u32 rx_complete;
  32. };
  33. /* hw_options bits in CPPI buffer descriptors */
  34. #define CPPI_SOP_SET ((u32)(1 << 31))
  35. #define CPPI_EOP_SET ((u32)(1 << 30))
  36. #define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */
  37. #define CPPI_EOQ_MASK ((u32)(1 << 28))
  38. #define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */
  39. #define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */
  40. #define CPPI_RECV_PKTLEN_MASK 0xFFFF
  41. #define CPPI_BUFFER_LEN_MASK 0xFFFF
  42. #define CPPI_TEAR_READY ((u32)(1 << 31))
  43. /* CPPI data structure definitions */
  44. #define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */
  45. struct cppi_descriptor {
  46. /* hardware overlay */
  47. u32 hw_next; /* next buffer descriptor Pointer */
  48. u32 hw_bufp; /* i/o buffer pointer */
  49. u32 hw_off_len; /* buffer_offset16, buffer_length16 */
  50. u32 hw_options; /* flags: SOP, EOP etc*/
  51. struct cppi_descriptor *next;
  52. dma_addr_t dma; /* address of this descriptor */
  53. u32 buflen; /* for RX: original buffer length */
  54. } __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
  55. struct cppi;
  56. /* CPPI Channel Control structure */
  57. struct cppi_channel {
  58. struct dma_channel channel;
  59. /* back pointer to the DMA controller structure */
  60. struct cppi *controller;
  61. /* which direction of which endpoint? */
  62. struct musb_hw_ep *hw_ep;
  63. bool transmit;
  64. u8 index;
  65. /* DMA modes: RNDIS or "transparent" */
  66. u8 is_rndis;
  67. /* book keeping for current transfer request */
  68. dma_addr_t buf_dma;
  69. u32 buf_len;
  70. u32 maxpacket;
  71. u32 offset; /* dma requested */
  72. void __iomem *state_ram; /* CPPI state */
  73. struct cppi_descriptor *freelist;
  74. /* BD management fields */
  75. struct cppi_descriptor *head;
  76. struct cppi_descriptor *tail;
  77. struct cppi_descriptor *last_processed;
  78. /* use tx_complete in host role to track endpoints waiting for
  79. * FIFONOTEMPTY to clear.
  80. */
  81. struct list_head tx_complete;
  82. };
  83. /* CPPI DMA controller object */
  84. struct cppi {
  85. struct dma_controller controller;
  86. void __iomem *mregs; /* Mentor regs */
  87. void __iomem *tibase; /* TI/CPPI regs */
  88. int irq;
  89. struct cppi_channel tx[4];
  90. struct cppi_channel rx[4];
  91. struct dma_pool *pool;
  92. struct list_head tx_complete;
  93. };
  94. /* CPPI IRQ handler */
  95. extern irqreturn_t cppi_interrupt(int, void *);
  96. struct cppi41_dma_channel {
  97. struct dma_channel channel;
  98. struct cppi41_dma_controller *controller;
  99. struct musb_hw_ep *hw_ep;
  100. struct dma_chan *dc;
  101. dma_cookie_t cookie;
  102. u8 port_num;
  103. u8 is_tx;
  104. u8 is_allocated;
  105. u8 usb_toggle;
  106. dma_addr_t buf_addr;
  107. u32 total_len;
  108. u32 prog_len;
  109. u32 transferred;
  110. u32 packet_sz;
  111. struct list_head tx_check;
  112. int tx_zlp;
  113. };
  114. #endif /* end of ifndef _CPPI_DMA_H_ */