am35x.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments AM35x "glue layer"
  4. *
  5. * Copyright (c) 2010, by Texas Instruments
  6. *
  7. * Based on the DA8xx "glue layer" code.
  8. * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  9. *
  10. * This file is part of the Inventra Controller Driver for Linux.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/clk.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/usb/usb_phy_generic.h>
  19. #include <linux/platform_data/usb-omap.h>
  20. #include "musb_core.h"
  21. /*
  22. * AM35x specific definitions
  23. */
  24. /* USB 2.0 OTG module registers */
  25. #define USB_REVISION_REG 0x00
  26. #define USB_CTRL_REG 0x04
  27. #define USB_STAT_REG 0x08
  28. #define USB_EMULATION_REG 0x0c
  29. /* 0x10 Reserved */
  30. #define USB_AUTOREQ_REG 0x14
  31. #define USB_SRP_FIX_TIME_REG 0x18
  32. #define USB_TEARDOWN_REG 0x1c
  33. #define EP_INTR_SRC_REG 0x20
  34. #define EP_INTR_SRC_SET_REG 0x24
  35. #define EP_INTR_SRC_CLEAR_REG 0x28
  36. #define EP_INTR_MASK_REG 0x2c
  37. #define EP_INTR_MASK_SET_REG 0x30
  38. #define EP_INTR_MASK_CLEAR_REG 0x34
  39. #define EP_INTR_SRC_MASKED_REG 0x38
  40. #define CORE_INTR_SRC_REG 0x40
  41. #define CORE_INTR_SRC_SET_REG 0x44
  42. #define CORE_INTR_SRC_CLEAR_REG 0x48
  43. #define CORE_INTR_MASK_REG 0x4c
  44. #define CORE_INTR_MASK_SET_REG 0x50
  45. #define CORE_INTR_MASK_CLEAR_REG 0x54
  46. #define CORE_INTR_SRC_MASKED_REG 0x58
  47. /* 0x5c Reserved */
  48. #define USB_END_OF_INTR_REG 0x60
  49. /* Control register bits */
  50. #define AM35X_SOFT_RESET_MASK 1
  51. /* USB interrupt register bits */
  52. #define AM35X_INTR_USB_SHIFT 16
  53. #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
  54. #define AM35X_INTR_DRVVBUS 0x100
  55. #define AM35X_INTR_RX_SHIFT 16
  56. #define AM35X_INTR_TX_SHIFT 0
  57. #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
  58. #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
  59. #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  60. #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  61. #define USB_MENTOR_CORE_OFFSET 0x400
  62. struct am35x_glue {
  63. struct device *dev;
  64. struct platform_device *musb;
  65. struct platform_device *phy;
  66. struct clk *phy_clk;
  67. struct clk *clk;
  68. };
  69. /*
  70. * am35x_musb_enable - enable interrupts
  71. */
  72. static void am35x_musb_enable(struct musb *musb)
  73. {
  74. void __iomem *reg_base = musb->ctrl_base;
  75. u32 epmask;
  76. /* Workaround: setup IRQs through both register sets. */
  77. epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
  78. ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
  79. musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
  80. musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
  81. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  82. musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
  83. AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
  84. }
  85. /*
  86. * am35x_musb_disable - disable HDRC and flush interrupts
  87. */
  88. static void am35x_musb_disable(struct musb *musb)
  89. {
  90. void __iomem *reg_base = musb->ctrl_base;
  91. musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
  92. musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
  93. AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
  94. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  95. }
  96. #define portstate(stmt) stmt
  97. static void am35x_musb_set_vbus(struct musb *musb, int is_on)
  98. {
  99. WARN_ON(is_on && is_peripheral_active(musb));
  100. }
  101. #define POLL_SECONDS 2
  102. static void otg_timer(struct timer_list *t)
  103. {
  104. struct musb *musb = from_timer(musb, t, dev_timer);
  105. void __iomem *mregs = musb->mregs;
  106. u8 devctl;
  107. unsigned long flags;
  108. /*
  109. * We poll because AM35x's won't expose several OTG-critical
  110. * status change events (from the transceiver) otherwise.
  111. */
  112. devctl = musb_readb(mregs, MUSB_DEVCTL);
  113. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  114. usb_otg_state_string(musb->xceiv->otg->state));
  115. spin_lock_irqsave(&musb->lock, flags);
  116. switch (musb->xceiv->otg->state) {
  117. case OTG_STATE_A_WAIT_BCON:
  118. devctl &= ~MUSB_DEVCTL_SESSION;
  119. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  120. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  121. if (devctl & MUSB_DEVCTL_BDEVICE) {
  122. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  123. MUSB_DEV_MODE(musb);
  124. } else {
  125. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  126. MUSB_HST_MODE(musb);
  127. }
  128. break;
  129. case OTG_STATE_A_WAIT_VFALL:
  130. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  131. musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
  132. MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
  133. break;
  134. case OTG_STATE_B_IDLE:
  135. devctl = musb_readb(mregs, MUSB_DEVCTL);
  136. if (devctl & MUSB_DEVCTL_BDEVICE)
  137. mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
  138. else
  139. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  140. break;
  141. default:
  142. break;
  143. }
  144. spin_unlock_irqrestore(&musb->lock, flags);
  145. }
  146. static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
  147. {
  148. static unsigned long last_timer;
  149. if (timeout == 0)
  150. timeout = jiffies + msecs_to_jiffies(3);
  151. /* Never idle if active, or when VBUS timeout is not set as host */
  152. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  153. musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
  154. dev_dbg(musb->controller, "%s active, deleting timer\n",
  155. usb_otg_state_string(musb->xceiv->otg->state));
  156. del_timer(&musb->dev_timer);
  157. last_timer = jiffies;
  158. return;
  159. }
  160. if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) {
  161. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
  162. return;
  163. }
  164. last_timer = timeout;
  165. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  166. usb_otg_state_string(musb->xceiv->otg->state),
  167. jiffies_to_msecs(timeout - jiffies));
  168. mod_timer(&musb->dev_timer, timeout);
  169. }
  170. static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
  171. {
  172. struct musb *musb = hci;
  173. void __iomem *reg_base = musb->ctrl_base;
  174. struct device *dev = musb->controller;
  175. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  176. struct omap_musb_board_data *data = plat->board_data;
  177. unsigned long flags;
  178. irqreturn_t ret = IRQ_NONE;
  179. u32 epintr, usbintr;
  180. spin_lock_irqsave(&musb->lock, flags);
  181. /* Get endpoint interrupts */
  182. epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
  183. if (epintr) {
  184. musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
  185. musb->int_rx =
  186. (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
  187. musb->int_tx =
  188. (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
  189. }
  190. /* Get usb core interrupts */
  191. usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
  192. if (!usbintr && !epintr)
  193. goto eoi;
  194. if (usbintr) {
  195. musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
  196. musb->int_usb =
  197. (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
  198. }
  199. /*
  200. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  201. * AM35x's missing ID change IRQ. We need an ID change IRQ to
  202. * switch appropriately between halves of the OTG state machine.
  203. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  204. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  205. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  206. */
  207. if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
  208. int drvvbus = musb_readl(reg_base, USB_STAT_REG);
  209. void __iomem *mregs = musb->mregs;
  210. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  211. int err;
  212. err = musb->int_usb & MUSB_INTR_VBUSERROR;
  213. if (err) {
  214. /*
  215. * The Mentor core doesn't debounce VBUS as needed
  216. * to cope with device connect current spikes. This
  217. * means it's not uncommon for bus-powered devices
  218. * to get VBUS errors during enumeration.
  219. *
  220. * This is a workaround, but newer RTL from Mentor
  221. * seems to allow a better one: "re"-starting sessions
  222. * without waiting for VBUS to stop registering in
  223. * devctl.
  224. */
  225. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  226. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
  227. mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
  228. WARNING("VBUS error workaround (delay coming)\n");
  229. } else if (drvvbus) {
  230. MUSB_HST_MODE(musb);
  231. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  232. portstate(musb->port1_status |= USB_PORT_STAT_POWER);
  233. del_timer(&musb->dev_timer);
  234. } else {
  235. musb->is_active = 0;
  236. MUSB_DEV_MODE(musb);
  237. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  238. portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
  239. }
  240. /* NOTE: this must complete power-on within 100 ms. */
  241. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  242. drvvbus ? "on" : "off",
  243. usb_otg_state_string(musb->xceiv->otg->state),
  244. err ? " ERROR" : "",
  245. devctl);
  246. ret = IRQ_HANDLED;
  247. }
  248. /* Drop spurious RX and TX if device is disconnected */
  249. if (musb->int_usb & MUSB_INTR_DISCONNECT) {
  250. musb->int_tx = 0;
  251. musb->int_rx = 0;
  252. }
  253. if (musb->int_tx || musb->int_rx || musb->int_usb)
  254. ret |= musb_interrupt(musb);
  255. eoi:
  256. /* EOI needs to be written for the IRQ to be re-asserted. */
  257. if (ret == IRQ_HANDLED || epintr || usbintr) {
  258. /* clear level interrupt */
  259. if (data->clear_irq)
  260. data->clear_irq();
  261. /* write EOI */
  262. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  263. }
  264. /* Poll for ID change */
  265. if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
  266. mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
  267. spin_unlock_irqrestore(&musb->lock, flags);
  268. return ret;
  269. }
  270. static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
  271. {
  272. struct device *dev = musb->controller;
  273. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  274. struct omap_musb_board_data *data = plat->board_data;
  275. int retval = 0;
  276. if (data->set_mode)
  277. data->set_mode(musb_mode);
  278. else
  279. retval = -EIO;
  280. return retval;
  281. }
  282. static int am35x_musb_init(struct musb *musb)
  283. {
  284. struct device *dev = musb->controller;
  285. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  286. struct omap_musb_board_data *data = plat->board_data;
  287. void __iomem *reg_base = musb->ctrl_base;
  288. u32 rev;
  289. musb->mregs += USB_MENTOR_CORE_OFFSET;
  290. /* Returns zero if e.g. not clocked */
  291. rev = musb_readl(reg_base, USB_REVISION_REG);
  292. if (!rev)
  293. return -ENODEV;
  294. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  295. if (IS_ERR_OR_NULL(musb->xceiv))
  296. return -EPROBE_DEFER;
  297. timer_setup(&musb->dev_timer, otg_timer, 0);
  298. /* Reset the musb */
  299. if (data->reset)
  300. data->reset();
  301. /* Reset the controller */
  302. musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
  303. /* Start the on-chip PHY and its PLL. */
  304. if (data->set_phy_power)
  305. data->set_phy_power(1);
  306. msleep(5);
  307. musb->isr = am35x_musb_interrupt;
  308. /* clear level interrupt */
  309. if (data->clear_irq)
  310. data->clear_irq();
  311. return 0;
  312. }
  313. static int am35x_musb_exit(struct musb *musb)
  314. {
  315. struct device *dev = musb->controller;
  316. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  317. struct omap_musb_board_data *data = plat->board_data;
  318. del_timer_sync(&musb->dev_timer);
  319. /* Shutdown the on-chip PHY and its PLL. */
  320. if (data->set_phy_power)
  321. data->set_phy_power(0);
  322. usb_put_phy(musb->xceiv);
  323. return 0;
  324. }
  325. /* AM35x supports only 32bit read operation */
  326. static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  327. {
  328. void __iomem *fifo = hw_ep->fifo;
  329. u32 val;
  330. int i;
  331. /* Read for 32bit-aligned destination address */
  332. if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
  333. readsl(fifo, dst, len >> 2);
  334. dst += len & ~0x03;
  335. len &= 0x03;
  336. }
  337. /*
  338. * Now read the remaining 1 to 3 byte or complete length if
  339. * unaligned address.
  340. */
  341. if (len > 4) {
  342. for (i = 0; i < (len >> 2); i++) {
  343. *(u32 *) dst = musb_readl(fifo, 0);
  344. dst += 4;
  345. }
  346. len &= 0x03;
  347. }
  348. if (len > 0) {
  349. val = musb_readl(fifo, 0);
  350. memcpy(dst, &val, len);
  351. }
  352. }
  353. static const struct musb_platform_ops am35x_ops = {
  354. .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
  355. .init = am35x_musb_init,
  356. .exit = am35x_musb_exit,
  357. .read_fifo = am35x_read_fifo,
  358. #ifdef CONFIG_USB_INVENTRA_DMA
  359. .dma_init = musbhs_dma_controller_create,
  360. .dma_exit = musbhs_dma_controller_destroy,
  361. #endif
  362. .enable = am35x_musb_enable,
  363. .disable = am35x_musb_disable,
  364. .set_mode = am35x_musb_set_mode,
  365. .try_idle = am35x_musb_try_idle,
  366. .set_vbus = am35x_musb_set_vbus,
  367. };
  368. static const struct platform_device_info am35x_dev_info = {
  369. .name = "musb-hdrc",
  370. .id = PLATFORM_DEVID_AUTO,
  371. .dma_mask = DMA_BIT_MASK(32),
  372. };
  373. static int am35x_probe(struct platform_device *pdev)
  374. {
  375. struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  376. struct platform_device *musb;
  377. struct am35x_glue *glue;
  378. struct platform_device_info pinfo;
  379. struct clk *phy_clk;
  380. struct clk *clk;
  381. int ret = -ENOMEM;
  382. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  383. if (!glue)
  384. goto err0;
  385. phy_clk = clk_get(&pdev->dev, "fck");
  386. if (IS_ERR(phy_clk)) {
  387. dev_err(&pdev->dev, "failed to get PHY clock\n");
  388. ret = PTR_ERR(phy_clk);
  389. goto err3;
  390. }
  391. clk = clk_get(&pdev->dev, "ick");
  392. if (IS_ERR(clk)) {
  393. dev_err(&pdev->dev, "failed to get clock\n");
  394. ret = PTR_ERR(clk);
  395. goto err4;
  396. }
  397. ret = clk_enable(phy_clk);
  398. if (ret) {
  399. dev_err(&pdev->dev, "failed to enable PHY clock\n");
  400. goto err5;
  401. }
  402. ret = clk_enable(clk);
  403. if (ret) {
  404. dev_err(&pdev->dev, "failed to enable clock\n");
  405. goto err6;
  406. }
  407. glue->dev = &pdev->dev;
  408. glue->phy_clk = phy_clk;
  409. glue->clk = clk;
  410. pdata->platform_ops = &am35x_ops;
  411. glue->phy = usb_phy_generic_register();
  412. if (IS_ERR(glue->phy)) {
  413. ret = PTR_ERR(glue->phy);
  414. goto err7;
  415. }
  416. platform_set_drvdata(pdev, glue);
  417. pinfo = am35x_dev_info;
  418. pinfo.parent = &pdev->dev;
  419. pinfo.res = pdev->resource;
  420. pinfo.num_res = pdev->num_resources;
  421. pinfo.data = pdata;
  422. pinfo.size_data = sizeof(*pdata);
  423. glue->musb = musb = platform_device_register_full(&pinfo);
  424. if (IS_ERR(musb)) {
  425. ret = PTR_ERR(musb);
  426. dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
  427. goto err8;
  428. }
  429. return 0;
  430. err8:
  431. usb_phy_generic_unregister(glue->phy);
  432. err7:
  433. clk_disable(clk);
  434. err6:
  435. clk_disable(phy_clk);
  436. err5:
  437. clk_put(clk);
  438. err4:
  439. clk_put(phy_clk);
  440. err3:
  441. kfree(glue);
  442. err0:
  443. return ret;
  444. }
  445. static int am35x_remove(struct platform_device *pdev)
  446. {
  447. struct am35x_glue *glue = platform_get_drvdata(pdev);
  448. platform_device_unregister(glue->musb);
  449. usb_phy_generic_unregister(glue->phy);
  450. clk_disable(glue->clk);
  451. clk_disable(glue->phy_clk);
  452. clk_put(glue->clk);
  453. clk_put(glue->phy_clk);
  454. kfree(glue);
  455. return 0;
  456. }
  457. #ifdef CONFIG_PM_SLEEP
  458. static int am35x_suspend(struct device *dev)
  459. {
  460. struct am35x_glue *glue = dev_get_drvdata(dev);
  461. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  462. struct omap_musb_board_data *data = plat->board_data;
  463. /* Shutdown the on-chip PHY and its PLL. */
  464. if (data->set_phy_power)
  465. data->set_phy_power(0);
  466. clk_disable(glue->phy_clk);
  467. clk_disable(glue->clk);
  468. return 0;
  469. }
  470. static int am35x_resume(struct device *dev)
  471. {
  472. struct am35x_glue *glue = dev_get_drvdata(dev);
  473. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  474. struct omap_musb_board_data *data = plat->board_data;
  475. int ret;
  476. /* Start the on-chip PHY and its PLL. */
  477. if (data->set_phy_power)
  478. data->set_phy_power(1);
  479. ret = clk_enable(glue->phy_clk);
  480. if (ret) {
  481. dev_err(dev, "failed to enable PHY clock\n");
  482. return ret;
  483. }
  484. ret = clk_enable(glue->clk);
  485. if (ret) {
  486. dev_err(dev, "failed to enable clock\n");
  487. return ret;
  488. }
  489. return 0;
  490. }
  491. #endif
  492. static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
  493. static struct platform_driver am35x_driver = {
  494. .probe = am35x_probe,
  495. .remove = am35x_remove,
  496. .driver = {
  497. .name = "musb-am35x",
  498. .pm = &am35x_pm_ops,
  499. },
  500. };
  501. MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
  502. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  503. MODULE_LICENSE("GPL v2");
  504. module_platform_driver(am35x_driver);