isp1760-regs.h 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Driver for the NXP ISP1760 chip
  4. *
  5. * Copyright 2014 Laurent Pinchart
  6. * Copyright 2007 Sebastian Siewior
  7. *
  8. * Contacts:
  9. * Sebastian Siewior <bigeasy@linutronix.de>
  10. * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  11. */
  12. #ifndef _ISP1760_REGS_H_
  13. #define _ISP1760_REGS_H_
  14. /* -----------------------------------------------------------------------------
  15. * Host Controller
  16. */
  17. /* EHCI capability registers */
  18. #define HC_CAPLENGTH 0x000
  19. #define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
  20. #define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
  21. #define HC_HCSPARAMS 0x004
  22. #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
  23. #define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
  24. #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
  25. #define HC_HCCPARAMS 0x008
  26. #define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
  27. #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
  28. /* EHCI operational registers */
  29. #define HC_USBCMD 0x020
  30. #define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
  31. #define CMD_RESET (1 << 1) /* reset HC not bus */
  32. #define CMD_RUN (1 << 0) /* start/stop HC */
  33. #define HC_USBSTS 0x024
  34. #define STS_PCD (1 << 2) /* port change detect */
  35. #define HC_FRINDEX 0x02c
  36. #define HC_CONFIGFLAG 0x060
  37. #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
  38. #define HC_PORTSC1 0x064
  39. #define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
  40. #define PORT_POWER (1 << 12) /* true: has power (see PPC) */
  41. #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
  42. #define PORT_RESET (1 << 8) /* reset port */
  43. #define PORT_SUSPEND (1 << 7) /* suspend port */
  44. #define PORT_RESUME (1 << 6) /* resume it */
  45. #define PORT_PE (1 << 2) /* port enable */
  46. #define PORT_CSC (1 << 1) /* connect status change */
  47. #define PORT_CONNECT (1 << 0) /* device connected */
  48. #define PORT_RWC_BITS (PORT_CSC)
  49. #define HC_ISO_PTD_DONEMAP_REG 0x130
  50. #define HC_ISO_PTD_SKIPMAP_REG 0x134
  51. #define HC_ISO_PTD_LASTPTD_REG 0x138
  52. #define HC_INT_PTD_DONEMAP_REG 0x140
  53. #define HC_INT_PTD_SKIPMAP_REG 0x144
  54. #define HC_INT_PTD_LASTPTD_REG 0x148
  55. #define HC_ATL_PTD_DONEMAP_REG 0x150
  56. #define HC_ATL_PTD_SKIPMAP_REG 0x154
  57. #define HC_ATL_PTD_LASTPTD_REG 0x158
  58. /* Configuration Register */
  59. #define HC_HW_MODE_CTRL 0x300
  60. #define ALL_ATX_RESET (1 << 31)
  61. #define HW_ANA_DIGI_OC (1 << 15)
  62. #define HW_DEV_DMA (1 << 11)
  63. #define HW_COMN_IRQ (1 << 10)
  64. #define HW_COMN_DMA (1 << 9)
  65. #define HW_DATA_BUS_32BIT (1 << 8)
  66. #define HW_DACK_POL_HIGH (1 << 6)
  67. #define HW_DREQ_POL_HIGH (1 << 5)
  68. #define HW_INTR_HIGH_ACT (1 << 2)
  69. #define HW_INTR_EDGE_TRIG (1 << 1)
  70. #define HW_GLOBAL_INTR_EN (1 << 0)
  71. #define HC_CHIP_ID_REG 0x304
  72. #define HC_SCRATCH_REG 0x308
  73. #define HC_RESET_REG 0x30c
  74. #define SW_RESET_RESET_HC (1 << 1)
  75. #define SW_RESET_RESET_ALL (1 << 0)
  76. #define HC_BUFFER_STATUS_REG 0x334
  77. #define ISO_BUF_FILL (1 << 2)
  78. #define INT_BUF_FILL (1 << 1)
  79. #define ATL_BUF_FILL (1 << 0)
  80. #define HC_MEMORY_REG 0x33c
  81. #define ISP_BANK(x) ((x) << 16)
  82. #define HC_PORT1_CTRL 0x374
  83. #define PORT1_POWER (3 << 3)
  84. #define PORT1_INIT1 (1 << 7)
  85. #define PORT1_INIT2 (1 << 23)
  86. #define HW_OTG_CTRL_SET 0x374
  87. #define HW_OTG_CTRL_CLR 0x376
  88. #define HW_OTG_DISABLE (1 << 10)
  89. #define HW_OTG_SE0_EN (1 << 9)
  90. #define HW_BDIS_ACON_EN (1 << 8)
  91. #define HW_SW_SEL_HC_DC (1 << 7)
  92. #define HW_VBUS_CHRG (1 << 6)
  93. #define HW_VBUS_DISCHRG (1 << 5)
  94. #define HW_VBUS_DRV (1 << 4)
  95. #define HW_SEL_CP_EXT (1 << 3)
  96. #define HW_DM_PULLDOWN (1 << 2)
  97. #define HW_DP_PULLDOWN (1 << 1)
  98. #define HW_DP_PULLUP (1 << 0)
  99. /* Interrupt Register */
  100. #define HC_INTERRUPT_REG 0x310
  101. #define HC_INTERRUPT_ENABLE 0x314
  102. #define HC_ISO_INT (1 << 9)
  103. #define HC_ATL_INT (1 << 8)
  104. #define HC_INTL_INT (1 << 7)
  105. #define HC_EOT_INT (1 << 3)
  106. #define HC_SOT_INT (1 << 1)
  107. #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
  108. #define HC_ISO_IRQ_MASK_OR_REG 0x318
  109. #define HC_INT_IRQ_MASK_OR_REG 0x31c
  110. #define HC_ATL_IRQ_MASK_OR_REG 0x320
  111. #define HC_ISO_IRQ_MASK_AND_REG 0x324
  112. #define HC_INT_IRQ_MASK_AND_REG 0x328
  113. #define HC_ATL_IRQ_MASK_AND_REG 0x32c
  114. /* -----------------------------------------------------------------------------
  115. * Peripheral Controller
  116. */
  117. /* Initialization Registers */
  118. #define DC_ADDRESS 0x0200
  119. #define DC_DEVEN (1 << 7)
  120. #define DC_MODE 0x020c
  121. #define DC_DMACLKON (1 << 9)
  122. #define DC_VBUSSTAT (1 << 8)
  123. #define DC_CLKAON (1 << 7)
  124. #define DC_SNDRSU (1 << 6)
  125. #define DC_GOSUSP (1 << 5)
  126. #define DC_SFRESET (1 << 4)
  127. #define DC_GLINTENA (1 << 3)
  128. #define DC_WKUPCS (1 << 2)
  129. #define DC_INTCONF 0x0210
  130. #define DC_CDBGMOD_ACK_NAK (0 << 6)
  131. #define DC_CDBGMOD_ACK (1 << 6)
  132. #define DC_CDBGMOD_ACK_1NAK (2 << 6)
  133. #define DC_DDBGMODIN_ACK_NAK (0 << 4)
  134. #define DC_DDBGMODIN_ACK (1 << 4)
  135. #define DC_DDBGMODIN_ACK_1NAK (2 << 4)
  136. #define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2)
  137. #define DC_DDBGMODOUT_ACK_NYET (1 << 2)
  138. #define DC_DDBGMODOUT_ACK_NYET_1NAK (2 << 2)
  139. #define DC_INTLVL (1 << 1)
  140. #define DC_INTPOL (1 << 0)
  141. #define DC_DEBUG 0x0212
  142. #define DC_INTENABLE 0x0214
  143. #define DC_IEPTX(n) (1 << (11 + 2 * (n)))
  144. #define DC_IEPRX(n) (1 << (10 + 2 * (n)))
  145. #define DC_IEPRXTX(n) (3 << (10 + 2 * (n)))
  146. #define DC_IEP0SETUP (1 << 8)
  147. #define DC_IEVBUS (1 << 7)
  148. #define DC_IEDMA (1 << 6)
  149. #define DC_IEHS_STA (1 << 5)
  150. #define DC_IERESM (1 << 4)
  151. #define DC_IESUSP (1 << 3)
  152. #define DC_IEPSOF (1 << 2)
  153. #define DC_IESOF (1 << 1)
  154. #define DC_IEBRST (1 << 0)
  155. /* Data Flow Registers */
  156. #define DC_EPINDEX 0x022c
  157. #define DC_EP0SETUP (1 << 5)
  158. #define DC_ENDPIDX(n) ((n) << 1)
  159. #define DC_EPDIR (1 << 0)
  160. #define DC_CTRLFUNC 0x0228
  161. #define DC_CLBUF (1 << 4)
  162. #define DC_VENDP (1 << 3)
  163. #define DC_DSEN (1 << 2)
  164. #define DC_STATUS (1 << 1)
  165. #define DC_STALL (1 << 0)
  166. #define DC_DATAPORT 0x0220
  167. #define DC_BUFLEN 0x021c
  168. #define DC_DATACOUNT_MASK 0xffff
  169. #define DC_BUFSTAT 0x021e
  170. #define DC_EPMAXPKTSZ 0x0204
  171. #define DC_EPTYPE 0x0208
  172. #define DC_NOEMPKT (1 << 4)
  173. #define DC_EPENABLE (1 << 3)
  174. #define DC_DBLBUF (1 << 2)
  175. #define DC_ENDPTYP_ISOC (1 << 0)
  176. #define DC_ENDPTYP_BULK (2 << 0)
  177. #define DC_ENDPTYP_INTERRUPT (3 << 0)
  178. /* DMA Registers */
  179. #define DC_DMACMD 0x0230
  180. #define DC_DMATXCOUNT 0x0234
  181. #define DC_DMACONF 0x0238
  182. #define DC_DMAHW 0x023c
  183. #define DC_DMAINTREASON 0x0250
  184. #define DC_DMAINTEN 0x0254
  185. #define DC_DMAEP 0x0258
  186. #define DC_DMABURSTCOUNT 0x0264
  187. /* General Registers */
  188. #define DC_INTERRUPT 0x0218
  189. #define DC_CHIPID 0x0270
  190. #define DC_FRAMENUM 0x0274
  191. #define DC_SCRATCH 0x0278
  192. #define DC_UNLOCKDEV 0x027c
  193. #define DC_INTPULSEWIDTH 0x0280
  194. #define DC_TESTMODE 0x0284
  195. #endif