xhci-pci.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xHCI host controller driver PCI Bus Glue.
  4. *
  5. * Copyright (C) 2008 Intel Corp.
  6. *
  7. * Author: Sarah Sharp
  8. * Some code borrowed from the Linux EHCI driver.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/acpi.h>
  14. #include <linux/reset.h>
  15. #include "xhci.h"
  16. #include "xhci-trace.h"
  17. #include "xhci-pci.h"
  18. #define SSIC_PORT_NUM 2
  19. #define SSIC_PORT_CFG2 0x880c
  20. #define SSIC_PORT_CFG2_OFFSET 0x30
  21. #define PROG_DONE (1 << 30)
  22. #define SSIC_PORT_UNUSED (1 << 31)
  23. #define SPARSE_DISABLE_BIT 17
  24. #define SPARSE_CNTL_ENABLE 0xC12C
  25. /* Device for a quirk */
  26. #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
  27. #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
  28. #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
  29. #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
  30. #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
  31. #define PCI_VENDOR_ID_ETRON 0x1b6f
  32. #define PCI_DEVICE_ID_EJ168 0x7023
  33. #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
  34. #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
  35. #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
  36. #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
  37. #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
  38. #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
  39. #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
  40. #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
  41. #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
  42. #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
  43. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
  44. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
  45. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
  46. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
  47. #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
  48. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
  49. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
  50. #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
  51. #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
  52. #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
  53. #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
  54. #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
  55. #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
  56. #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
  57. #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
  58. #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
  59. #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
  60. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a
  61. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b
  62. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d
  63. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e
  64. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6
  65. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7
  66. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c
  67. #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f
  68. #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
  69. #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
  70. #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
  71. #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
  72. #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
  73. static const char hcd_name[] = "xhci_hcd";
  74. static struct hc_driver __read_mostly xhci_pci_hc_driver;
  75. static int xhci_pci_setup(struct usb_hcd *hcd);
  76. static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  77. .reset = xhci_pci_setup,
  78. };
  79. /* called after powerup, by probe or system-pm "wakeup" */
  80. static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  81. {
  82. /*
  83. * TODO: Implement finding debug ports later.
  84. * TODO: see if there are any quirks that need to be added to handle
  85. * new extended capabilities.
  86. */
  87. /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  88. if (!pci_set_mwi(pdev))
  89. xhci_dbg(xhci, "MWI active\n");
  90. xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  91. return 0;
  92. }
  93. static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  94. {
  95. struct pci_dev *pdev = to_pci_dev(dev);
  96. struct xhci_driver_data *driver_data;
  97. const struct pci_device_id *id;
  98. id = pci_match_id(pdev->driver->id_table, pdev);
  99. if (id && id->driver_data) {
  100. driver_data = (struct xhci_driver_data *)id->driver_data;
  101. xhci->quirks |= driver_data->quirks;
  102. }
  103. /* Look for vendor-specific quirks */
  104. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  105. (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  106. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  107. if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  108. pdev->revision == 0x0) {
  109. xhci->quirks |= XHCI_RESET_EP_QUIRK;
  110. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  111. "QUIRK: Fresco Logic xHC needs configure"
  112. " endpoint cmd after reset endpoint");
  113. }
  114. if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  115. pdev->revision == 0x4) {
  116. xhci->quirks |= XHCI_SLOW_SUSPEND;
  117. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  118. "QUIRK: Fresco Logic xHC revision %u"
  119. "must be suspended extra slowly",
  120. pdev->revision);
  121. }
  122. if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
  123. xhci->quirks |= XHCI_BROKEN_STREAMS;
  124. /* Fresco Logic confirms: all revisions of this chip do not
  125. * support MSI, even though some of them claim to in their PCI
  126. * capabilities.
  127. */
  128. xhci->quirks |= XHCI_BROKEN_MSI;
  129. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  130. "QUIRK: Fresco Logic revision %u "
  131. "has broken MSI implementation",
  132. pdev->revision);
  133. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  134. }
  135. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  136. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
  137. xhci->quirks |= XHCI_BROKEN_STREAMS;
  138. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  139. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
  140. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  141. if (pdev->vendor == PCI_VENDOR_ID_NEC)
  142. xhci->quirks |= XHCI_NEC_HOST;
  143. if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
  144. xhci->quirks |= XHCI_AMD_0x96_HOST;
  145. /* AMD PLL quirk */
  146. if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
  147. xhci->quirks |= XHCI_AMD_PLL_FIX;
  148. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  149. (pdev->device == 0x145c ||
  150. pdev->device == 0x15e0 ||
  151. pdev->device == 0x15e1 ||
  152. pdev->device == 0x43bb))
  153. xhci->quirks |= XHCI_SUSPEND_DELAY;
  154. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  155. (pdev->device == 0x15e0 || pdev->device == 0x15e1))
  156. xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
  157. if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
  158. xhci->quirks |= XHCI_DISABLE_SPARSE;
  159. xhci->quirks |= XHCI_RESET_ON_RESUME;
  160. }
  161. if (pdev->vendor == PCI_VENDOR_ID_AMD)
  162. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  163. if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
  164. ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
  165. (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
  166. (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
  167. (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
  168. xhci->quirks |= XHCI_U2_DISABLE_WAKE;
  169. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  170. xhci->quirks |= XHCI_LPM_SUPPORT;
  171. xhci->quirks |= XHCI_INTEL_HOST;
  172. xhci->quirks |= XHCI_AVOID_BEI;
  173. }
  174. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  175. pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
  176. xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
  177. xhci->limit_active_eps = 64;
  178. xhci->quirks |= XHCI_SW_BW_CHECKING;
  179. /*
  180. * PPT desktop boards DH77EB and DH77DF will power back on after
  181. * a few seconds of being shutdown. The fix for this is to
  182. * switch the ports from xHCI to EHCI on shutdown. We can't use
  183. * DMI information to find those particular boards (since each
  184. * vendor will change the board name), so we have to key off all
  185. * PPT chipsets.
  186. */
  187. xhci->quirks |= XHCI_SPURIOUS_REBOOT;
  188. }
  189. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  190. (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
  191. pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
  192. xhci->quirks |= XHCI_SPURIOUS_REBOOT;
  193. xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
  194. }
  195. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  196. (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
  197. pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
  198. pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
  199. pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
  200. pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
  201. pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
  202. pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
  203. pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
  204. xhci->quirks |= XHCI_PME_STUCK_QUIRK;
  205. }
  206. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  207. pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
  208. xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
  209. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  210. (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
  211. pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
  212. pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
  213. xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
  214. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  215. (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
  216. pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
  217. pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
  218. pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
  219. pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
  220. xhci->quirks |= XHCI_MISSING_CAS;
  221. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  222. (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
  223. pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
  224. pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
  225. pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
  226. pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
  227. pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
  228. pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
  229. pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
  230. pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
  231. pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
  232. pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
  233. pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
  234. xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
  235. if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
  236. pdev->device == PCI_DEVICE_ID_EJ168) {
  237. xhci->quirks |= XHCI_RESET_ON_RESUME;
  238. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  239. xhci->quirks |= XHCI_BROKEN_STREAMS;
  240. }
  241. if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
  242. pdev->device == 0x0014) {
  243. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  244. xhci->quirks |= XHCI_ZERO_64B_REGS;
  245. }
  246. if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
  247. pdev->device == 0x0015) {
  248. xhci->quirks |= XHCI_RESET_ON_RESUME;
  249. xhci->quirks |= XHCI_ZERO_64B_REGS;
  250. }
  251. if (pdev->vendor == PCI_VENDOR_ID_VIA)
  252. xhci->quirks |= XHCI_RESET_ON_RESUME;
  253. /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
  254. if (pdev->vendor == PCI_VENDOR_ID_VIA &&
  255. pdev->device == 0x3432)
  256. xhci->quirks |= XHCI_BROKEN_STREAMS;
  257. if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
  258. xhci->quirks |= XHCI_LPM_SUPPORT;
  259. xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
  260. }
  261. if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
  262. pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
  263. xhci->quirks |= XHCI_BROKEN_STREAMS;
  264. if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
  265. pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
  266. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  267. xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
  268. }
  269. if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
  270. (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
  271. pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
  272. pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
  273. xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
  274. if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
  275. pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
  276. xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
  277. if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
  278. xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
  279. if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
  280. pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
  281. pdev->device == 0x9026)
  282. xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
  283. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  284. (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
  285. pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
  286. xhci->quirks |= XHCI_NO_SOFT_RETRY;
  287. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  288. (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
  289. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
  290. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
  291. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
  292. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
  293. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
  294. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
  295. pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
  296. xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
  297. if (xhci->quirks & XHCI_RESET_ON_RESUME)
  298. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  299. "QUIRK: Resetting on resume");
  300. }
  301. #ifdef CONFIG_ACPI
  302. static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
  303. {
  304. static const guid_t intel_dsm_guid =
  305. GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
  306. 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
  307. union acpi_object *obj;
  308. obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
  309. NULL);
  310. ACPI_FREE(obj);
  311. }
  312. #else
  313. static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
  314. #endif /* CONFIG_ACPI */
  315. /* called during probe() after chip reset completes */
  316. static int xhci_pci_setup(struct usb_hcd *hcd)
  317. {
  318. struct xhci_hcd *xhci;
  319. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  320. int retval;
  321. xhci = hcd_to_xhci(hcd);
  322. if (!xhci->sbrn)
  323. pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
  324. /* imod_interval is the interrupt moderation value in nanoseconds. */
  325. xhci->imod_interval = 40000;
  326. retval = xhci_gen_setup(hcd, xhci_pci_quirks);
  327. if (retval)
  328. return retval;
  329. if (!usb_hcd_is_primary_hcd(hcd))
  330. return 0;
  331. if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
  332. xhci_pme_acpi_rtd3_enable(pdev);
  333. xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
  334. /* Find any debug ports */
  335. return xhci_pci_reinit(xhci, pdev);
  336. }
  337. /*
  338. * We need to register our own PCI probe function (instead of the USB core's
  339. * function) in order to create a second roothub under xHCI.
  340. */
  341. static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  342. {
  343. int retval;
  344. struct xhci_hcd *xhci;
  345. struct usb_hcd *hcd;
  346. struct xhci_driver_data *driver_data;
  347. struct reset_control *reset;
  348. driver_data = (struct xhci_driver_data *)id->driver_data;
  349. if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
  350. retval = renesas_xhci_check_request_fw(dev, id);
  351. if (retval)
  352. return retval;
  353. }
  354. reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
  355. if (IS_ERR(reset))
  356. return PTR_ERR(reset);
  357. reset_control_reset(reset);
  358. /* Prevent runtime suspending between USB-2 and USB-3 initialization */
  359. pm_runtime_get_noresume(&dev->dev);
  360. /* Register the USB 2.0 roothub.
  361. * FIXME: USB core must know to register the USB 2.0 roothub first.
  362. * This is sort of silly, because we could just set the HCD driver flags
  363. * to say USB 2.0, but I'm not sure what the implications would be in
  364. * the other parts of the HCD code.
  365. */
  366. retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
  367. if (retval)
  368. goto put_runtime_pm;
  369. /* USB 2.0 roothub is stored in the PCI device now. */
  370. hcd = dev_get_drvdata(&dev->dev);
  371. xhci = hcd_to_xhci(hcd);
  372. xhci->reset = reset;
  373. xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
  374. pci_name(dev), hcd);
  375. if (!xhci->shared_hcd) {
  376. retval = -ENOMEM;
  377. goto dealloc_usb2_hcd;
  378. }
  379. retval = xhci_ext_cap_init(xhci);
  380. if (retval)
  381. goto put_usb3_hcd;
  382. retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
  383. IRQF_SHARED);
  384. if (retval)
  385. goto put_usb3_hcd;
  386. /* Roothub already marked as USB 3.0 speed */
  387. if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
  388. HCC_MAX_PSA(xhci->hcc_params) >= 4)
  389. xhci->shared_hcd->can_do_streams = 1;
  390. /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
  391. pm_runtime_put_noidle(&dev->dev);
  392. if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
  393. pm_runtime_allow(&dev->dev);
  394. return 0;
  395. put_usb3_hcd:
  396. usb_put_hcd(xhci->shared_hcd);
  397. dealloc_usb2_hcd:
  398. usb_hcd_pci_remove(dev);
  399. put_runtime_pm:
  400. pm_runtime_put_noidle(&dev->dev);
  401. return retval;
  402. }
  403. static void xhci_pci_remove(struct pci_dev *dev)
  404. {
  405. struct xhci_hcd *xhci;
  406. xhci = hcd_to_xhci(pci_get_drvdata(dev));
  407. if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
  408. renesas_xhci_pci_exit(dev);
  409. xhci->xhc_state |= XHCI_STATE_REMOVING;
  410. if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
  411. pm_runtime_forbid(&dev->dev);
  412. if (xhci->shared_hcd) {
  413. usb_remove_hcd(xhci->shared_hcd);
  414. usb_put_hcd(xhci->shared_hcd);
  415. xhci->shared_hcd = NULL;
  416. }
  417. /* Workaround for spurious wakeups at shutdown with HSW */
  418. if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
  419. pci_set_power_state(dev, PCI_D3hot);
  420. usb_hcd_pci_remove(dev);
  421. }
  422. #ifdef CONFIG_PM
  423. /*
  424. * In some Intel xHCI controllers, in order to get D3 working,
  425. * through a vendor specific SSIC CONFIG register at offset 0x883c,
  426. * SSIC PORT need to be marked as "unused" before putting xHCI
  427. * into D3. After D3 exit, the SSIC port need to be marked as "used".
  428. * Without this change, xHCI might not enter D3 state.
  429. */
  430. static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
  431. {
  432. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  433. u32 val;
  434. void __iomem *reg;
  435. int i;
  436. for (i = 0; i < SSIC_PORT_NUM; i++) {
  437. reg = (void __iomem *) xhci->cap_regs +
  438. SSIC_PORT_CFG2 +
  439. i * SSIC_PORT_CFG2_OFFSET;
  440. /* Notify SSIC that SSIC profile programming is not done. */
  441. val = readl(reg) & ~PROG_DONE;
  442. writel(val, reg);
  443. /* Mark SSIC port as unused(suspend) or used(resume) */
  444. val = readl(reg);
  445. if (suspend)
  446. val |= SSIC_PORT_UNUSED;
  447. else
  448. val &= ~SSIC_PORT_UNUSED;
  449. writel(val, reg);
  450. /* Notify SSIC that SSIC profile programming is done */
  451. val = readl(reg) | PROG_DONE;
  452. writel(val, reg);
  453. readl(reg);
  454. }
  455. }
  456. /*
  457. * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
  458. * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
  459. */
  460. static void xhci_pme_quirk(struct usb_hcd *hcd)
  461. {
  462. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  463. void __iomem *reg;
  464. u32 val;
  465. reg = (void __iomem *) xhci->cap_regs + 0x80a4;
  466. val = readl(reg);
  467. writel(val | BIT(28), reg);
  468. readl(reg);
  469. }
  470. static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
  471. {
  472. u32 reg;
  473. reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
  474. reg &= ~BIT(SPARSE_DISABLE_BIT);
  475. writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
  476. }
  477. static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  478. {
  479. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  480. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  481. int ret;
  482. /*
  483. * Systems with the TI redriver that loses port status change events
  484. * need to have the registers polled during D3, so avoid D3cold.
  485. */
  486. if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
  487. pci_d3cold_disable(pdev);
  488. if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
  489. xhci_pme_quirk(hcd);
  490. if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
  491. xhci_ssic_port_unused_quirk(hcd, true);
  492. if (xhci->quirks & XHCI_DISABLE_SPARSE)
  493. xhci_sparse_control_quirk(hcd);
  494. ret = xhci_suspend(xhci, do_wakeup);
  495. if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
  496. xhci_ssic_port_unused_quirk(hcd, false);
  497. return ret;
  498. }
  499. static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  500. {
  501. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  502. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  503. int retval = 0;
  504. reset_control_reset(xhci->reset);
  505. /* The BIOS on systems with the Intel Panther Point chipset may or may
  506. * not support xHCI natively. That means that during system resume, it
  507. * may switch the ports back to EHCI so that users can use their
  508. * keyboard to select a kernel from GRUB after resume from hibernate.
  509. *
  510. * The BIOS is supposed to remember whether the OS had xHCI ports
  511. * enabled before resume, and switch the ports back to xHCI when the
  512. * BIOS/OS semaphore is written, but we all know we can't trust BIOS
  513. * writers.
  514. *
  515. * Unconditionally switch the ports back to xHCI after a system resume.
  516. * It should not matter whether the EHCI or xHCI controller is
  517. * resumed first. It's enough to do the switchover in xHCI because
  518. * USB core won't notice anything as the hub driver doesn't start
  519. * running again until after all the devices (including both EHCI and
  520. * xHCI host controllers) have been resumed.
  521. */
  522. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  523. usb_enable_intel_xhci_ports(pdev);
  524. if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
  525. xhci_ssic_port_unused_quirk(hcd, false);
  526. if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
  527. xhci_pme_quirk(hcd);
  528. retval = xhci_resume(xhci, hibernated);
  529. return retval;
  530. }
  531. static void xhci_pci_shutdown(struct usb_hcd *hcd)
  532. {
  533. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  534. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  535. xhci_shutdown(hcd);
  536. /* Yet another workaround for spurious wakeups at shutdown with HSW */
  537. if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
  538. pci_set_power_state(pdev, PCI_D3hot);
  539. }
  540. #endif /* CONFIG_PM */
  541. /*-------------------------------------------------------------------------*/
  542. static const struct xhci_driver_data reneses_data = {
  543. .quirks = XHCI_RENESAS_FW_QUIRK,
  544. .firmware = "renesas_usb_fw.mem",
  545. };
  546. /* PCI driver selection metadata; PCI hotplugging uses this */
  547. static const struct pci_device_id pci_ids[] = {
  548. { PCI_DEVICE(0x1912, 0x0014),
  549. .driver_data = (unsigned long)&reneses_data,
  550. },
  551. { PCI_DEVICE(0x1912, 0x0015),
  552. .driver_data = (unsigned long)&reneses_data,
  553. },
  554. /* handle any USB 3.0 xHCI controller */
  555. { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
  556. },
  557. { /* end: all zeroes */ }
  558. };
  559. MODULE_DEVICE_TABLE(pci, pci_ids);
  560. /*
  561. * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
  562. * load firmware, so don't encumber the xhci-pci driver with it.
  563. */
  564. #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
  565. MODULE_FIRMWARE("renesas_usb_fw.mem");
  566. #endif
  567. /* pci driver glue; this is a "new style" PCI driver module */
  568. static struct pci_driver xhci_pci_driver = {
  569. .name = hcd_name,
  570. .id_table = pci_ids,
  571. .probe = xhci_pci_probe,
  572. .remove = xhci_pci_remove,
  573. /* suspend and resume implemented later */
  574. .shutdown = usb_hcd_pci_shutdown,
  575. #ifdef CONFIG_PM
  576. .driver = {
  577. .pm = &usb_hcd_pci_pm_ops
  578. },
  579. #endif
  580. };
  581. static int __init xhci_pci_init(void)
  582. {
  583. xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
  584. #ifdef CONFIG_PM
  585. xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
  586. xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
  587. xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
  588. #endif
  589. return pci_register_driver(&xhci_pci_driver);
  590. }
  591. module_init(xhci_pci_init);
  592. static void __exit xhci_pci_exit(void)
  593. {
  594. pci_unregister_driver(&xhci_pci_driver);
  595. }
  596. module_exit(xhci_pci_exit);
  597. MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
  598. MODULE_LICENSE("GPL");