xhci-dbgcap.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xhci-dbgcap.c - xHCI debug capability support
  4. *
  5. * Copyright (C) 2017 Intel Corporation
  6. *
  7. * Author: Lu Baolu <baolu.lu@linux.intel.com>
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/slab.h>
  11. #include <linux/nls.h>
  12. #include "xhci.h"
  13. #include "xhci-trace.h"
  14. #include "xhci-dbgcap.h"
  15. static void dbc_free_ctx(struct device *dev, struct xhci_container_ctx *ctx)
  16. {
  17. if (!ctx)
  18. return;
  19. dma_free_coherent(dev, ctx->size, ctx->bytes, ctx->dma);
  20. kfree(ctx);
  21. }
  22. /* we use only one segment for DbC rings */
  23. static void dbc_ring_free(struct device *dev, struct xhci_ring *ring)
  24. {
  25. if (!ring)
  26. return;
  27. if (ring->first_seg && ring->first_seg->trbs) {
  28. dma_free_coherent(dev, TRB_SEGMENT_SIZE,
  29. ring->first_seg->trbs,
  30. ring->first_seg->dma);
  31. kfree(ring->first_seg);
  32. }
  33. kfree(ring);
  34. }
  35. static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
  36. {
  37. struct usb_string_descriptor *s_desc;
  38. u32 string_length;
  39. /* Serial string: */
  40. s_desc = (struct usb_string_descriptor *)strings->serial;
  41. utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
  42. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  43. DBC_MAX_STRING_LENGTH);
  44. s_desc->bLength = (strlen(DBC_STRING_SERIAL) + 1) * 2;
  45. s_desc->bDescriptorType = USB_DT_STRING;
  46. string_length = s_desc->bLength;
  47. string_length <<= 8;
  48. /* Product string: */
  49. s_desc = (struct usb_string_descriptor *)strings->product;
  50. utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
  51. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  52. DBC_MAX_STRING_LENGTH);
  53. s_desc->bLength = (strlen(DBC_STRING_PRODUCT) + 1) * 2;
  54. s_desc->bDescriptorType = USB_DT_STRING;
  55. string_length += s_desc->bLength;
  56. string_length <<= 8;
  57. /* Manufacture string: */
  58. s_desc = (struct usb_string_descriptor *)strings->manufacturer;
  59. utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
  60. strlen(DBC_STRING_MANUFACTURER),
  61. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  62. DBC_MAX_STRING_LENGTH);
  63. s_desc->bLength = (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
  64. s_desc->bDescriptorType = USB_DT_STRING;
  65. string_length += s_desc->bLength;
  66. string_length <<= 8;
  67. /* String0: */
  68. strings->string0[0] = 4;
  69. strings->string0[1] = USB_DT_STRING;
  70. strings->string0[2] = 0x09;
  71. strings->string0[3] = 0x04;
  72. string_length += 4;
  73. return string_length;
  74. }
  75. static void xhci_dbc_init_contexts(struct xhci_dbc *dbc, u32 string_length)
  76. {
  77. struct dbc_info_context *info;
  78. struct xhci_ep_ctx *ep_ctx;
  79. u32 dev_info;
  80. dma_addr_t deq, dma;
  81. unsigned int max_burst;
  82. if (!dbc)
  83. return;
  84. /* Populate info Context: */
  85. info = (struct dbc_info_context *)dbc->ctx->bytes;
  86. dma = dbc->string_dma;
  87. info->string0 = cpu_to_le64(dma);
  88. info->manufacturer = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
  89. info->product = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
  90. info->serial = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
  91. info->length = cpu_to_le32(string_length);
  92. /* Populate bulk out endpoint context: */
  93. ep_ctx = dbc_bulkout_ctx(dbc);
  94. max_burst = DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
  95. deq = dbc_bulkout_enq(dbc);
  96. ep_ctx->ep_info = 0;
  97. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
  98. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_out->cycle_state);
  99. /* Populate bulk in endpoint context: */
  100. ep_ctx = dbc_bulkin_ctx(dbc);
  101. deq = dbc_bulkin_enq(dbc);
  102. ep_ctx->ep_info = 0;
  103. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
  104. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_in->cycle_state);
  105. /* Set DbC context and info registers: */
  106. lo_hi_writeq(dbc->ctx->dma, &dbc->regs->dccp);
  107. dev_info = cpu_to_le32((DBC_VENDOR_ID << 16) | DBC_PROTOCOL);
  108. writel(dev_info, &dbc->regs->devinfo1);
  109. dev_info = cpu_to_le32((DBC_DEVICE_REV << 16) | DBC_PRODUCT_ID);
  110. writel(dev_info, &dbc->regs->devinfo2);
  111. }
  112. static void xhci_dbc_giveback(struct dbc_request *req, int status)
  113. __releases(&dbc->lock)
  114. __acquires(&dbc->lock)
  115. {
  116. struct xhci_dbc *dbc = req->dbc;
  117. struct device *dev = dbc->dev;
  118. list_del_init(&req->list_pending);
  119. req->trb_dma = 0;
  120. req->trb = NULL;
  121. if (req->status == -EINPROGRESS)
  122. req->status = status;
  123. trace_xhci_dbc_giveback_request(req);
  124. dma_unmap_single(dev,
  125. req->dma,
  126. req->length,
  127. dbc_ep_dma_direction(req));
  128. /* Give back the transfer request: */
  129. spin_unlock(&dbc->lock);
  130. req->complete(dbc, req);
  131. spin_lock(&dbc->lock);
  132. }
  133. static void xhci_dbc_flush_single_request(struct dbc_request *req)
  134. {
  135. union xhci_trb *trb = req->trb;
  136. trb->generic.field[0] = 0;
  137. trb->generic.field[1] = 0;
  138. trb->generic.field[2] = 0;
  139. trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
  140. trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
  141. xhci_dbc_giveback(req, -ESHUTDOWN);
  142. }
  143. static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
  144. {
  145. struct dbc_request *req, *tmp;
  146. list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
  147. xhci_dbc_flush_single_request(req);
  148. }
  149. static void xhci_dbc_flush_requests(struct xhci_dbc *dbc)
  150. {
  151. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
  152. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
  153. }
  154. struct dbc_request *
  155. dbc_alloc_request(struct xhci_dbc *dbc, unsigned int direction, gfp_t flags)
  156. {
  157. struct dbc_request *req;
  158. if (direction != BULK_IN &&
  159. direction != BULK_OUT)
  160. return NULL;
  161. if (!dbc)
  162. return NULL;
  163. req = kzalloc(sizeof(*req), flags);
  164. if (!req)
  165. return NULL;
  166. req->dbc = dbc;
  167. INIT_LIST_HEAD(&req->list_pending);
  168. INIT_LIST_HEAD(&req->list_pool);
  169. req->direction = direction;
  170. trace_xhci_dbc_alloc_request(req);
  171. return req;
  172. }
  173. void
  174. dbc_free_request(struct dbc_request *req)
  175. {
  176. trace_xhci_dbc_free_request(req);
  177. kfree(req);
  178. }
  179. static void
  180. xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
  181. u32 field2, u32 field3, u32 field4)
  182. {
  183. union xhci_trb *trb, *next;
  184. trb = ring->enqueue;
  185. trb->generic.field[0] = cpu_to_le32(field1);
  186. trb->generic.field[1] = cpu_to_le32(field2);
  187. trb->generic.field[2] = cpu_to_le32(field3);
  188. trb->generic.field[3] = cpu_to_le32(field4);
  189. trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
  190. ring->num_trbs_free--;
  191. next = ++(ring->enqueue);
  192. if (TRB_TYPE_LINK_LE32(next->link.control)) {
  193. next->link.control ^= cpu_to_le32(TRB_CYCLE);
  194. ring->enqueue = ring->enq_seg->trbs;
  195. ring->cycle_state ^= 1;
  196. }
  197. }
  198. static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
  199. struct dbc_request *req)
  200. {
  201. u64 addr;
  202. union xhci_trb *trb;
  203. unsigned int num_trbs;
  204. struct xhci_dbc *dbc = req->dbc;
  205. struct xhci_ring *ring = dep->ring;
  206. u32 length, control, cycle;
  207. num_trbs = count_trbs(req->dma, req->length);
  208. WARN_ON(num_trbs != 1);
  209. if (ring->num_trbs_free < num_trbs)
  210. return -EBUSY;
  211. addr = req->dma;
  212. trb = ring->enqueue;
  213. cycle = ring->cycle_state;
  214. length = TRB_LEN(req->length);
  215. control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
  216. if (cycle)
  217. control &= cpu_to_le32(~TRB_CYCLE);
  218. else
  219. control |= cpu_to_le32(TRB_CYCLE);
  220. req->trb = ring->enqueue;
  221. req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
  222. xhci_dbc_queue_trb(ring,
  223. lower_32_bits(addr),
  224. upper_32_bits(addr),
  225. length, control);
  226. /*
  227. * Add a barrier between writes of trb fields and flipping
  228. * the cycle bit:
  229. */
  230. wmb();
  231. if (cycle)
  232. trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
  233. else
  234. trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
  235. writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
  236. return 0;
  237. }
  238. static int
  239. dbc_ep_do_queue(struct dbc_request *req)
  240. {
  241. int ret;
  242. struct xhci_dbc *dbc = req->dbc;
  243. struct device *dev = dbc->dev;
  244. struct dbc_ep *dep = &dbc->eps[req->direction];
  245. if (!req->length || !req->buf)
  246. return -EINVAL;
  247. req->actual = 0;
  248. req->status = -EINPROGRESS;
  249. req->dma = dma_map_single(dev,
  250. req->buf,
  251. req->length,
  252. dbc_ep_dma_direction(dep));
  253. if (dma_mapping_error(dev, req->dma)) {
  254. dev_err(dbc->dev, "failed to map buffer\n");
  255. return -EFAULT;
  256. }
  257. ret = xhci_dbc_queue_bulk_tx(dep, req);
  258. if (ret) {
  259. dev_err(dbc->dev, "failed to queue trbs\n");
  260. dma_unmap_single(dev,
  261. req->dma,
  262. req->length,
  263. dbc_ep_dma_direction(dep));
  264. return -EFAULT;
  265. }
  266. list_add_tail(&req->list_pending, &dep->list_pending);
  267. return 0;
  268. }
  269. int dbc_ep_queue(struct dbc_request *req)
  270. {
  271. unsigned long flags;
  272. struct xhci_dbc *dbc = req->dbc;
  273. int ret = -ESHUTDOWN;
  274. if (!dbc)
  275. return -ENODEV;
  276. if (req->direction != BULK_IN &&
  277. req->direction != BULK_OUT)
  278. return -EINVAL;
  279. spin_lock_irqsave(&dbc->lock, flags);
  280. if (dbc->state == DS_CONFIGURED)
  281. ret = dbc_ep_do_queue(req);
  282. spin_unlock_irqrestore(&dbc->lock, flags);
  283. mod_delayed_work(system_wq, &dbc->event_work, 0);
  284. trace_xhci_dbc_queue_request(req);
  285. return ret;
  286. }
  287. static inline void xhci_dbc_do_eps_init(struct xhci_dbc *dbc, bool direction)
  288. {
  289. struct dbc_ep *dep;
  290. dep = &dbc->eps[direction];
  291. dep->dbc = dbc;
  292. dep->direction = direction;
  293. dep->ring = direction ? dbc->ring_in : dbc->ring_out;
  294. INIT_LIST_HEAD(&dep->list_pending);
  295. }
  296. static void xhci_dbc_eps_init(struct xhci_dbc *dbc)
  297. {
  298. xhci_dbc_do_eps_init(dbc, BULK_OUT);
  299. xhci_dbc_do_eps_init(dbc, BULK_IN);
  300. }
  301. static void xhci_dbc_eps_exit(struct xhci_dbc *dbc)
  302. {
  303. memset(dbc->eps, 0, sizeof(struct dbc_ep) * ARRAY_SIZE(dbc->eps));
  304. }
  305. static int dbc_erst_alloc(struct device *dev, struct xhci_ring *evt_ring,
  306. struct xhci_erst *erst, gfp_t flags)
  307. {
  308. erst->entries = dma_alloc_coherent(dev, sizeof(struct xhci_erst_entry),
  309. &erst->erst_dma_addr, flags);
  310. if (!erst->entries)
  311. return -ENOMEM;
  312. erst->num_entries = 1;
  313. erst->entries[0].seg_addr = cpu_to_le64(evt_ring->first_seg->dma);
  314. erst->entries[0].seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
  315. erst->entries[0].rsvd = 0;
  316. return 0;
  317. }
  318. static void dbc_erst_free(struct device *dev, struct xhci_erst *erst)
  319. {
  320. if (erst->entries)
  321. dma_free_coherent(dev, sizeof(struct xhci_erst_entry),
  322. erst->entries, erst->erst_dma_addr);
  323. erst->entries = NULL;
  324. }
  325. static struct xhci_container_ctx *
  326. dbc_alloc_ctx(struct device *dev, gfp_t flags)
  327. {
  328. struct xhci_container_ctx *ctx;
  329. ctx = kzalloc(sizeof(*ctx), flags);
  330. if (!ctx)
  331. return NULL;
  332. /* xhci 7.6.9, all three contexts; info, ep-out and ep-in. Each 64 bytes*/
  333. ctx->size = 3 * DBC_CONTEXT_SIZE;
  334. ctx->bytes = dma_alloc_coherent(dev, ctx->size, &ctx->dma, flags);
  335. if (!ctx->bytes) {
  336. kfree(ctx);
  337. return NULL;
  338. }
  339. return ctx;
  340. }
  341. static struct xhci_ring *
  342. xhci_dbc_ring_alloc(struct device *dev, enum xhci_ring_type type, gfp_t flags)
  343. {
  344. struct xhci_ring *ring;
  345. struct xhci_segment *seg;
  346. dma_addr_t dma;
  347. ring = kzalloc(sizeof(*ring), flags);
  348. if (!ring)
  349. return NULL;
  350. ring->num_segs = 1;
  351. ring->type = type;
  352. seg = kzalloc(sizeof(*seg), flags);
  353. if (!seg)
  354. goto seg_fail;
  355. ring->first_seg = seg;
  356. ring->last_seg = seg;
  357. seg->next = seg;
  358. seg->trbs = dma_alloc_coherent(dev, TRB_SEGMENT_SIZE, &dma, flags);
  359. if (!seg->trbs)
  360. goto dma_fail;
  361. seg->dma = dma;
  362. /* Only event ring does not use link TRB */
  363. if (type != TYPE_EVENT) {
  364. union xhci_trb *trb = &seg->trbs[TRBS_PER_SEGMENT - 1];
  365. trb->link.segment_ptr = cpu_to_le64(dma);
  366. trb->link.control = cpu_to_le32(LINK_TOGGLE | TRB_TYPE(TRB_LINK));
  367. }
  368. INIT_LIST_HEAD(&ring->td_list);
  369. xhci_initialize_ring_info(ring, 1);
  370. return ring;
  371. dma_fail:
  372. kfree(seg);
  373. seg_fail:
  374. kfree(ring);
  375. return NULL;
  376. }
  377. static int xhci_dbc_mem_init(struct xhci_dbc *dbc, gfp_t flags)
  378. {
  379. int ret;
  380. dma_addr_t deq;
  381. u32 string_length;
  382. struct device *dev = dbc->dev;
  383. /* Allocate various rings for events and transfers: */
  384. dbc->ring_evt = xhci_dbc_ring_alloc(dev, TYPE_EVENT, flags);
  385. if (!dbc->ring_evt)
  386. goto evt_fail;
  387. dbc->ring_in = xhci_dbc_ring_alloc(dev, TYPE_BULK, flags);
  388. if (!dbc->ring_in)
  389. goto in_fail;
  390. dbc->ring_out = xhci_dbc_ring_alloc(dev, TYPE_BULK, flags);
  391. if (!dbc->ring_out)
  392. goto out_fail;
  393. /* Allocate and populate ERST: */
  394. ret = dbc_erst_alloc(dev, dbc->ring_evt, &dbc->erst, flags);
  395. if (ret)
  396. goto erst_fail;
  397. /* Allocate context data structure: */
  398. dbc->ctx = dbc_alloc_ctx(dev, flags); /* was sysdev, and is still */
  399. if (!dbc->ctx)
  400. goto ctx_fail;
  401. /* Allocate the string table: */
  402. dbc->string_size = sizeof(struct dbc_str_descs);
  403. dbc->string = dma_alloc_coherent(dev, dbc->string_size,
  404. &dbc->string_dma, flags);
  405. if (!dbc->string)
  406. goto string_fail;
  407. /* Setup ERST register: */
  408. writel(dbc->erst.erst_size, &dbc->regs->ersts);
  409. lo_hi_writeq(dbc->erst.erst_dma_addr, &dbc->regs->erstba);
  410. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  411. dbc->ring_evt->dequeue);
  412. lo_hi_writeq(deq, &dbc->regs->erdp);
  413. /* Setup strings and contexts: */
  414. string_length = xhci_dbc_populate_strings(dbc->string);
  415. xhci_dbc_init_contexts(dbc, string_length);
  416. xhci_dbc_eps_init(dbc);
  417. dbc->state = DS_INITIALIZED;
  418. return 0;
  419. string_fail:
  420. dbc_free_ctx(dev, dbc->ctx);
  421. dbc->ctx = NULL;
  422. ctx_fail:
  423. dbc_erst_free(dev, &dbc->erst);
  424. erst_fail:
  425. dbc_ring_free(dev, dbc->ring_out);
  426. dbc->ring_out = NULL;
  427. out_fail:
  428. dbc_ring_free(dev, dbc->ring_in);
  429. dbc->ring_in = NULL;
  430. in_fail:
  431. dbc_ring_free(dev, dbc->ring_evt);
  432. dbc->ring_evt = NULL;
  433. evt_fail:
  434. return -ENOMEM;
  435. }
  436. static void xhci_dbc_mem_cleanup(struct xhci_dbc *dbc)
  437. {
  438. if (!dbc)
  439. return;
  440. xhci_dbc_eps_exit(dbc);
  441. if (dbc->string) {
  442. dma_free_coherent(dbc->dev, dbc->string_size,
  443. dbc->string, dbc->string_dma);
  444. dbc->string = NULL;
  445. }
  446. dbc_free_ctx(dbc->dev, dbc->ctx);
  447. dbc->ctx = NULL;
  448. dbc_erst_free(dbc->dev, &dbc->erst);
  449. dbc_ring_free(dbc->dev, dbc->ring_out);
  450. dbc_ring_free(dbc->dev, dbc->ring_in);
  451. dbc_ring_free(dbc->dev, dbc->ring_evt);
  452. dbc->ring_in = NULL;
  453. dbc->ring_out = NULL;
  454. dbc->ring_evt = NULL;
  455. }
  456. static int xhci_do_dbc_start(struct xhci_dbc *dbc)
  457. {
  458. int ret;
  459. u32 ctrl;
  460. if (dbc->state != DS_DISABLED)
  461. return -EINVAL;
  462. writel(0, &dbc->regs->control);
  463. ret = xhci_handshake(&dbc->regs->control,
  464. DBC_CTRL_DBC_ENABLE,
  465. 0, 1000);
  466. if (ret)
  467. return ret;
  468. ret = xhci_dbc_mem_init(dbc, GFP_ATOMIC);
  469. if (ret)
  470. return ret;
  471. ctrl = readl(&dbc->regs->control);
  472. writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
  473. &dbc->regs->control);
  474. ret = xhci_handshake(&dbc->regs->control,
  475. DBC_CTRL_DBC_ENABLE,
  476. DBC_CTRL_DBC_ENABLE, 1000);
  477. if (ret)
  478. return ret;
  479. dbc->state = DS_ENABLED;
  480. return 0;
  481. }
  482. static int xhci_do_dbc_stop(struct xhci_dbc *dbc)
  483. {
  484. if (dbc->state == DS_DISABLED)
  485. return -1;
  486. writel(0, &dbc->regs->control);
  487. dbc->state = DS_DISABLED;
  488. return 0;
  489. }
  490. static int xhci_dbc_start(struct xhci_dbc *dbc)
  491. {
  492. int ret;
  493. unsigned long flags;
  494. WARN_ON(!dbc);
  495. pm_runtime_get_sync(dbc->dev); /* note this was self.controller */
  496. spin_lock_irqsave(&dbc->lock, flags);
  497. ret = xhci_do_dbc_start(dbc);
  498. spin_unlock_irqrestore(&dbc->lock, flags);
  499. if (ret) {
  500. pm_runtime_put(dbc->dev); /* note this was self.controller */
  501. return ret;
  502. }
  503. return mod_delayed_work(system_wq, &dbc->event_work, 1);
  504. }
  505. static void xhci_dbc_stop(struct xhci_dbc *dbc)
  506. {
  507. int ret;
  508. unsigned long flags;
  509. WARN_ON(!dbc);
  510. switch (dbc->state) {
  511. case DS_DISABLED:
  512. return;
  513. case DS_CONFIGURED:
  514. case DS_STALLED:
  515. if (dbc->driver->disconnect)
  516. dbc->driver->disconnect(dbc);
  517. break;
  518. default:
  519. break;
  520. }
  521. cancel_delayed_work_sync(&dbc->event_work);
  522. spin_lock_irqsave(&dbc->lock, flags);
  523. ret = xhci_do_dbc_stop(dbc);
  524. spin_unlock_irqrestore(&dbc->lock, flags);
  525. if (!ret) {
  526. xhci_dbc_mem_cleanup(dbc);
  527. pm_runtime_put_sync(dbc->dev); /* note, was self.controller */
  528. }
  529. }
  530. static void
  531. dbc_handle_port_status(struct xhci_dbc *dbc, union xhci_trb *event)
  532. {
  533. u32 portsc;
  534. portsc = readl(&dbc->regs->portsc);
  535. if (portsc & DBC_PORTSC_CONN_CHANGE)
  536. dev_info(dbc->dev, "DbC port connect change\n");
  537. if (portsc & DBC_PORTSC_RESET_CHANGE)
  538. dev_info(dbc->dev, "DbC port reset change\n");
  539. if (portsc & DBC_PORTSC_LINK_CHANGE)
  540. dev_info(dbc->dev, "DbC port link status change\n");
  541. if (portsc & DBC_PORTSC_CONFIG_CHANGE)
  542. dev_info(dbc->dev, "DbC config error change\n");
  543. /* Port reset change bit will be cleared in other place: */
  544. writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
  545. }
  546. static void dbc_handle_xfer_event(struct xhci_dbc *dbc, union xhci_trb *event)
  547. {
  548. struct dbc_ep *dep;
  549. struct xhci_ring *ring;
  550. int ep_id;
  551. int status;
  552. u32 comp_code;
  553. size_t remain_length;
  554. struct dbc_request *req = NULL, *r;
  555. comp_code = GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
  556. remain_length = EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
  557. ep_id = TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
  558. dep = (ep_id == EPID_OUT) ?
  559. get_out_ep(dbc) : get_in_ep(dbc);
  560. ring = dep->ring;
  561. switch (comp_code) {
  562. case COMP_SUCCESS:
  563. remain_length = 0;
  564. fallthrough;
  565. case COMP_SHORT_PACKET:
  566. status = 0;
  567. break;
  568. case COMP_TRB_ERROR:
  569. case COMP_BABBLE_DETECTED_ERROR:
  570. case COMP_USB_TRANSACTION_ERROR:
  571. case COMP_STALL_ERROR:
  572. dev_warn(dbc->dev, "tx error %d detected\n", comp_code);
  573. status = -comp_code;
  574. break;
  575. default:
  576. dev_err(dbc->dev, "unknown tx error %d\n", comp_code);
  577. status = -comp_code;
  578. break;
  579. }
  580. /* Match the pending request: */
  581. list_for_each_entry(r, &dep->list_pending, list_pending) {
  582. if (r->trb_dma == event->trans_event.buffer) {
  583. req = r;
  584. break;
  585. }
  586. }
  587. if (!req) {
  588. dev_warn(dbc->dev, "no matched request\n");
  589. return;
  590. }
  591. trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
  592. ring->num_trbs_free++;
  593. req->actual = req->length - remain_length;
  594. xhci_dbc_giveback(req, status);
  595. }
  596. static void inc_evt_deq(struct xhci_ring *ring)
  597. {
  598. /* If on the last TRB of the segment go back to the beginning */
  599. if (ring->dequeue == &ring->deq_seg->trbs[TRBS_PER_SEGMENT - 1]) {
  600. ring->cycle_state ^= 1;
  601. ring->dequeue = ring->deq_seg->trbs;
  602. return;
  603. }
  604. ring->dequeue++;
  605. }
  606. static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
  607. {
  608. dma_addr_t deq;
  609. struct dbc_ep *dep;
  610. union xhci_trb *evt;
  611. u32 ctrl, portsc;
  612. bool update_erdp = false;
  613. /* DbC state machine: */
  614. switch (dbc->state) {
  615. case DS_DISABLED:
  616. case DS_INITIALIZED:
  617. return EVT_ERR;
  618. case DS_ENABLED:
  619. portsc = readl(&dbc->regs->portsc);
  620. if (portsc & DBC_PORTSC_CONN_STATUS) {
  621. dbc->state = DS_CONNECTED;
  622. dev_info(dbc->dev, "DbC connected\n");
  623. }
  624. return EVT_DONE;
  625. case DS_CONNECTED:
  626. ctrl = readl(&dbc->regs->control);
  627. if (ctrl & DBC_CTRL_DBC_RUN) {
  628. dbc->state = DS_CONFIGURED;
  629. dev_info(dbc->dev, "DbC configured\n");
  630. portsc = readl(&dbc->regs->portsc);
  631. writel(portsc, &dbc->regs->portsc);
  632. return EVT_GSER;
  633. }
  634. return EVT_DONE;
  635. case DS_CONFIGURED:
  636. /* Handle cable unplug event: */
  637. portsc = readl(&dbc->regs->portsc);
  638. if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
  639. !(portsc & DBC_PORTSC_CONN_STATUS)) {
  640. dev_info(dbc->dev, "DbC cable unplugged\n");
  641. dbc->state = DS_ENABLED;
  642. xhci_dbc_flush_requests(dbc);
  643. return EVT_DISC;
  644. }
  645. /* Handle debug port reset event: */
  646. if (portsc & DBC_PORTSC_RESET_CHANGE) {
  647. dev_info(dbc->dev, "DbC port reset\n");
  648. writel(portsc, &dbc->regs->portsc);
  649. dbc->state = DS_ENABLED;
  650. xhci_dbc_flush_requests(dbc);
  651. return EVT_DISC;
  652. }
  653. /* Handle endpoint stall event: */
  654. ctrl = readl(&dbc->regs->control);
  655. if ((ctrl & DBC_CTRL_HALT_IN_TR) ||
  656. (ctrl & DBC_CTRL_HALT_OUT_TR)) {
  657. dev_info(dbc->dev, "DbC Endpoint stall\n");
  658. dbc->state = DS_STALLED;
  659. if (ctrl & DBC_CTRL_HALT_IN_TR) {
  660. dep = get_in_ep(dbc);
  661. xhci_dbc_flush_endpoint_requests(dep);
  662. }
  663. if (ctrl & DBC_CTRL_HALT_OUT_TR) {
  664. dep = get_out_ep(dbc);
  665. xhci_dbc_flush_endpoint_requests(dep);
  666. }
  667. return EVT_DONE;
  668. }
  669. /* Clear DbC run change bit: */
  670. if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
  671. writel(ctrl, &dbc->regs->control);
  672. ctrl = readl(&dbc->regs->control);
  673. }
  674. break;
  675. case DS_STALLED:
  676. ctrl = readl(&dbc->regs->control);
  677. if (!(ctrl & DBC_CTRL_HALT_IN_TR) &&
  678. !(ctrl & DBC_CTRL_HALT_OUT_TR) &&
  679. (ctrl & DBC_CTRL_DBC_RUN)) {
  680. dbc->state = DS_CONFIGURED;
  681. break;
  682. }
  683. return EVT_DONE;
  684. default:
  685. dev_err(dbc->dev, "Unknown DbC state %d\n", dbc->state);
  686. break;
  687. }
  688. /* Handle the events in the event ring: */
  689. evt = dbc->ring_evt->dequeue;
  690. while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
  691. dbc->ring_evt->cycle_state) {
  692. /*
  693. * Add a barrier between reading the cycle flag and any
  694. * reads of the event's flags/data below:
  695. */
  696. rmb();
  697. trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
  698. switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
  699. case TRB_TYPE(TRB_PORT_STATUS):
  700. dbc_handle_port_status(dbc, evt);
  701. break;
  702. case TRB_TYPE(TRB_TRANSFER):
  703. dbc_handle_xfer_event(dbc, evt);
  704. break;
  705. default:
  706. break;
  707. }
  708. inc_evt_deq(dbc->ring_evt);
  709. evt = dbc->ring_evt->dequeue;
  710. update_erdp = true;
  711. }
  712. /* Update event ring dequeue pointer: */
  713. if (update_erdp) {
  714. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  715. dbc->ring_evt->dequeue);
  716. lo_hi_writeq(deq, &dbc->regs->erdp);
  717. }
  718. return EVT_DONE;
  719. }
  720. static void xhci_dbc_handle_events(struct work_struct *work)
  721. {
  722. enum evtreturn evtr;
  723. struct xhci_dbc *dbc;
  724. unsigned long flags;
  725. dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
  726. spin_lock_irqsave(&dbc->lock, flags);
  727. evtr = xhci_dbc_do_handle_events(dbc);
  728. spin_unlock_irqrestore(&dbc->lock, flags);
  729. switch (evtr) {
  730. case EVT_GSER:
  731. if (dbc->driver->configure)
  732. dbc->driver->configure(dbc);
  733. break;
  734. case EVT_DISC:
  735. if (dbc->driver->disconnect)
  736. dbc->driver->disconnect(dbc);
  737. break;
  738. case EVT_DONE:
  739. break;
  740. default:
  741. dev_info(dbc->dev, "stop handling dbc events\n");
  742. return;
  743. }
  744. mod_delayed_work(system_wq, &dbc->event_work, 1);
  745. }
  746. static void xhci_do_dbc_exit(struct xhci_hcd *xhci)
  747. {
  748. unsigned long flags;
  749. spin_lock_irqsave(&xhci->lock, flags);
  750. kfree(xhci->dbc);
  751. xhci->dbc = NULL;
  752. spin_unlock_irqrestore(&xhci->lock, flags);
  753. }
  754. static int xhci_do_dbc_init(struct xhci_hcd *xhci)
  755. {
  756. u32 reg;
  757. struct xhci_dbc *dbc;
  758. unsigned long flags;
  759. void __iomem *base;
  760. int dbc_cap_offs;
  761. base = &xhci->cap_regs->hc_capbase;
  762. dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
  763. if (!dbc_cap_offs)
  764. return -ENODEV;
  765. dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
  766. if (!dbc)
  767. return -ENOMEM;
  768. dbc->regs = base + dbc_cap_offs;
  769. /* We will avoid using DbC in xhci driver if it's in use. */
  770. reg = readl(&dbc->regs->control);
  771. if (reg & DBC_CTRL_DBC_ENABLE) {
  772. kfree(dbc);
  773. return -EBUSY;
  774. }
  775. spin_lock_irqsave(&xhci->lock, flags);
  776. if (xhci->dbc) {
  777. spin_unlock_irqrestore(&xhci->lock, flags);
  778. kfree(dbc);
  779. return -EBUSY;
  780. }
  781. xhci->dbc = dbc;
  782. spin_unlock_irqrestore(&xhci->lock, flags);
  783. dbc->xhci = xhci;
  784. dbc->dev = xhci_to_hcd(xhci)->self.sysdev;
  785. INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
  786. spin_lock_init(&dbc->lock);
  787. return 0;
  788. }
  789. static ssize_t dbc_show(struct device *dev,
  790. struct device_attribute *attr,
  791. char *buf)
  792. {
  793. const char *p;
  794. struct xhci_dbc *dbc;
  795. struct xhci_hcd *xhci;
  796. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  797. dbc = xhci->dbc;
  798. switch (dbc->state) {
  799. case DS_DISABLED:
  800. p = "disabled";
  801. break;
  802. case DS_INITIALIZED:
  803. p = "initialized";
  804. break;
  805. case DS_ENABLED:
  806. p = "enabled";
  807. break;
  808. case DS_CONNECTED:
  809. p = "connected";
  810. break;
  811. case DS_CONFIGURED:
  812. p = "configured";
  813. break;
  814. case DS_STALLED:
  815. p = "stalled";
  816. break;
  817. default:
  818. p = "unknown";
  819. }
  820. return sprintf(buf, "%s\n", p);
  821. }
  822. static ssize_t dbc_store(struct device *dev,
  823. struct device_attribute *attr,
  824. const char *buf, size_t count)
  825. {
  826. struct xhci_hcd *xhci;
  827. struct xhci_dbc *dbc;
  828. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  829. dbc = xhci->dbc;
  830. if (!strncmp(buf, "enable", 6))
  831. xhci_dbc_start(dbc);
  832. else if (!strncmp(buf, "disable", 7))
  833. xhci_dbc_stop(dbc);
  834. else
  835. return -EINVAL;
  836. return count;
  837. }
  838. static DEVICE_ATTR_RW(dbc);
  839. int xhci_dbc_init(struct xhci_hcd *xhci)
  840. {
  841. int ret;
  842. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  843. ret = xhci_do_dbc_init(xhci);
  844. if (ret)
  845. goto init_err3;
  846. ret = xhci_dbc_tty_probe(xhci);
  847. if (ret)
  848. goto init_err2;
  849. ret = device_create_file(dev, &dev_attr_dbc);
  850. if (ret)
  851. goto init_err1;
  852. return 0;
  853. init_err1:
  854. xhci_dbc_tty_remove(xhci->dbc);
  855. init_err2:
  856. xhci_do_dbc_exit(xhci);
  857. init_err3:
  858. return ret;
  859. }
  860. void xhci_dbc_exit(struct xhci_hcd *xhci)
  861. {
  862. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  863. if (!xhci->dbc)
  864. return;
  865. device_remove_file(dev, &dev_attr_dbc);
  866. xhci_dbc_tty_remove(xhci->dbc);
  867. xhci_dbc_stop(xhci->dbc);
  868. xhci_do_dbc_exit(xhci);
  869. }
  870. #ifdef CONFIG_PM
  871. int xhci_dbc_suspend(struct xhci_hcd *xhci)
  872. {
  873. struct xhci_dbc *dbc = xhci->dbc;
  874. if (!dbc)
  875. return 0;
  876. if (dbc->state == DS_CONFIGURED)
  877. dbc->resume_required = 1;
  878. xhci_dbc_stop(dbc);
  879. return 0;
  880. }
  881. int xhci_dbc_resume(struct xhci_hcd *xhci)
  882. {
  883. int ret = 0;
  884. struct xhci_dbc *dbc = xhci->dbc;
  885. if (!dbc)
  886. return 0;
  887. if (dbc->resume_required) {
  888. dbc->resume_required = 0;
  889. xhci_dbc_start(dbc);
  890. }
  891. return ret;
  892. }
  893. #endif /* CONFIG_PM */