ohci-q.c 34 KB

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  1. // SPDX-License-Identifier: GPL-1.0+
  2. /*
  3. * OHCI HCD (Host Controller Driver) for USB.
  4. *
  5. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  6. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  7. *
  8. * This file is licenced under the GPL.
  9. */
  10. #include <linux/irq.h>
  11. #include <linux/slab.h>
  12. static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  13. {
  14. int last = urb_priv->length - 1;
  15. if (last >= 0) {
  16. int i;
  17. struct td *td;
  18. for (i = 0; i <= last; i++) {
  19. td = urb_priv->td [i];
  20. if (td)
  21. td_free (hc, td);
  22. }
  23. }
  24. list_del (&urb_priv->pending);
  25. kfree (urb_priv);
  26. }
  27. /*-------------------------------------------------------------------------*/
  28. /*
  29. * URB goes back to driver, and isn't reissued.
  30. * It's completely gone from HC data structures.
  31. * PRECONDITION: ohci lock held, irqs blocked.
  32. */
  33. static void
  34. finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  35. __releases(ohci->lock)
  36. __acquires(ohci->lock)
  37. {
  38. struct device *dev = ohci_to_hcd(ohci)->self.controller;
  39. struct usb_host_endpoint *ep = urb->ep;
  40. struct urb_priv *urb_priv;
  41. // ASSERT (urb->hcpriv != 0);
  42. restart:
  43. urb_free_priv (ohci, urb->hcpriv);
  44. urb->hcpriv = NULL;
  45. if (likely(status == -EINPROGRESS))
  46. status = 0;
  47. switch (usb_pipetype (urb->pipe)) {
  48. case PIPE_ISOCHRONOUS:
  49. ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  50. if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  51. if (quirk_amdiso(ohci))
  52. usb_amd_quirk_pll_enable();
  53. if (quirk_amdprefetch(ohci))
  54. sb800_prefetch(dev, 0);
  55. }
  56. break;
  57. case PIPE_INTERRUPT:
  58. ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  59. break;
  60. }
  61. /* urb->complete() can reenter this HCD */
  62. usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  63. spin_unlock (&ohci->lock);
  64. usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  65. spin_lock (&ohci->lock);
  66. /* stop periodic dma if it's not needed */
  67. if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  68. && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  69. ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  70. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  71. }
  72. /*
  73. * An isochronous URB that is sumitted too late won't have any TDs
  74. * (marked by the fact that the td_cnt value is larger than the
  75. * actual number of TDs). If the next URB on this endpoint is like
  76. * that, give it back now.
  77. */
  78. if (!list_empty(&ep->urb_list)) {
  79. urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
  80. urb_priv = urb->hcpriv;
  81. if (urb_priv->td_cnt > urb_priv->length) {
  82. status = 0;
  83. goto restart;
  84. }
  85. }
  86. }
  87. /*-------------------------------------------------------------------------*
  88. * ED handling functions
  89. *-------------------------------------------------------------------------*/
  90. /* search for the right schedule branch to use for a periodic ed.
  91. * does some load balancing; returns the branch, or negative errno.
  92. */
  93. static int balance (struct ohci_hcd *ohci, int interval, int load)
  94. {
  95. int i, branch = -ENOSPC;
  96. /* iso periods can be huge; iso tds specify frame numbers */
  97. if (interval > NUM_INTS)
  98. interval = NUM_INTS;
  99. /* search for the least loaded schedule branch of that period
  100. * that has enough bandwidth left unreserved.
  101. */
  102. for (i = 0; i < interval ; i++) {
  103. if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
  104. int j;
  105. /* usb 1.1 says 90% of one frame */
  106. for (j = i; j < NUM_INTS; j += interval) {
  107. if ((ohci->load [j] + load) > 900)
  108. break;
  109. }
  110. if (j < NUM_INTS)
  111. continue;
  112. branch = i;
  113. }
  114. }
  115. return branch;
  116. }
  117. /*-------------------------------------------------------------------------*/
  118. /* both iso and interrupt requests have periods; this routine puts them
  119. * into the schedule tree in the apppropriate place. most iso devices use
  120. * 1msec periods, but that's not required.
  121. */
  122. static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
  123. {
  124. unsigned i;
  125. ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n",
  126. (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
  127. ed, ed->branch, ed->load, ed->interval);
  128. for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
  129. struct ed **prev = &ohci->periodic [i];
  130. __hc32 *prev_p = &ohci->hcca->int_table [i];
  131. struct ed *here = *prev;
  132. /* sorting each branch by period (slow before fast)
  133. * lets us share the faster parts of the tree.
  134. * (plus maybe: put interrupt eds before iso)
  135. */
  136. while (here && ed != here) {
  137. if (ed->interval > here->interval)
  138. break;
  139. prev = &here->ed_next;
  140. prev_p = &here->hwNextED;
  141. here = *prev;
  142. }
  143. if (ed != here) {
  144. ed->ed_next = here;
  145. if (here)
  146. ed->hwNextED = *prev_p;
  147. wmb ();
  148. *prev = ed;
  149. *prev_p = cpu_to_hc32(ohci, ed->dma);
  150. wmb();
  151. }
  152. ohci->load [i] += ed->load;
  153. }
  154. ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
  155. }
  156. /* link an ed into one of the HC chains */
  157. static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
  158. {
  159. int branch;
  160. ed->ed_prev = NULL;
  161. ed->ed_next = NULL;
  162. ed->hwNextED = 0;
  163. wmb ();
  164. /* we care about rm_list when setting CLE/BLE in case the HC was at
  165. * work on some TD when CLE/BLE was turned off, and isn't quiesced
  166. * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
  167. *
  168. * control and bulk EDs are doubly linked (ed_next, ed_prev), but
  169. * periodic ones are singly linked (ed_next). that's because the
  170. * periodic schedule encodes a tree like figure 3-5 in the ohci
  171. * spec: each qh can have several "previous" nodes, and the tree
  172. * doesn't have unused/idle descriptors.
  173. */
  174. switch (ed->type) {
  175. case PIPE_CONTROL:
  176. if (ohci->ed_controltail == NULL) {
  177. WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
  178. ohci_writel (ohci, ed->dma,
  179. &ohci->regs->ed_controlhead);
  180. } else {
  181. ohci->ed_controltail->ed_next = ed;
  182. ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
  183. ed->dma);
  184. }
  185. ed->ed_prev = ohci->ed_controltail;
  186. if (!ohci->ed_controltail && !ohci->ed_rm_list) {
  187. wmb();
  188. ohci->hc_control |= OHCI_CTRL_CLE;
  189. ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
  190. ohci_writel (ohci, ohci->hc_control,
  191. &ohci->regs->control);
  192. }
  193. ohci->ed_controltail = ed;
  194. break;
  195. case PIPE_BULK:
  196. if (ohci->ed_bulktail == NULL) {
  197. WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
  198. ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
  199. } else {
  200. ohci->ed_bulktail->ed_next = ed;
  201. ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
  202. ed->dma);
  203. }
  204. ed->ed_prev = ohci->ed_bulktail;
  205. if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
  206. wmb();
  207. ohci->hc_control |= OHCI_CTRL_BLE;
  208. ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
  209. ohci_writel (ohci, ohci->hc_control,
  210. &ohci->regs->control);
  211. }
  212. ohci->ed_bulktail = ed;
  213. break;
  214. // case PIPE_INTERRUPT:
  215. // case PIPE_ISOCHRONOUS:
  216. default:
  217. branch = balance (ohci, ed->interval, ed->load);
  218. if (branch < 0) {
  219. ohci_dbg (ohci,
  220. "ERR %d, interval %d msecs, load %d\n",
  221. branch, ed->interval, ed->load);
  222. // FIXME if there are TDs queued, fail them!
  223. return branch;
  224. }
  225. ed->branch = branch;
  226. periodic_link (ohci, ed);
  227. }
  228. /* the HC may not see the schedule updates yet, but if it does
  229. * then they'll be properly ordered.
  230. */
  231. ed->state = ED_OPER;
  232. return 0;
  233. }
  234. /*-------------------------------------------------------------------------*/
  235. /* scan the periodic table to find and unlink this ED */
  236. static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
  237. {
  238. int i;
  239. for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
  240. struct ed *temp;
  241. struct ed **prev = &ohci->periodic [i];
  242. __hc32 *prev_p = &ohci->hcca->int_table [i];
  243. while (*prev && (temp = *prev) != ed) {
  244. prev_p = &temp->hwNextED;
  245. prev = &temp->ed_next;
  246. }
  247. if (*prev) {
  248. *prev_p = ed->hwNextED;
  249. *prev = ed->ed_next;
  250. }
  251. ohci->load [i] -= ed->load;
  252. }
  253. ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
  254. ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
  255. (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
  256. ed, ed->branch, ed->load, ed->interval);
  257. }
  258. /* unlink an ed from one of the HC chains.
  259. * just the link to the ed is unlinked.
  260. * the link from the ed still points to another operational ed or 0
  261. * so the HC can eventually finish the processing of the unlinked ed
  262. * (assuming it already started that, which needn't be true).
  263. *
  264. * ED_UNLINK is a transient state: the HC may still see this ED, but soon
  265. * it won't. ED_SKIP means the HC will finish its current transaction,
  266. * but won't start anything new. The TD queue may still grow; device
  267. * drivers don't know about this HCD-internal state.
  268. *
  269. * When the HC can't see the ED, something changes ED_UNLINK to one of:
  270. *
  271. * - ED_OPER: when there's any request queued, the ED gets rescheduled
  272. * immediately. HC should be working on them.
  273. *
  274. * - ED_IDLE: when there's no TD queue or the HC isn't running.
  275. *
  276. * When finish_unlinks() runs later, after SOF interrupt, it will often
  277. * complete one or more URB unlinks before making that state change.
  278. */
  279. static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
  280. {
  281. ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
  282. wmb ();
  283. ed->state = ED_UNLINK;
  284. /* To deschedule something from the control or bulk list, just
  285. * clear CLE/BLE and wait. There's no safe way to scrub out list
  286. * head/current registers until later, and "later" isn't very
  287. * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
  288. * the HC is reading the ED queues (while we modify them).
  289. *
  290. * For now, ed_schedule() is "later". It might be good paranoia
  291. * to scrub those registers in finish_unlinks(), in case of bugs
  292. * that make the HC try to use them.
  293. */
  294. switch (ed->type) {
  295. case PIPE_CONTROL:
  296. /* remove ED from the HC's list: */
  297. if (ed->ed_prev == NULL) {
  298. if (!ed->hwNextED) {
  299. ohci->hc_control &= ~OHCI_CTRL_CLE;
  300. ohci_writel (ohci, ohci->hc_control,
  301. &ohci->regs->control);
  302. // a ohci_readl() later syncs CLE with the HC
  303. } else
  304. ohci_writel (ohci,
  305. hc32_to_cpup (ohci, &ed->hwNextED),
  306. &ohci->regs->ed_controlhead);
  307. } else {
  308. ed->ed_prev->ed_next = ed->ed_next;
  309. ed->ed_prev->hwNextED = ed->hwNextED;
  310. }
  311. /* remove ED from the HCD's list: */
  312. if (ohci->ed_controltail == ed) {
  313. ohci->ed_controltail = ed->ed_prev;
  314. if (ohci->ed_controltail)
  315. ohci->ed_controltail->ed_next = NULL;
  316. } else if (ed->ed_next) {
  317. ed->ed_next->ed_prev = ed->ed_prev;
  318. }
  319. break;
  320. case PIPE_BULK:
  321. /* remove ED from the HC's list: */
  322. if (ed->ed_prev == NULL) {
  323. if (!ed->hwNextED) {
  324. ohci->hc_control &= ~OHCI_CTRL_BLE;
  325. ohci_writel (ohci, ohci->hc_control,
  326. &ohci->regs->control);
  327. // a ohci_readl() later syncs BLE with the HC
  328. } else
  329. ohci_writel (ohci,
  330. hc32_to_cpup (ohci, &ed->hwNextED),
  331. &ohci->regs->ed_bulkhead);
  332. } else {
  333. ed->ed_prev->ed_next = ed->ed_next;
  334. ed->ed_prev->hwNextED = ed->hwNextED;
  335. }
  336. /* remove ED from the HCD's list: */
  337. if (ohci->ed_bulktail == ed) {
  338. ohci->ed_bulktail = ed->ed_prev;
  339. if (ohci->ed_bulktail)
  340. ohci->ed_bulktail->ed_next = NULL;
  341. } else if (ed->ed_next) {
  342. ed->ed_next->ed_prev = ed->ed_prev;
  343. }
  344. break;
  345. // case PIPE_INTERRUPT:
  346. // case PIPE_ISOCHRONOUS:
  347. default:
  348. periodic_unlink (ohci, ed);
  349. break;
  350. }
  351. }
  352. /*-------------------------------------------------------------------------*/
  353. /* get and maybe (re)init an endpoint. init _should_ be done only as part
  354. * of enumeration, usb_set_configuration() or usb_set_interface().
  355. */
  356. static struct ed *ed_get (
  357. struct ohci_hcd *ohci,
  358. struct usb_host_endpoint *ep,
  359. struct usb_device *udev,
  360. unsigned int pipe,
  361. int interval
  362. ) {
  363. struct ed *ed;
  364. unsigned long flags;
  365. spin_lock_irqsave (&ohci->lock, flags);
  366. ed = ep->hcpriv;
  367. if (!ed) {
  368. struct td *td;
  369. int is_out;
  370. u32 info;
  371. ed = ed_alloc (ohci, GFP_ATOMIC);
  372. if (!ed) {
  373. /* out of memory */
  374. goto done;
  375. }
  376. /* dummy td; end of td list for ed */
  377. td = td_alloc (ohci, GFP_ATOMIC);
  378. if (!td) {
  379. /* out of memory */
  380. ed_free (ohci, ed);
  381. ed = NULL;
  382. goto done;
  383. }
  384. ed->dummy = td;
  385. ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
  386. ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
  387. ed->state = ED_IDLE;
  388. is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
  389. /* FIXME usbcore changes dev->devnum before SET_ADDRESS
  390. * succeeds ... otherwise we wouldn't need "pipe".
  391. */
  392. info = usb_pipedevice (pipe);
  393. ed->type = usb_pipetype(pipe);
  394. info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
  395. info |= usb_endpoint_maxp(&ep->desc) << 16;
  396. if (udev->speed == USB_SPEED_LOW)
  397. info |= ED_LOWSPEED;
  398. /* only control transfers store pids in tds */
  399. if (ed->type != PIPE_CONTROL) {
  400. info |= is_out ? ED_OUT : ED_IN;
  401. if (ed->type != PIPE_BULK) {
  402. /* periodic transfers... */
  403. if (ed->type == PIPE_ISOCHRONOUS)
  404. info |= ED_ISO;
  405. else if (interval > 32) /* iso can be bigger */
  406. interval = 32;
  407. ed->interval = interval;
  408. ed->load = usb_calc_bus_time (
  409. udev->speed, !is_out,
  410. ed->type == PIPE_ISOCHRONOUS,
  411. usb_endpoint_maxp(&ep->desc))
  412. / 1000;
  413. }
  414. }
  415. ed->hwINFO = cpu_to_hc32(ohci, info);
  416. ep->hcpriv = ed;
  417. }
  418. done:
  419. spin_unlock_irqrestore (&ohci->lock, flags);
  420. return ed;
  421. }
  422. /*-------------------------------------------------------------------------*/
  423. /* request unlinking of an endpoint from an operational HC.
  424. * put the ep on the rm_list
  425. * real work is done at the next start frame (SF) hardware interrupt
  426. * caller guarantees HCD is running, so hardware access is safe,
  427. * and that ed->state is ED_OPER
  428. */
  429. static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
  430. {
  431. ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
  432. ed_deschedule (ohci, ed);
  433. /* rm_list is just singly linked, for simplicity */
  434. ed->ed_next = ohci->ed_rm_list;
  435. ed->ed_prev = NULL;
  436. ohci->ed_rm_list = ed;
  437. /* enable SOF interrupt */
  438. ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
  439. ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
  440. // flush those writes, and get latest HCCA contents
  441. (void) ohci_readl (ohci, &ohci->regs->control);
  442. /* SF interrupt might get delayed; record the frame counter value that
  443. * indicates when the HC isn't looking at it, so concurrent unlinks
  444. * behave. frame_no wraps every 2^16 msec, and changes right before
  445. * SF is triggered.
  446. */
  447. ed->tick = ohci_frame_no(ohci) + 1;
  448. }
  449. /*-------------------------------------------------------------------------*
  450. * TD handling functions
  451. *-------------------------------------------------------------------------*/
  452. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  453. static void
  454. td_fill (struct ohci_hcd *ohci, u32 info,
  455. dma_addr_t data, int len,
  456. struct urb *urb, int index)
  457. {
  458. struct td *td, *td_pt;
  459. struct urb_priv *urb_priv = urb->hcpriv;
  460. int is_iso = info & TD_ISO;
  461. int hash;
  462. // ASSERT (index < urb_priv->length);
  463. /* aim for only one interrupt per urb. mostly applies to control
  464. * and iso; other urbs rarely need more than one TD per urb.
  465. * this way, only final tds (or ones with an error) cause IRQs.
  466. * at least immediately; use DI=6 in case any control request is
  467. * tempted to die part way through. (and to force the hc to flush
  468. * its donelist soonish, even on unlink paths.)
  469. *
  470. * NOTE: could delay interrupts even for the last TD, and get fewer
  471. * interrupts ... increasing per-urb latency by sharing interrupts.
  472. * Drivers that queue bulk urbs may request that behavior.
  473. */
  474. if (index != (urb_priv->length - 1)
  475. || (urb->transfer_flags & URB_NO_INTERRUPT))
  476. info |= TD_DI_SET (6);
  477. /* use this td as the next dummy */
  478. td_pt = urb_priv->td [index];
  479. /* fill the old dummy TD */
  480. td = urb_priv->td [index] = urb_priv->ed->dummy;
  481. urb_priv->ed->dummy = td_pt;
  482. td->ed = urb_priv->ed;
  483. td->next_dl_td = NULL;
  484. td->index = index;
  485. td->urb = urb;
  486. td->data_dma = data;
  487. if (!len)
  488. data = 0;
  489. td->hwINFO = cpu_to_hc32 (ohci, info);
  490. if (is_iso) {
  491. td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
  492. *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
  493. (data & 0x0FFF) | 0xE000);
  494. } else {
  495. td->hwCBP = cpu_to_hc32 (ohci, data);
  496. }
  497. if (data)
  498. td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
  499. else
  500. td->hwBE = 0;
  501. td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
  502. /* append to queue */
  503. list_add_tail (&td->td_list, &td->ed->td_list);
  504. /* hash it for later reverse mapping */
  505. hash = TD_HASH_FUNC (td->td_dma);
  506. td->td_hash = ohci->td_hash [hash];
  507. ohci->td_hash [hash] = td;
  508. /* HC might read the TD (or cachelines) right away ... */
  509. wmb ();
  510. td->ed->hwTailP = td->hwNextTD;
  511. }
  512. /*-------------------------------------------------------------------------*/
  513. /* Prepare all TDs of a transfer, and queue them onto the ED.
  514. * Caller guarantees HC is active.
  515. * Usually the ED is already on the schedule, so TDs might be
  516. * processed as soon as they're queued.
  517. */
  518. static void td_submit_urb (
  519. struct ohci_hcd *ohci,
  520. struct urb *urb
  521. ) {
  522. struct urb_priv *urb_priv = urb->hcpriv;
  523. struct device *dev = ohci_to_hcd(ohci)->self.controller;
  524. dma_addr_t data;
  525. int data_len = urb->transfer_buffer_length;
  526. int cnt = 0;
  527. u32 info = 0;
  528. int is_out = usb_pipeout (urb->pipe);
  529. int periodic = 0;
  530. int i, this_sg_len, n;
  531. struct scatterlist *sg;
  532. /* OHCI handles the bulk/interrupt data toggles itself. We just
  533. * use the device toggle bits for resetting, and rely on the fact
  534. * that resetting toggle is meaningless if the endpoint is active.
  535. */
  536. if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
  537. usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
  538. is_out, 1);
  539. urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
  540. }
  541. list_add (&urb_priv->pending, &ohci->pending);
  542. i = urb->num_mapped_sgs;
  543. if (data_len > 0 && i > 0) {
  544. sg = urb->sg;
  545. data = sg_dma_address(sg);
  546. /*
  547. * urb->transfer_buffer_length may be smaller than the
  548. * size of the scatterlist (or vice versa)
  549. */
  550. this_sg_len = min_t(int, sg_dma_len(sg), data_len);
  551. } else {
  552. sg = NULL;
  553. if (data_len)
  554. data = urb->transfer_dma;
  555. else
  556. data = 0;
  557. this_sg_len = data_len;
  558. }
  559. /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
  560. * using TD_CC_GET, as well as by seeing them on the done list.
  561. * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
  562. */
  563. switch (urb_priv->ed->type) {
  564. /* Bulk and interrupt are identical except for where in the schedule
  565. * their EDs live.
  566. */
  567. case PIPE_INTERRUPT:
  568. /* ... and periodic urbs have extra accounting */
  569. periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
  570. && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
  571. fallthrough;
  572. case PIPE_BULK:
  573. info = is_out
  574. ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
  575. : TD_T_TOGGLE | TD_CC | TD_DP_IN;
  576. /* TDs _could_ transfer up to 8K each */
  577. for (;;) {
  578. n = min(this_sg_len, 4096);
  579. /* maybe avoid ED halt on final TD short read */
  580. if (n >= data_len || (i == 1 && n >= this_sg_len)) {
  581. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  582. info |= TD_R;
  583. }
  584. td_fill(ohci, info, data, n, urb, cnt);
  585. this_sg_len -= n;
  586. data_len -= n;
  587. data += n;
  588. cnt++;
  589. if (this_sg_len <= 0) {
  590. if (--i <= 0 || data_len <= 0)
  591. break;
  592. sg = sg_next(sg);
  593. data = sg_dma_address(sg);
  594. this_sg_len = min_t(int, sg_dma_len(sg),
  595. data_len);
  596. }
  597. }
  598. if ((urb->transfer_flags & URB_ZERO_PACKET)
  599. && cnt < urb_priv->length) {
  600. td_fill (ohci, info, 0, 0, urb, cnt);
  601. cnt++;
  602. }
  603. /* maybe kickstart bulk list */
  604. if (urb_priv->ed->type == PIPE_BULK) {
  605. wmb ();
  606. ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
  607. }
  608. break;
  609. /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
  610. * any DATA phase works normally, and the STATUS ack is special.
  611. */
  612. case PIPE_CONTROL:
  613. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  614. td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
  615. if (data_len > 0) {
  616. info = TD_CC | TD_R | TD_T_DATA1;
  617. info |= is_out ? TD_DP_OUT : TD_DP_IN;
  618. /* NOTE: mishandles transfers >8K, some >4K */
  619. td_fill (ohci, info, data, data_len, urb, cnt++);
  620. }
  621. info = (is_out || data_len == 0)
  622. ? TD_CC | TD_DP_IN | TD_T_DATA1
  623. : TD_CC | TD_DP_OUT | TD_T_DATA1;
  624. td_fill (ohci, info, data, 0, urb, cnt++);
  625. /* maybe kickstart control list */
  626. wmb ();
  627. ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
  628. break;
  629. /* ISO has no retransmit, so no toggle; and it uses special TDs.
  630. * Each TD could handle multiple consecutive frames (interval 1);
  631. * we could often reduce the number of TDs here.
  632. */
  633. case PIPE_ISOCHRONOUS:
  634. for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
  635. cnt++) {
  636. int frame = urb->start_frame;
  637. // FIXME scheduling should handle frame counter
  638. // roll-around ... exotic case (and OHCI has
  639. // a 2^16 iso range, vs other HCs max of 2^10)
  640. frame += cnt * urb->interval;
  641. frame &= 0xffff;
  642. td_fill (ohci, TD_CC | TD_ISO | frame,
  643. data + urb->iso_frame_desc [cnt].offset,
  644. urb->iso_frame_desc [cnt].length, urb, cnt);
  645. }
  646. if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  647. if (quirk_amdiso(ohci))
  648. usb_amd_quirk_pll_disable();
  649. if (quirk_amdprefetch(ohci))
  650. sb800_prefetch(dev, 1);
  651. }
  652. periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
  653. && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
  654. break;
  655. }
  656. /* start periodic dma if needed */
  657. if (periodic) {
  658. wmb ();
  659. ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
  660. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  661. }
  662. // ASSERT (urb_priv->length == cnt);
  663. }
  664. /*-------------------------------------------------------------------------*
  665. * Done List handling functions
  666. *-------------------------------------------------------------------------*/
  667. /* calculate transfer length/status and update the urb */
  668. static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
  669. {
  670. u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
  671. int cc = 0;
  672. int status = -EINPROGRESS;
  673. list_del (&td->td_list);
  674. /* ISO ... drivers see per-TD length/status */
  675. if (tdINFO & TD_ISO) {
  676. u16 tdPSW = ohci_hwPSW(ohci, td, 0);
  677. int dlen = 0;
  678. /* NOTE: assumes FC in tdINFO == 0, and that
  679. * only the first of 0..MAXPSW psws is used.
  680. */
  681. cc = (tdPSW >> 12) & 0xF;
  682. if (tdINFO & TD_CC) /* hc didn't touch? */
  683. return status;
  684. if (usb_pipeout (urb->pipe))
  685. dlen = urb->iso_frame_desc [td->index].length;
  686. else {
  687. /* short reads are always OK for ISO */
  688. if (cc == TD_DATAUNDERRUN)
  689. cc = TD_CC_NOERROR;
  690. dlen = tdPSW & 0x3ff;
  691. }
  692. urb->actual_length += dlen;
  693. urb->iso_frame_desc [td->index].actual_length = dlen;
  694. urb->iso_frame_desc [td->index].status = cc_to_error [cc];
  695. if (cc != TD_CC_NOERROR)
  696. ohci_dbg(ohci,
  697. "urb %p iso td %p (%d) len %d cc %d\n",
  698. urb, td, 1 + td->index, dlen, cc);
  699. /* BULK, INT, CONTROL ... drivers see aggregate length/status,
  700. * except that "setup" bytes aren't counted and "short" transfers
  701. * might not be reported as errors.
  702. */
  703. } else {
  704. int type = usb_pipetype (urb->pipe);
  705. u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
  706. cc = TD_CC_GET (tdINFO);
  707. /* update packet status if needed (short is normally ok) */
  708. if (cc == TD_DATAUNDERRUN
  709. && !(urb->transfer_flags & URB_SHORT_NOT_OK))
  710. cc = TD_CC_NOERROR;
  711. if (cc != TD_CC_NOERROR && cc < 0x0E)
  712. status = cc_to_error[cc];
  713. /* count all non-empty packets except control SETUP packet */
  714. if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
  715. if (td->hwCBP == 0)
  716. urb->actual_length += tdBE - td->data_dma + 1;
  717. else
  718. urb->actual_length +=
  719. hc32_to_cpup (ohci, &td->hwCBP)
  720. - td->data_dma;
  721. }
  722. if (cc != TD_CC_NOERROR && cc < 0x0E)
  723. ohci_dbg(ohci,
  724. "urb %p td %p (%d) cc %d, len=%d/%d\n",
  725. urb, td, 1 + td->index, cc,
  726. urb->actual_length,
  727. urb->transfer_buffer_length);
  728. }
  729. return status;
  730. }
  731. /*-------------------------------------------------------------------------*/
  732. static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
  733. {
  734. struct urb *urb = td->urb;
  735. urb_priv_t *urb_priv = urb->hcpriv;
  736. struct ed *ed = td->ed;
  737. struct list_head *tmp = td->td_list.next;
  738. __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
  739. /* clear ed halt; this is the td that caused it, but keep it inactive
  740. * until its urb->complete() has a chance to clean up.
  741. */
  742. ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
  743. wmb ();
  744. ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
  745. /* Get rid of all later tds from this urb. We don't have
  746. * to be careful: no errors and nothing was transferred.
  747. * Also patch the ed so it looks as if those tds completed normally.
  748. */
  749. while (tmp != &ed->td_list) {
  750. struct td *next;
  751. next = list_entry (tmp, struct td, td_list);
  752. tmp = next->td_list.next;
  753. if (next->urb != urb)
  754. break;
  755. /* NOTE: if multi-td control DATA segments get supported,
  756. * this urb had one of them, this td wasn't the last td
  757. * in that segment (TD_R clear), this ed halted because
  758. * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
  759. * then we need to leave the control STATUS packet queued
  760. * and clear ED_SKIP.
  761. */
  762. list_del(&next->td_list);
  763. urb_priv->td_cnt++;
  764. ed->hwHeadP = next->hwNextTD | toggle;
  765. }
  766. /* help for troubleshooting: report anything that
  767. * looks odd ... that doesn't include protocol stalls
  768. * (or maybe some other things)
  769. */
  770. switch (cc) {
  771. case TD_DATAUNDERRUN:
  772. if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
  773. break;
  774. fallthrough;
  775. case TD_CC_STALL:
  776. if (usb_pipecontrol (urb->pipe))
  777. break;
  778. fallthrough;
  779. default:
  780. ohci_dbg (ohci,
  781. "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
  782. urb, urb->dev->devpath,
  783. usb_pipeendpoint (urb->pipe),
  784. usb_pipein (urb->pipe) ? "in" : "out",
  785. hc32_to_cpu (ohci, td->hwINFO),
  786. cc, cc_to_error [cc]);
  787. }
  788. }
  789. /* Add a TD to the done list */
  790. static void add_to_done_list(struct ohci_hcd *ohci, struct td *td)
  791. {
  792. struct td *td2, *td_prev;
  793. struct ed *ed;
  794. if (td->next_dl_td)
  795. return; /* Already on the list */
  796. /* Add all the TDs going back until we reach one that's on the list */
  797. ed = td->ed;
  798. td2 = td_prev = td;
  799. list_for_each_entry_continue_reverse(td2, &ed->td_list, td_list) {
  800. if (td2->next_dl_td)
  801. break;
  802. td2->next_dl_td = td_prev;
  803. td_prev = td2;
  804. }
  805. if (ohci->dl_end)
  806. ohci->dl_end->next_dl_td = td_prev;
  807. else
  808. ohci->dl_start = td_prev;
  809. /*
  810. * Make td->next_dl_td point to td itself, to mark the fact
  811. * that td is on the done list.
  812. */
  813. ohci->dl_end = td->next_dl_td = td;
  814. /* Did we just add the latest pending TD? */
  815. td2 = ed->pending_td;
  816. if (td2 && td2->next_dl_td)
  817. ed->pending_td = NULL;
  818. }
  819. /* Get the entries on the hardware done queue and put them on our list */
  820. static void update_done_list(struct ohci_hcd *ohci)
  821. {
  822. u32 td_dma;
  823. struct td *td = NULL;
  824. td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
  825. ohci->hcca->done_head = 0;
  826. wmb();
  827. /* get TD from hc's singly linked list, and
  828. * add to ours. ed->td_list changes later.
  829. */
  830. while (td_dma) {
  831. int cc;
  832. td = dma_to_td (ohci, td_dma);
  833. if (!td) {
  834. ohci_err (ohci, "bad entry %8x\n", td_dma);
  835. break;
  836. }
  837. td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
  838. cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
  839. /* Non-iso endpoints can halt on error; un-halt,
  840. * and dequeue any other TDs from this urb.
  841. * No other TD could have caused the halt.
  842. */
  843. if (cc != TD_CC_NOERROR
  844. && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
  845. ed_halted(ohci, td, cc);
  846. td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
  847. add_to_done_list(ohci, td);
  848. }
  849. }
  850. /*-------------------------------------------------------------------------*/
  851. /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
  852. static void finish_unlinks(struct ohci_hcd *ohci)
  853. {
  854. unsigned tick = ohci_frame_no(ohci);
  855. struct ed *ed, **last;
  856. rescan_all:
  857. for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
  858. struct list_head *entry, *tmp;
  859. int completed, modified;
  860. __hc32 *prev;
  861. /* only take off EDs that the HC isn't using, accounting for
  862. * frame counter wraps and EDs with partially retired TDs
  863. */
  864. if (likely(ohci->rh_state == OHCI_RH_RUNNING) &&
  865. tick_before(tick, ed->tick)) {
  866. skip_ed:
  867. last = &ed->ed_next;
  868. continue;
  869. }
  870. if (!list_empty(&ed->td_list)) {
  871. struct td *td;
  872. u32 head;
  873. td = list_first_entry(&ed->td_list, struct td, td_list);
  874. /* INTR_WDH may need to clean up first */
  875. head = hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK;
  876. if (td->td_dma != head &&
  877. ohci->rh_state == OHCI_RH_RUNNING)
  878. goto skip_ed;
  879. /* Don't mess up anything already on the done list */
  880. if (td->next_dl_td)
  881. goto skip_ed;
  882. }
  883. /* ED's now officially unlinked, hc doesn't see */
  884. ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
  885. ed->hwNextED = 0;
  886. wmb();
  887. ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE);
  888. /* reentrancy: if we drop the schedule lock, someone might
  889. * have modified this list. normally it's just prepending
  890. * entries (which we'd ignore), but paranoia won't hurt.
  891. */
  892. *last = ed->ed_next;
  893. ed->ed_next = NULL;
  894. modified = 0;
  895. /* unlink urbs as requested, but rescan the list after
  896. * we call a completion since it might have unlinked
  897. * another (earlier) urb
  898. *
  899. * When we get here, the HC doesn't see this ed. But it
  900. * must not be rescheduled until all completed URBs have
  901. * been given back to the driver.
  902. */
  903. rescan_this:
  904. completed = 0;
  905. prev = &ed->hwHeadP;
  906. list_for_each_safe (entry, tmp, &ed->td_list) {
  907. struct td *td;
  908. struct urb *urb;
  909. urb_priv_t *urb_priv;
  910. __hc32 savebits;
  911. u32 tdINFO;
  912. td = list_entry (entry, struct td, td_list);
  913. urb = td->urb;
  914. urb_priv = td->urb->hcpriv;
  915. if (!urb->unlinked) {
  916. prev = &td->hwNextTD;
  917. continue;
  918. }
  919. /* patch pointer hc uses */
  920. savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
  921. *prev = td->hwNextTD | savebits;
  922. /* If this was unlinked, the TD may not have been
  923. * retired ... so manually save the data toggle.
  924. * The controller ignores the value we save for
  925. * control and ISO endpoints.
  926. */
  927. tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
  928. if ((tdINFO & TD_T) == TD_T_DATA0)
  929. ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
  930. else if ((tdINFO & TD_T) == TD_T_DATA1)
  931. ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
  932. /* HC may have partly processed this TD */
  933. td_done (ohci, urb, td);
  934. urb_priv->td_cnt++;
  935. /* if URB is done, clean up */
  936. if (urb_priv->td_cnt >= urb_priv->length) {
  937. modified = completed = 1;
  938. finish_urb(ohci, urb, 0);
  939. }
  940. }
  941. if (completed && !list_empty (&ed->td_list))
  942. goto rescan_this;
  943. /*
  944. * If no TDs are queued, ED is now idle.
  945. * Otherwise, if the HC is running, reschedule.
  946. * If the HC isn't running, add ED back to the
  947. * start of the list for later processing.
  948. */
  949. if (list_empty(&ed->td_list)) {
  950. ed->state = ED_IDLE;
  951. list_del(&ed->in_use_list);
  952. } else if (ohci->rh_state == OHCI_RH_RUNNING) {
  953. ed_schedule(ohci, ed);
  954. } else {
  955. ed->ed_next = ohci->ed_rm_list;
  956. ohci->ed_rm_list = ed;
  957. /* Don't loop on the same ED */
  958. if (last == &ohci->ed_rm_list)
  959. last = &ed->ed_next;
  960. }
  961. if (modified)
  962. goto rescan_all;
  963. }
  964. /* maybe reenable control and bulk lists */
  965. if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
  966. u32 command = 0, control = 0;
  967. if (ohci->ed_controltail) {
  968. command |= OHCI_CLF;
  969. if (quirk_zfmicro(ohci))
  970. mdelay(1);
  971. if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
  972. control |= OHCI_CTRL_CLE;
  973. ohci_writel (ohci, 0,
  974. &ohci->regs->ed_controlcurrent);
  975. }
  976. }
  977. if (ohci->ed_bulktail) {
  978. command |= OHCI_BLF;
  979. if (quirk_zfmicro(ohci))
  980. mdelay(1);
  981. if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
  982. control |= OHCI_CTRL_BLE;
  983. ohci_writel (ohci, 0,
  984. &ohci->regs->ed_bulkcurrent);
  985. }
  986. }
  987. /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
  988. if (control) {
  989. ohci->hc_control |= control;
  990. if (quirk_zfmicro(ohci))
  991. mdelay(1);
  992. ohci_writel (ohci, ohci->hc_control,
  993. &ohci->regs->control);
  994. }
  995. if (command) {
  996. if (quirk_zfmicro(ohci))
  997. mdelay(1);
  998. ohci_writel (ohci, command, &ohci->regs->cmdstatus);
  999. }
  1000. }
  1001. }
  1002. /*-------------------------------------------------------------------------*/
  1003. /* Take back a TD from the host controller */
  1004. static void takeback_td(struct ohci_hcd *ohci, struct td *td)
  1005. {
  1006. struct urb *urb = td->urb;
  1007. urb_priv_t *urb_priv = urb->hcpriv;
  1008. struct ed *ed = td->ed;
  1009. int status;
  1010. /* update URB's length and status from TD */
  1011. status = td_done(ohci, urb, td);
  1012. urb_priv->td_cnt++;
  1013. /* If all this urb's TDs are done, call complete() */
  1014. if (urb_priv->td_cnt >= urb_priv->length)
  1015. finish_urb(ohci, urb, status);
  1016. /* clean schedule: unlink EDs that are no longer busy */
  1017. if (list_empty(&ed->td_list)) {
  1018. if (ed->state == ED_OPER)
  1019. start_ed_unlink(ohci, ed);
  1020. /* ... reenabling halted EDs only after fault cleanup */
  1021. } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
  1022. == cpu_to_hc32(ohci, ED_SKIP)) {
  1023. td = list_entry(ed->td_list.next, struct td, td_list);
  1024. if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
  1025. ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
  1026. /* ... hc may need waking-up */
  1027. switch (ed->type) {
  1028. case PIPE_CONTROL:
  1029. ohci_writel(ohci, OHCI_CLF,
  1030. &ohci->regs->cmdstatus);
  1031. break;
  1032. case PIPE_BULK:
  1033. ohci_writel(ohci, OHCI_BLF,
  1034. &ohci->regs->cmdstatus);
  1035. break;
  1036. }
  1037. }
  1038. }
  1039. }
  1040. /*
  1041. * Process normal completions (error or success) and clean the schedules.
  1042. *
  1043. * This is the main path for handing urbs back to drivers. The only other
  1044. * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
  1045. * instead of scanning the (re-reversed) donelist as this does.
  1046. */
  1047. static void process_done_list(struct ohci_hcd *ohci)
  1048. {
  1049. struct td *td;
  1050. while (ohci->dl_start) {
  1051. td = ohci->dl_start;
  1052. if (td == ohci->dl_end)
  1053. ohci->dl_start = ohci->dl_end = NULL;
  1054. else
  1055. ohci->dl_start = td->next_dl_td;
  1056. takeback_td(ohci, td);
  1057. }
  1058. }
  1059. /*
  1060. * TD takeback and URB giveback must be single-threaded.
  1061. * This routine takes care of it all.
  1062. */
  1063. static void ohci_work(struct ohci_hcd *ohci)
  1064. {
  1065. if (ohci->working) {
  1066. ohci->restart_work = 1;
  1067. return;
  1068. }
  1069. ohci->working = 1;
  1070. restart:
  1071. process_done_list(ohci);
  1072. if (ohci->ed_rm_list)
  1073. finish_unlinks(ohci);
  1074. if (ohci->restart_work) {
  1075. ohci->restart_work = 0;
  1076. goto restart;
  1077. }
  1078. ohci->working = 0;
  1079. }