ohci-pxa27x.c 17 KB

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  1. // SPDX-License-Identifier: GPL-1.0+
  2. /*
  3. * OHCI HCD (Host Controller Driver) for USB.
  4. *
  5. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  6. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  7. * (C) Copyright 2002 Hewlett-Packard Company
  8. *
  9. * Bus Glue for pxa27x
  10. *
  11. * Written by Christopher Hoover <ch@hpl.hp.com>
  12. * Based on fragments of previous driver by Russell King et al.
  13. *
  14. * Modified for LH7A404 from ohci-sa1111.c
  15. * by Durgesh Pattamatta <pattamattad@sharpsec.com>
  16. *
  17. * Modified for pxa27x from ohci-lh7a404.c
  18. * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
  19. *
  20. * This file is licenced under the GPL.
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/device.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/io.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/of_platform.h>
  29. #include <linux/of_gpio.h>
  30. #include <linux/platform_data/usb-ohci-pxa27x.h>
  31. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/regulator/consumer.h>
  34. #include <linux/signal.h>
  35. #include <linux/usb.h>
  36. #include <linux/usb/hcd.h>
  37. #include <linux/usb/otg.h>
  38. #include <mach/hardware.h>
  39. #include "ohci.h"
  40. #define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
  41. /*
  42. * UHC: USB Host Controller (OHCI-like) register definitions
  43. */
  44. #define UHCREV (0x0000) /* UHC HCI Spec Revision */
  45. #define UHCHCON (0x0004) /* UHC Host Control Register */
  46. #define UHCCOMS (0x0008) /* UHC Command Status Register */
  47. #define UHCINTS (0x000C) /* UHC Interrupt Status Register */
  48. #define UHCINTE (0x0010) /* UHC Interrupt Enable */
  49. #define UHCINTD (0x0014) /* UHC Interrupt Disable */
  50. #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
  51. #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
  52. #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
  53. #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
  54. #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
  55. #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
  56. #define UHCDHEAD (0x0030) /* UHC Done Head */
  57. #define UHCFMI (0x0034) /* UHC Frame Interval */
  58. #define UHCFMR (0x0038) /* UHC Frame Remaining */
  59. #define UHCFMN (0x003C) /* UHC Frame Number */
  60. #define UHCPERS (0x0040) /* UHC Periodic Start */
  61. #define UHCLS (0x0044) /* UHC Low Speed Threshold */
  62. #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
  63. #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
  64. #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
  65. #define UHCRHDA_POTPGT(x) \
  66. (((x) & 0xff) << 24) /* Power On To Power Good Time */
  67. #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
  68. #define UHCRHS (0x0050) /* UHC Root Hub Status */
  69. #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
  70. #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
  71. #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
  72. #define UHCSTAT (0x0060) /* UHC Status Register */
  73. #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
  74. #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
  75. #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
  76. #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
  77. #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
  78. #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
  79. #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
  80. #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
  81. #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
  82. #define UHCHR (0x0064) /* UHC Reset Register */
  83. #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
  84. #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
  85. #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
  86. #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
  87. #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
  88. #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
  89. #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
  90. #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
  91. #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
  92. #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
  93. #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
  94. #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
  95. #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
  96. #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
  97. #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
  98. #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
  99. #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
  100. Interrupt Enable*/
  101. #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
  102. #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
  103. #define UHCHIT (0x006C) /* UHC Interrupt Test register */
  104. #define PXA_UHC_MAX_PORTNUM 3
  105. static const char hcd_name[] = "ohci-pxa27x";
  106. static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
  107. struct pxa27x_ohci {
  108. struct clk *clk;
  109. void __iomem *mmio_base;
  110. struct regulator *vbus[3];
  111. bool vbus_enabled[3];
  112. };
  113. #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
  114. /*
  115. PMM_NPS_MODE -- PMM Non-power switching mode
  116. Ports are powered continuously.
  117. PMM_GLOBAL_MODE -- PMM global switching mode
  118. All ports are powered at the same time.
  119. PMM_PERPORT_MODE -- PMM per port switching mode
  120. Ports are powered individually.
  121. */
  122. static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
  123. {
  124. uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
  125. uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
  126. switch (mode) {
  127. case PMM_NPS_MODE:
  128. uhcrhda |= RH_A_NPS;
  129. break;
  130. case PMM_GLOBAL_MODE:
  131. uhcrhda &= ~(RH_A_NPS | RH_A_PSM);
  132. break;
  133. case PMM_PERPORT_MODE:
  134. uhcrhda &= ~(RH_A_NPS);
  135. uhcrhda |= RH_A_PSM;
  136. /* Set port power control mask bits, only 3 ports. */
  137. uhcrhdb |= (0x7<<17);
  138. break;
  139. default:
  140. printk( KERN_ERR
  141. "Invalid mode %d, set to non-power switch mode.\n",
  142. mode );
  143. uhcrhda |= RH_A_NPS;
  144. }
  145. __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
  146. __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
  147. return 0;
  148. }
  149. static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
  150. unsigned int port, bool enable)
  151. {
  152. struct regulator *vbus = pxa_ohci->vbus[port];
  153. int ret = 0;
  154. if (IS_ERR_OR_NULL(vbus))
  155. return 0;
  156. if (enable && !pxa_ohci->vbus_enabled[port])
  157. ret = regulator_enable(vbus);
  158. else if (!enable && pxa_ohci->vbus_enabled[port])
  159. ret = regulator_disable(vbus);
  160. if (ret < 0)
  161. return ret;
  162. pxa_ohci->vbus_enabled[port] = enable;
  163. return 0;
  164. }
  165. static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  166. u16 wIndex, char *buf, u16 wLength)
  167. {
  168. struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
  169. int ret;
  170. switch (typeReq) {
  171. case SetPortFeature:
  172. case ClearPortFeature:
  173. if (!wIndex || wIndex > 3)
  174. return -EPIPE;
  175. if (wValue != USB_PORT_FEAT_POWER)
  176. break;
  177. ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
  178. typeReq == SetPortFeature);
  179. if (ret)
  180. return ret;
  181. break;
  182. }
  183. return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
  184. }
  185. /*-------------------------------------------------------------------------*/
  186. static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
  187. struct pxaohci_platform_data *inf)
  188. {
  189. uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
  190. uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
  191. if (inf->flags & ENABLE_PORT1)
  192. uhchr &= ~UHCHR_SSEP1;
  193. if (inf->flags & ENABLE_PORT2)
  194. uhchr &= ~UHCHR_SSEP2;
  195. if (inf->flags & ENABLE_PORT3)
  196. uhchr &= ~UHCHR_SSEP3;
  197. if (inf->flags & POWER_CONTROL_LOW)
  198. uhchr |= UHCHR_PCPL;
  199. if (inf->flags & POWER_SENSE_LOW)
  200. uhchr |= UHCHR_PSPL;
  201. if (inf->flags & NO_OC_PROTECTION)
  202. uhcrhda |= UHCRHDA_NOCP;
  203. else
  204. uhcrhda &= ~UHCRHDA_NOCP;
  205. if (inf->flags & OC_MODE_PERPORT)
  206. uhcrhda |= UHCRHDA_OCPM;
  207. else
  208. uhcrhda &= ~UHCRHDA_OCPM;
  209. if (inf->power_on_delay) {
  210. uhcrhda &= ~UHCRHDA_POTPGT(0xff);
  211. uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
  212. }
  213. __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
  214. __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
  215. }
  216. static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
  217. {
  218. uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
  219. __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
  220. udelay(11);
  221. __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
  222. }
  223. #ifdef CONFIG_PXA27x
  224. extern void pxa27x_clear_otgph(void);
  225. #else
  226. #define pxa27x_clear_otgph() do {} while (0)
  227. #endif
  228. static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
  229. {
  230. int retval;
  231. struct pxaohci_platform_data *inf;
  232. uint32_t uhchr;
  233. struct usb_hcd *hcd = dev_get_drvdata(dev);
  234. inf = dev_get_platdata(dev);
  235. retval = clk_prepare_enable(pxa_ohci->clk);
  236. if (retval)
  237. return retval;
  238. pxa27x_reset_hc(pxa_ohci);
  239. uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
  240. __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
  241. while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
  242. cpu_relax();
  243. pxa27x_setup_hc(pxa_ohci, inf);
  244. if (inf->init)
  245. retval = inf->init(dev);
  246. if (retval < 0) {
  247. clk_disable_unprepare(pxa_ohci->clk);
  248. return retval;
  249. }
  250. if (cpu_is_pxa3xx())
  251. pxa3xx_u2d_start_hc(&hcd->self);
  252. uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
  253. __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
  254. __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
  255. /* Clear any OTG Pin Hold */
  256. pxa27x_clear_otgph();
  257. return 0;
  258. }
  259. static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
  260. {
  261. struct pxaohci_platform_data *inf;
  262. struct usb_hcd *hcd = dev_get_drvdata(dev);
  263. uint32_t uhccoms;
  264. inf = dev_get_platdata(dev);
  265. if (cpu_is_pxa3xx())
  266. pxa3xx_u2d_stop_hc(&hcd->self);
  267. if (inf->exit)
  268. inf->exit(dev);
  269. pxa27x_reset_hc(pxa_ohci);
  270. /* Host Controller Reset */
  271. uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
  272. __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
  273. udelay(10);
  274. clk_disable_unprepare(pxa_ohci->clk);
  275. }
  276. #ifdef CONFIG_OF
  277. static const struct of_device_id pxa_ohci_dt_ids[] = {
  278. { .compatible = "marvell,pxa-ohci" },
  279. { }
  280. };
  281. MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
  282. static int ohci_pxa_of_init(struct platform_device *pdev)
  283. {
  284. struct device_node *np = pdev->dev.of_node;
  285. struct pxaohci_platform_data *pdata;
  286. u32 tmp;
  287. int ret;
  288. if (!np)
  289. return 0;
  290. /* Right now device-tree probed devices don't get dma_mask set.
  291. * Since shared usb code relies on it, set it here for now.
  292. * Once we have dma capability bindings this can go away.
  293. */
  294. ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  295. if (ret)
  296. return ret;
  297. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  298. if (!pdata)
  299. return -ENOMEM;
  300. if (of_property_read_bool(np, "marvell,enable-port1"))
  301. pdata->flags |= ENABLE_PORT1;
  302. if (of_property_read_bool(np, "marvell,enable-port2"))
  303. pdata->flags |= ENABLE_PORT2;
  304. if (of_property_read_bool(np, "marvell,enable-port3"))
  305. pdata->flags |= ENABLE_PORT3;
  306. if (of_property_read_bool(np, "marvell,port-sense-low"))
  307. pdata->flags |= POWER_SENSE_LOW;
  308. if (of_property_read_bool(np, "marvell,power-control-low"))
  309. pdata->flags |= POWER_CONTROL_LOW;
  310. if (of_property_read_bool(np, "marvell,no-oc-protection"))
  311. pdata->flags |= NO_OC_PROTECTION;
  312. if (of_property_read_bool(np, "marvell,oc-mode-perport"))
  313. pdata->flags |= OC_MODE_PERPORT;
  314. if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
  315. pdata->power_on_delay = tmp;
  316. if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
  317. pdata->port_mode = tmp;
  318. if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
  319. pdata->power_budget = tmp;
  320. pdev->dev.platform_data = pdata;
  321. return 0;
  322. }
  323. #else
  324. static int ohci_pxa_of_init(struct platform_device *pdev)
  325. {
  326. return 0;
  327. }
  328. #endif
  329. /*-------------------------------------------------------------------------*/
  330. /* configure so an HC device and id are always provided */
  331. /* always called with process context; sleeping is OK */
  332. /**
  333. * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs
  334. * Context: !in_interrupt()
  335. *
  336. * Allocates basic resources for this USB host controller, and
  337. * then invokes the start() method for the HCD associated with it
  338. * through the hotplug entry's driver_data.
  339. *
  340. */
  341. static int ohci_hcd_pxa27x_probe(struct platform_device *pdev)
  342. {
  343. int retval, irq;
  344. struct usb_hcd *hcd;
  345. struct pxaohci_platform_data *inf;
  346. struct pxa27x_ohci *pxa_ohci;
  347. struct ohci_hcd *ohci;
  348. struct resource *r;
  349. struct clk *usb_clk;
  350. unsigned int i;
  351. retval = ohci_pxa_of_init(pdev);
  352. if (retval)
  353. return retval;
  354. inf = dev_get_platdata(&pdev->dev);
  355. if (!inf)
  356. return -ENODEV;
  357. irq = platform_get_irq(pdev, 0);
  358. if (irq < 0) {
  359. pr_err("no resource of IORESOURCE_IRQ");
  360. return irq;
  361. }
  362. usb_clk = devm_clk_get(&pdev->dev, NULL);
  363. if (IS_ERR(usb_clk))
  364. return PTR_ERR(usb_clk);
  365. hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x");
  366. if (!hcd)
  367. return -ENOMEM;
  368. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  369. hcd->regs = devm_ioremap_resource(&pdev->dev, r);
  370. if (IS_ERR(hcd->regs)) {
  371. retval = PTR_ERR(hcd->regs);
  372. goto err;
  373. }
  374. hcd->rsrc_start = r->start;
  375. hcd->rsrc_len = resource_size(r);
  376. /* initialize "struct pxa27x_ohci" */
  377. pxa_ohci = to_pxa27x_ohci(hcd);
  378. pxa_ohci->clk = usb_clk;
  379. pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
  380. for (i = 0; i < 3; ++i) {
  381. char name[6];
  382. if (!(inf->flags & (ENABLE_PORT1 << i)))
  383. continue;
  384. sprintf(name, "vbus%u", i + 1);
  385. pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
  386. }
  387. retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
  388. if (retval < 0) {
  389. pr_debug("pxa27x_start_hc failed");
  390. goto err;
  391. }
  392. /* Select Power Management Mode */
  393. pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
  394. if (inf->power_budget)
  395. hcd->power_budget = inf->power_budget;
  396. /* The value of NDP in roothub_a is incorrect on this hardware */
  397. ohci = hcd_to_ohci(hcd);
  398. ohci->num_ports = 3;
  399. retval = usb_add_hcd(hcd, irq, 0);
  400. if (retval == 0) {
  401. device_wakeup_enable(hcd->self.controller);
  402. return retval;
  403. }
  404. pxa27x_stop_hc(pxa_ohci, &pdev->dev);
  405. err:
  406. usb_put_hcd(hcd);
  407. return retval;
  408. }
  409. /* may be called without controller electrically present */
  410. /* may be called with controller, bus, and devices active */
  411. /**
  412. * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
  413. * @dev: USB Host Controller being removed
  414. * Context: !in_interrupt()
  415. *
  416. * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking
  417. * the HCD's stop() method. It is always called from a thread
  418. * context, normally "rmmod", "apmd", or something similar.
  419. *
  420. */
  421. static int ohci_hcd_pxa27x_remove(struct platform_device *pdev)
  422. {
  423. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  424. struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
  425. unsigned int i;
  426. usb_remove_hcd(hcd);
  427. pxa27x_stop_hc(pxa_ohci, &pdev->dev);
  428. for (i = 0; i < 3; ++i)
  429. pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
  430. usb_put_hcd(hcd);
  431. return 0;
  432. }
  433. /*-------------------------------------------------------------------------*/
  434. #ifdef CONFIG_PM
  435. static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
  436. {
  437. struct usb_hcd *hcd = dev_get_drvdata(dev);
  438. struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
  439. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  440. bool do_wakeup = device_may_wakeup(dev);
  441. int ret;
  442. if (time_before(jiffies, ohci->next_statechange))
  443. msleep(5);
  444. ohci->next_statechange = jiffies;
  445. ret = ohci_suspend(hcd, do_wakeup);
  446. if (ret)
  447. return ret;
  448. pxa27x_stop_hc(pxa_ohci, dev);
  449. return ret;
  450. }
  451. static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
  452. {
  453. struct usb_hcd *hcd = dev_get_drvdata(dev);
  454. struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
  455. struct pxaohci_platform_data *inf = dev_get_platdata(dev);
  456. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  457. int status;
  458. if (time_before(jiffies, ohci->next_statechange))
  459. msleep(5);
  460. ohci->next_statechange = jiffies;
  461. status = pxa27x_start_hc(pxa_ohci, dev);
  462. if (status < 0)
  463. return status;
  464. /* Select Power Management Mode */
  465. pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
  466. ohci_resume(hcd, false);
  467. return 0;
  468. }
  469. static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
  470. .suspend = ohci_hcd_pxa27x_drv_suspend,
  471. .resume = ohci_hcd_pxa27x_drv_resume,
  472. };
  473. #endif
  474. static struct platform_driver ohci_hcd_pxa27x_driver = {
  475. .probe = ohci_hcd_pxa27x_probe,
  476. .remove = ohci_hcd_pxa27x_remove,
  477. .shutdown = usb_hcd_platform_shutdown,
  478. .driver = {
  479. .name = "pxa27x-ohci",
  480. .of_match_table = of_match_ptr(pxa_ohci_dt_ids),
  481. #ifdef CONFIG_PM
  482. .pm = &ohci_hcd_pxa27x_pm_ops,
  483. #endif
  484. },
  485. };
  486. static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
  487. .extra_priv_size = sizeof(struct pxa27x_ohci),
  488. };
  489. static int __init ohci_pxa27x_init(void)
  490. {
  491. if (usb_disabled())
  492. return -ENODEV;
  493. pr_info("%s: " DRIVER_DESC "\n", hcd_name);
  494. ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
  495. ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
  496. return platform_driver_register(&ohci_hcd_pxa27x_driver);
  497. }
  498. module_init(ohci_pxa27x_init);
  499. static void __exit ohci_pxa27x_cleanup(void)
  500. {
  501. platform_driver_unregister(&ohci_hcd_pxa27x_driver);
  502. }
  503. module_exit(ohci_pxa27x_cleanup);
  504. MODULE_DESCRIPTION(DRIVER_DESC);
  505. MODULE_LICENSE("GPL");
  506. MODULE_ALIAS("platform:pxa27x-ohci");