isp1362.h 30 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * ISP1362 HCD (Host Controller Driver) for USB.
  4. *
  5. * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de>
  6. */
  7. /* ------------------------------------------------------------------------- */
  8. #define MAX_ROOT_PORTS 2
  9. #define USE_32BIT 0
  10. /* These options are mutually exclusive */
  11. #define USE_PLATFORM_DELAY 0
  12. #define USE_NDELAY 0
  13. #define DUMMY_DELAY_ACCESS do {} while (0)
  14. /* ------------------------------------------------------------------------- */
  15. #define USB_RESET_WIDTH 50
  16. #define MAX_XFER_SIZE 1023
  17. /* Buffer sizes */
  18. #define ISP1362_BUF_SIZE 4096
  19. #define ISP1362_ISTL_BUFSIZE 512
  20. #define ISP1362_INTL_BLKSIZE 64
  21. #define ISP1362_INTL_BUFFERS 16
  22. #define ISP1362_ATL_BLKSIZE 64
  23. #define ISP1362_REG_WRITE_OFFSET 0x80
  24. #define REG_WIDTH_16 0x000
  25. #define REG_WIDTH_32 0x100
  26. #define REG_WIDTH_MASK 0x100
  27. #define REG_NO_MASK 0x0ff
  28. #ifdef ISP1362_DEBUG
  29. typedef const unsigned int isp1362_reg_t;
  30. #define REG_ACCESS_R 0x200
  31. #define REG_ACCESS_W 0x400
  32. #define REG_ACCESS_RW 0x600
  33. #define REG_ACCESS_MASK 0x600
  34. #define ISP1362_REG_NO(r) ((r) & REG_NO_MASK)
  35. #define ISP1362_REG(name, addr, width, rw) \
  36. static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw))
  37. #define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W))
  38. #define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w))
  39. #else
  40. typedef const unsigned char isp1362_reg_t;
  41. #define ISP1362_REG_NO(r) (r)
  42. #define ISP1362_REG(name, addr, width, rw) \
  43. static isp1362_reg_t __maybe_unused ISP1362_REG_##name = addr
  44. #define REG_ACCESS_TEST(r) do {} while (0)
  45. #define REG_WIDTH_TEST(r, w) do {} while (0)
  46. #endif
  47. /* OHCI compatible registers */
  48. /*
  49. * Note: Some of the ISP1362 'OHCI' registers implement only
  50. * a subset of the bits defined in the OHCI spec.
  51. *
  52. * Bitmasks for the individual bits of these registers are defined in "ohci.h"
  53. */
  54. ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R);
  55. ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW);
  56. ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW);
  57. ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW);
  58. ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW);
  59. ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW);
  60. ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW);
  61. ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW);
  62. ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW);
  63. ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW);
  64. ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW);
  65. ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW);
  66. ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW);
  67. ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW);
  68. ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW);
  69. /* Philips ISP1362 specific registers */
  70. ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW);
  71. #define HCHWCFG_DISABLE_SUSPEND (1 << 15)
  72. #define HCHWCFG_GLOBAL_PWRDOWN (1 << 14)
  73. #define HCHWCFG_PULLDOWN_DS2 (1 << 13)
  74. #define HCHWCFG_PULLDOWN_DS1 (1 << 12)
  75. #define HCHWCFG_CLKNOTSTOP (1 << 11)
  76. #define HCHWCFG_ANALOG_OC (1 << 10)
  77. #define HCHWCFG_ONEINT (1 << 9)
  78. #define HCHWCFG_DACK_MODE (1 << 8)
  79. #define HCHWCFG_ONEDMA (1 << 7)
  80. #define HCHWCFG_DACK_POL (1 << 6)
  81. #define HCHWCFG_DREQ_POL (1 << 5)
  82. #define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
  83. #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
  84. #define HCHWCFG_INT_POL (1 << 2)
  85. #define HCHWCFG_INT_TRIGGER (1 << 1)
  86. #define HCHWCFG_INT_ENABLE (1 << 0)
  87. ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW);
  88. #define HCDMACFG_CTR_ENABLE (1 << 7)
  89. #define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
  90. #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
  91. #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
  92. #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
  93. #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
  94. #define HCDMACFG_DMA_ENABLE (1 << 4)
  95. #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
  96. #define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK)
  97. #define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0)
  98. #define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1)
  99. #define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2)
  100. #define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3)
  101. #define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4)
  102. #define HCDMACFG_DMA_RW_SELECT (1 << 0)
  103. ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW);
  104. ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW);
  105. #define HCuPINT_SOF (1 << 0)
  106. #define HCuPINT_ISTL0 (1 << 1)
  107. #define HCuPINT_ISTL1 (1 << 2)
  108. #define HCuPINT_EOT (1 << 3)
  109. #define HCuPINT_OPR (1 << 4)
  110. #define HCuPINT_SUSP (1 << 5)
  111. #define HCuPINT_CLKRDY (1 << 6)
  112. #define HCuPINT_INTL (1 << 7)
  113. #define HCuPINT_ATL (1 << 8)
  114. #define HCuPINT_OTG (1 << 9)
  115. ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW);
  116. /* same bit definitions apply as for HCuPINT */
  117. ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R);
  118. #define HCCHIPID_MASK 0xff00
  119. #define HCCHIPID_MAGIC 0x3600
  120. ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW);
  121. ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W);
  122. #define HCSWRES_MAGIC 0x00f6
  123. ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW);
  124. #define HCBUFSTAT_ISTL0_FULL (1 << 0)
  125. #define HCBUFSTAT_ISTL1_FULL (1 << 1)
  126. #define HCBUFSTAT_INTL_ACTIVE (1 << 2)
  127. #define HCBUFSTAT_ATL_ACTIVE (1 << 3)
  128. #define HCBUFSTAT_RESET_HWPP (1 << 4)
  129. #define HCBUFSTAT_ISTL0_ACTIVE (1 << 5)
  130. #define HCBUFSTAT_ISTL1_ACTIVE (1 << 6)
  131. #define HCBUFSTAT_ISTL0_DONE (1 << 8)
  132. #define HCBUFSTAT_ISTL1_DONE (1 << 9)
  133. #define HCBUFSTAT_PAIRED_PTDPP (1 << 10)
  134. ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW);
  135. #define HCDIRADDR_ADDR_MASK 0x0000ffff
  136. #define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK)
  137. #define HCDIRADDR_COUNT_MASK 0xffff0000
  138. #define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK)
  139. ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW);
  140. ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW);
  141. ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW);
  142. ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW);
  143. ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW);
  144. ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW);
  145. ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW);
  146. ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW);
  147. ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R);
  148. ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW);
  149. ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW);
  150. ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R);
  151. ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW);
  152. ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW);
  153. ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW);
  154. ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R);
  155. ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW);
  156. ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW);
  157. ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R);
  158. ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW);
  159. ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW);
  160. ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW);
  161. ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R);
  162. ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW);
  163. ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW);
  164. ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW);
  165. ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW);
  166. /* Philips transfer descriptor, cpu-endian */
  167. struct ptd {
  168. u16 count;
  169. #define PTD_COUNT_MSK (0x3ff << 0)
  170. #define PTD_TOGGLE_MSK (1 << 10)
  171. #define PTD_ACTIVE_MSK (1 << 11)
  172. #define PTD_CC_MSK (0xf << 12)
  173. u16 mps;
  174. #define PTD_MPS_MSK (0x3ff << 0)
  175. #define PTD_SPD_MSK (1 << 10)
  176. #define PTD_LAST_MSK (1 << 11)
  177. #define PTD_EP_MSK (0xf << 12)
  178. u16 len;
  179. #define PTD_LEN_MSK (0x3ff << 0)
  180. #define PTD_DIR_MSK (3 << 10)
  181. #define PTD_DIR_SETUP (0)
  182. #define PTD_DIR_OUT (1)
  183. #define PTD_DIR_IN (2)
  184. u16 faddr;
  185. #define PTD_FA_MSK (0x7f << 0)
  186. /* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */
  187. #define PTD_SF_ISO_MSK (0xff << 8)
  188. #define PTD_SF_INT_MSK (0x1f << 8)
  189. #define PTD_PR_MSK (0x07 << 13)
  190. } __attribute__ ((packed, aligned(2)));
  191. #define PTD_HEADER_SIZE sizeof(struct ptd)
  192. /* ------------------------------------------------------------------------- */
  193. /* Copied from ohci.h: */
  194. /*
  195. * Hardware transfer status codes -- CC from PTD
  196. */
  197. #define PTD_CC_NOERROR 0x00
  198. #define PTD_CC_CRC 0x01
  199. #define PTD_CC_BITSTUFFING 0x02
  200. #define PTD_CC_DATATOGGLEM 0x03
  201. #define PTD_CC_STALL 0x04
  202. #define PTD_DEVNOTRESP 0x05
  203. #define PTD_PIDCHECKFAIL 0x06
  204. #define PTD_UNEXPECTEDPID 0x07
  205. #define PTD_DATAOVERRUN 0x08
  206. #define PTD_DATAUNDERRUN 0x09
  207. /* 0x0A, 0x0B reserved for hardware */
  208. #define PTD_BUFFEROVERRUN 0x0C
  209. #define PTD_BUFFERUNDERRUN 0x0D
  210. /* 0x0E, 0x0F reserved for HCD */
  211. #define PTD_NOTACCESSED 0x0F
  212. /* map OHCI TD status codes (CC) to errno values */
  213. static const int cc_to_error[16] = {
  214. /* No Error */ 0,
  215. /* CRC Error */ -EILSEQ,
  216. /* Bit Stuff */ -EPROTO,
  217. /* Data Togg */ -EILSEQ,
  218. /* Stall */ -EPIPE,
  219. /* DevNotResp */ -ETIMEDOUT,
  220. /* PIDCheck */ -EPROTO,
  221. /* UnExpPID */ -EPROTO,
  222. /* DataOver */ -EOVERFLOW,
  223. /* DataUnder */ -EREMOTEIO,
  224. /* (for hw) */ -EIO,
  225. /* (for hw) */ -EIO,
  226. /* BufferOver */ -ECOMM,
  227. /* BuffUnder */ -ENOSR,
  228. /* (for HCD) */ -EALREADY,
  229. /* (for HCD) */ -EALREADY
  230. };
  231. /*
  232. * HcControl (control) register masks
  233. */
  234. #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
  235. #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
  236. #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
  237. /* pre-shifted values for HCFS */
  238. # define OHCI_USB_RESET (0 << 6)
  239. # define OHCI_USB_RESUME (1 << 6)
  240. # define OHCI_USB_OPER (2 << 6)
  241. # define OHCI_USB_SUSPEND (3 << 6)
  242. /*
  243. * HcCommandStatus (cmdstatus) register masks
  244. */
  245. #define OHCI_HCR (1 << 0) /* host controller reset */
  246. #define OHCI_SOC (3 << 16) /* scheduling overrun count */
  247. /*
  248. * masks used with interrupt registers:
  249. * HcInterruptStatus (intrstatus)
  250. * HcInterruptEnable (intrenable)
  251. * HcInterruptDisable (intrdisable)
  252. */
  253. #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
  254. #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
  255. #define OHCI_INTR_SF (1 << 2) /* start frame */
  256. #define OHCI_INTR_RD (1 << 3) /* resume detect */
  257. #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
  258. #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
  259. #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
  260. #define OHCI_INTR_OC (1 << 30) /* ownership change */
  261. #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
  262. /* roothub.portstatus [i] bits */
  263. #define RH_PS_CCS 0x00000001 /* current connect status */
  264. #define RH_PS_PES 0x00000002 /* port enable status*/
  265. #define RH_PS_PSS 0x00000004 /* port suspend status */
  266. #define RH_PS_POCI 0x00000008 /* port over current indicator */
  267. #define RH_PS_PRS 0x00000010 /* port reset status */
  268. #define RH_PS_PPS 0x00000100 /* port power status */
  269. #define RH_PS_LSDA 0x00000200 /* low speed device attached */
  270. #define RH_PS_CSC 0x00010000 /* connect status change */
  271. #define RH_PS_PESC 0x00020000 /* port enable status change */
  272. #define RH_PS_PSSC 0x00040000 /* port suspend status change */
  273. #define RH_PS_OCIC 0x00080000 /* over current indicator change */
  274. #define RH_PS_PRSC 0x00100000 /* port reset status change */
  275. /* roothub.status bits */
  276. #define RH_HS_LPS 0x00000001 /* local power status */
  277. #define RH_HS_OCI 0x00000002 /* over current indicator */
  278. #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
  279. #define RH_HS_LPSC 0x00010000 /* local power status change */
  280. #define RH_HS_OCIC 0x00020000 /* over current indicator change */
  281. #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
  282. /* roothub.b masks */
  283. #define RH_B_DR 0x0000ffff /* device removable flags */
  284. #define RH_B_PPCM 0xffff0000 /* port power control mask */
  285. /* roothub.a masks */
  286. #define RH_A_NDP (0xff << 0) /* number of downstream ports */
  287. #define RH_A_PSM (1 << 8) /* power switching mode */
  288. #define RH_A_NPS (1 << 9) /* no power switching */
  289. #define RH_A_DT (1 << 10) /* device type (mbz) */
  290. #define RH_A_OCPM (1 << 11) /* over current protection mode */
  291. #define RH_A_NOCP (1 << 12) /* no over current protection */
  292. #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
  293. #define FI 0x2edf /* 12000 bits per frame (-1) */
  294. #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
  295. #define LSTHRESH 0x628 /* lowspeed bit threshold */
  296. /* ------------------------------------------------------------------------- */
  297. /* PTD accessor macros. */
  298. #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
  299. #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
  300. #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
  301. #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
  302. #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
  303. #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
  304. #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
  305. #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
  306. #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
  307. #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
  308. #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
  309. #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
  310. #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
  311. #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
  312. #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
  313. #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
  314. #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
  315. #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
  316. #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
  317. #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
  318. #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
  319. #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
  320. #define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8)
  321. #define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK)
  322. #define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8)
  323. #define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK)
  324. #define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13)
  325. #define PTD_PR(v) (((v) << 13) & PTD_PR_MSK)
  326. #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
  327. #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
  328. struct isp1362_ep {
  329. struct usb_host_endpoint *hep;
  330. struct usb_device *udev;
  331. /* philips transfer descriptor */
  332. struct ptd ptd;
  333. u8 maxpacket;
  334. u8 epnum;
  335. u8 nextpid;
  336. u16 error_count;
  337. u16 length; /* of current packet */
  338. s16 ptd_offset; /* buffer offset in ISP1362 where
  339. PTD has been stored
  340. (for access thru HCDIRDATA) */
  341. int ptd_index;
  342. int num_ptds;
  343. void *data; /* to databuf */
  344. /* queue of active EPs (the ones transmitted to the chip) */
  345. struct list_head active;
  346. /* periodic schedule */
  347. u8 branch;
  348. u16 interval;
  349. u16 load;
  350. u16 last_iso;
  351. /* async schedule */
  352. struct list_head schedule; /* list of all EPs that need processing */
  353. struct list_head remove_list;
  354. int num_req;
  355. };
  356. struct isp1362_ep_queue {
  357. struct list_head active; /* list of PTDs currently processed by HC */
  358. atomic_t finishing;
  359. unsigned long buf_map;
  360. unsigned long skip_map;
  361. int free_ptd;
  362. u16 buf_start;
  363. u16 buf_size;
  364. u16 blk_size; /* PTD buffer block size for ATL and INTL */
  365. u8 buf_count;
  366. u8 buf_avail;
  367. char name[16];
  368. /* for statistical tracking */
  369. u8 stat_maxptds; /* Max # of ptds seen simultaneously in fifo */
  370. u8 ptd_count; /* number of ptds submitted to this queue */
  371. };
  372. struct isp1362_hcd {
  373. spinlock_t lock;
  374. void __iomem *addr_reg;
  375. void __iomem *data_reg;
  376. struct isp1362_platform_data *board;
  377. struct dentry *debug_file;
  378. unsigned long stat1, stat2, stat4, stat8, stat16;
  379. /* HC registers */
  380. u32 intenb; /* "OHCI" interrupts */
  381. u16 irqenb; /* uP interrupts */
  382. /* Root hub registers */
  383. u32 rhdesca;
  384. u32 rhdescb;
  385. u32 rhstatus;
  386. u32 rhport[MAX_ROOT_PORTS];
  387. unsigned long next_statechange;
  388. /* HC control reg shadow copy */
  389. u32 hc_control;
  390. /* async schedule: control, bulk */
  391. struct list_head async;
  392. /* periodic schedule: int */
  393. u16 load[PERIODIC_SIZE];
  394. struct list_head periodic;
  395. u16 fmindex;
  396. /* periodic schedule: isochronous */
  397. struct list_head isoc;
  398. unsigned int istl_flip:1;
  399. unsigned int irq_active:1;
  400. /* Schedules for the current frame */
  401. struct isp1362_ep_queue atl_queue;
  402. struct isp1362_ep_queue intl_queue;
  403. struct isp1362_ep_queue istl_queue[2];
  404. /* list of PTDs retrieved from HC */
  405. struct list_head remove_list;
  406. enum {
  407. ISP1362_INT_SOF,
  408. ISP1362_INT_ISTL0,
  409. ISP1362_INT_ISTL1,
  410. ISP1362_INT_EOT,
  411. ISP1362_INT_OPR,
  412. ISP1362_INT_SUSP,
  413. ISP1362_INT_CLKRDY,
  414. ISP1362_INT_INTL,
  415. ISP1362_INT_ATL,
  416. ISP1362_INT_OTG,
  417. NUM_ISP1362_IRQS
  418. } IRQ_NAMES;
  419. unsigned int irq_stat[NUM_ISP1362_IRQS];
  420. int req_serial;
  421. };
  422. static inline const char *ISP1362_INT_NAME(int n)
  423. {
  424. switch (n) {
  425. case ISP1362_INT_SOF: return "SOF";
  426. case ISP1362_INT_ISTL0: return "ISTL0";
  427. case ISP1362_INT_ISTL1: return "ISTL1";
  428. case ISP1362_INT_EOT: return "EOT";
  429. case ISP1362_INT_OPR: return "OPR";
  430. case ISP1362_INT_SUSP: return "SUSP";
  431. case ISP1362_INT_CLKRDY: return "CLKRDY";
  432. case ISP1362_INT_INTL: return "INTL";
  433. case ISP1362_INT_ATL: return "ATL";
  434. case ISP1362_INT_OTG: return "OTG";
  435. default: return "unknown";
  436. }
  437. }
  438. static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr)
  439. {
  440. unsigned long p = (unsigned long)ptr;
  441. if (!(p & 0xf))
  442. isp1362_hcd->stat16++;
  443. else if (!(p & 0x7))
  444. isp1362_hcd->stat8++;
  445. else if (!(p & 0x3))
  446. isp1362_hcd->stat4++;
  447. else if (!(p & 0x1))
  448. isp1362_hcd->stat2++;
  449. else
  450. isp1362_hcd->stat1++;
  451. }
  452. static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd)
  453. {
  454. return (struct isp1362_hcd *) (hcd->hcd_priv);
  455. }
  456. static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd)
  457. {
  458. return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv);
  459. }
  460. #define frame_before(f1, f2) ((s16)((u16)f1 - (u16)f2) < 0)
  461. /*
  462. * ISP1362 HW Interface
  463. */
  464. #define DBG(level, fmt...) \
  465. do { \
  466. if (dbg_level > level) \
  467. pr_debug(fmt); \
  468. } while (0)
  469. #ifdef VERBOSE
  470. # define VDBG(fmt...) DBG(3, fmt)
  471. #else
  472. # define VDBG(fmt...) do {} while (0)
  473. #endif
  474. #ifdef REGISTERS
  475. # define RDBG(fmt...) DBG(1, fmt)
  476. #else
  477. # define RDBG(fmt...) do {} while (0)
  478. #endif
  479. #ifdef URB_TRACE
  480. #define URB_DBG(fmt...) DBG(0, fmt)
  481. #else
  482. #define URB_DBG(fmt...) do {} while (0)
  483. #endif
  484. #if USE_PLATFORM_DELAY
  485. #if USE_NDELAY
  486. #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously.
  487. #endif
  488. #define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d)
  489. #elif USE_NDELAY
  490. #define isp1362_delay(h, d) ndelay(d)
  491. #else
  492. #define isp1362_delay(h, d) do {} while (0)
  493. #endif
  494. #define get_urb(ep) ({ \
  495. BUG_ON(list_empty(&ep->hep->urb_list)); \
  496. container_of(ep->hep->urb_list.next, struct urb, urb_list); \
  497. })
  498. /* basic access functions for ISP1362 chip registers */
  499. /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure,
  500. * that all register accesses are performed with interrupts disabled, since the interrupt
  501. * handler has no way of restoring the previous state.
  502. */
  503. static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg)
  504. {
  505. REG_ACCESS_TEST(reg);
  506. DUMMY_DELAY_ACCESS;
  507. writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg);
  508. DUMMY_DELAY_ACCESS;
  509. isp1362_delay(isp1362_hcd, 1);
  510. }
  511. static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val)
  512. {
  513. DUMMY_DELAY_ACCESS;
  514. writew(val, isp1362_hcd->data_reg);
  515. }
  516. static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd)
  517. {
  518. u16 val;
  519. DUMMY_DELAY_ACCESS;
  520. val = readw(isp1362_hcd->data_reg);
  521. return val;
  522. }
  523. static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val)
  524. {
  525. #if USE_32BIT
  526. DUMMY_DELAY_ACCESS;
  527. writel(val, isp1362_hcd->data_reg);
  528. #else
  529. DUMMY_DELAY_ACCESS;
  530. writew((u16)val, isp1362_hcd->data_reg);
  531. DUMMY_DELAY_ACCESS;
  532. writew(val >> 16, isp1362_hcd->data_reg);
  533. #endif
  534. }
  535. static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd)
  536. {
  537. u32 val;
  538. #if USE_32BIT
  539. DUMMY_DELAY_ACCESS;
  540. val = readl(isp1362_hcd->data_reg);
  541. #else
  542. DUMMY_DELAY_ACCESS;
  543. val = (u32)readw(isp1362_hcd->data_reg);
  544. DUMMY_DELAY_ACCESS;
  545. val |= (u32)readw(isp1362_hcd->data_reg) << 16;
  546. #endif
  547. return val;
  548. }
  549. /* use readsw/writesw to access the fifo whenever possible */
  550. /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */
  551. static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
  552. {
  553. u8 *dp = buf;
  554. u16 data;
  555. if (!len)
  556. return;
  557. RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf);
  558. #if USE_32BIT
  559. if (len >= 4) {
  560. RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2);
  561. readsl(isp1362_hcd->data_reg, dp, len >> 2);
  562. dp += len & ~3;
  563. len &= 3;
  564. }
  565. #endif
  566. if (len >= 2) {
  567. RDBG("%s: Using readsw for %d words\n", __func__, len >> 1);
  568. insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
  569. dp += len & ~1;
  570. len &= 1;
  571. }
  572. BUG_ON(len & ~1);
  573. if (len > 0) {
  574. data = isp1362_read_data16(isp1362_hcd);
  575. RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__,
  576. (u8)data, (u32)dp);
  577. *dp = (u8)data;
  578. }
  579. }
  580. static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len)
  581. {
  582. u8 *dp = buf;
  583. u16 data;
  584. if (!len)
  585. return;
  586. if ((unsigned long)dp & 0x1) {
  587. /* not aligned */
  588. for (; len > 1; len -= 2) {
  589. data = *dp++;
  590. data |= *dp++ << 8;
  591. isp1362_write_data16(isp1362_hcd, data);
  592. }
  593. if (len)
  594. isp1362_write_data16(isp1362_hcd, *dp);
  595. return;
  596. }
  597. RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf);
  598. #if USE_32BIT
  599. if (len >= 4) {
  600. RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2);
  601. writesl(isp1362_hcd->data_reg, dp, len >> 2);
  602. dp += len & ~3;
  603. len &= 3;
  604. }
  605. #endif
  606. if (len >= 2) {
  607. RDBG("%s: Using writesw for %d words\n", __func__, len >> 1);
  608. outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1);
  609. dp += len & ~1;
  610. len &= 1;
  611. }
  612. BUG_ON(len & ~1);
  613. if (len > 0) {
  614. /* finally write any trailing byte; we don't need to care
  615. * about the high byte of the last word written
  616. */
  617. data = (u16)*dp;
  618. RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__,
  619. data, (u32)dp);
  620. isp1362_write_data16(isp1362_hcd, data);
  621. }
  622. }
  623. #define isp1362_read_reg16(d, r) ({ \
  624. u16 __v; \
  625. REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \
  626. isp1362_write_addr(d, ISP1362_REG_##r); \
  627. __v = isp1362_read_data16(d); \
  628. RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r, \
  629. ISP1362_REG_NO(ISP1362_REG_##r)); \
  630. __v; \
  631. })
  632. #define isp1362_read_reg32(d, r) ({ \
  633. u32 __v; \
  634. REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \
  635. isp1362_write_addr(d, ISP1362_REG_##r); \
  636. __v = isp1362_read_data32(d); \
  637. RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r, \
  638. ISP1362_REG_NO(ISP1362_REG_##r)); \
  639. __v; \
  640. })
  641. #define isp1362_write_reg16(d, r, v) { \
  642. REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \
  643. isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \
  644. isp1362_write_data16(d, (u16)(v)); \
  645. RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r, \
  646. ISP1362_REG_NO(ISP1362_REG_##r)); \
  647. }
  648. #define isp1362_write_reg32(d, r, v) { \
  649. REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \
  650. isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \
  651. isp1362_write_data32(d, (u32)(v)); \
  652. RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r, \
  653. ISP1362_REG_NO(ISP1362_REG_##r)); \
  654. }
  655. #define isp1362_set_mask16(d, r, m) { \
  656. u16 __v; \
  657. __v = isp1362_read_reg16(d, r); \
  658. if ((__v | m) != __v) \
  659. isp1362_write_reg16(d, r, __v | m); \
  660. }
  661. #define isp1362_clr_mask16(d, r, m) { \
  662. u16 __v; \
  663. __v = isp1362_read_reg16(d, r); \
  664. if ((__v & ~m) != __v) \
  665. isp1362_write_reg16(d, r, __v & ~m); \
  666. }
  667. #define isp1362_set_mask32(d, r, m) { \
  668. u32 __v; \
  669. __v = isp1362_read_reg32(d, r); \
  670. if ((__v | m) != __v) \
  671. isp1362_write_reg32(d, r, __v | m); \
  672. }
  673. #define isp1362_clr_mask32(d, r, m) { \
  674. u32 __v; \
  675. __v = isp1362_read_reg32(d, r); \
  676. if ((__v & ~m) != __v) \
  677. isp1362_write_reg32(d, r, __v & ~m); \
  678. }
  679. #define isp1362_show_reg(d, r) { \
  680. if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) \
  681. DBG(0, "%-12s[%02x]: %08x\n", #r, \
  682. ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \
  683. else \
  684. DBG(0, "%-12s[%02x]: %04x\n", #r, \
  685. ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \
  686. }
  687. static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd)
  688. {
  689. isp1362_show_reg(isp1362_hcd, HCREVISION);
  690. isp1362_show_reg(isp1362_hcd, HCCONTROL);
  691. isp1362_show_reg(isp1362_hcd, HCCMDSTAT);
  692. isp1362_show_reg(isp1362_hcd, HCINTSTAT);
  693. isp1362_show_reg(isp1362_hcd, HCINTENB);
  694. isp1362_show_reg(isp1362_hcd, HCFMINTVL);
  695. isp1362_show_reg(isp1362_hcd, HCFMREM);
  696. isp1362_show_reg(isp1362_hcd, HCFMNUM);
  697. isp1362_show_reg(isp1362_hcd, HCLSTHRESH);
  698. isp1362_show_reg(isp1362_hcd, HCRHDESCA);
  699. isp1362_show_reg(isp1362_hcd, HCRHDESCB);
  700. isp1362_show_reg(isp1362_hcd, HCRHSTATUS);
  701. isp1362_show_reg(isp1362_hcd, HCRHPORT1);
  702. isp1362_show_reg(isp1362_hcd, HCRHPORT2);
  703. isp1362_show_reg(isp1362_hcd, HCHWCFG);
  704. isp1362_show_reg(isp1362_hcd, HCDMACFG);
  705. isp1362_show_reg(isp1362_hcd, HCXFERCTR);
  706. isp1362_show_reg(isp1362_hcd, HCuPINT);
  707. if (in_interrupt())
  708. DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB",
  709. ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb);
  710. else
  711. isp1362_show_reg(isp1362_hcd, HCuPINTENB);
  712. isp1362_show_reg(isp1362_hcd, HCCHIPID);
  713. isp1362_show_reg(isp1362_hcd, HCSCRATCH);
  714. isp1362_show_reg(isp1362_hcd, HCBUFSTAT);
  715. isp1362_show_reg(isp1362_hcd, HCDIRADDR);
  716. /* Access would advance fifo
  717. * isp1362_show_reg(isp1362_hcd, HCDIRDATA);
  718. */
  719. isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ);
  720. isp1362_show_reg(isp1362_hcd, HCISTLRATE);
  721. isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ);
  722. isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ);
  723. isp1362_show_reg(isp1362_hcd, HCINTLDONE);
  724. isp1362_show_reg(isp1362_hcd, HCINTLSKIP);
  725. isp1362_show_reg(isp1362_hcd, HCINTLLAST);
  726. isp1362_show_reg(isp1362_hcd, HCINTLCURR);
  727. isp1362_show_reg(isp1362_hcd, HCATLBUFSZ);
  728. isp1362_show_reg(isp1362_hcd, HCATLBLKSZ);
  729. /* only valid after ATL_DONE interrupt
  730. * isp1362_show_reg(isp1362_hcd, HCATLDONE);
  731. */
  732. isp1362_show_reg(isp1362_hcd, HCATLSKIP);
  733. isp1362_show_reg(isp1362_hcd, HCATLLAST);
  734. isp1362_show_reg(isp1362_hcd, HCATLCURR);
  735. isp1362_show_reg(isp1362_hcd, HCATLDTC);
  736. isp1362_show_reg(isp1362_hcd, HCATLDTCTO);
  737. }
  738. static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len)
  739. {
  740. len = (len + 1) & ~1;
  741. isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE);
  742. isp1362_write_reg32(isp1362_hcd, HCDIRADDR,
  743. HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len));
  744. }
  745. static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
  746. {
  747. isp1362_write_diraddr(isp1362_hcd, offset, len);
  748. DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %p\n",
  749. __func__, len, offset, buf);
  750. isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
  751. isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA);
  752. isp1362_read_fifo(isp1362_hcd, buf, len);
  753. isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
  754. }
  755. static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len)
  756. {
  757. isp1362_write_diraddr(isp1362_hcd, offset, len);
  758. DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %p\n",
  759. __func__, len, offset, buf);
  760. isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
  761. isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET);
  762. isp1362_write_fifo(isp1362_hcd, buf, len);
  763. isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT);
  764. }
  765. static void __attribute__((unused)) dump_data(char *buf, int len)
  766. {
  767. if (dbg_level > 0) {
  768. int k;
  769. int lf = 0;
  770. for (k = 0; k < len; ++k) {
  771. if (!lf)
  772. DBG(0, "%04x:", k);
  773. printk(" %02x", ((u8 *) buf)[k]);
  774. lf = 1;
  775. if (!k)
  776. continue;
  777. if (k % 16 == 15) {
  778. printk("\n");
  779. lf = 0;
  780. continue;
  781. }
  782. if (k % 8 == 7)
  783. printk(" ");
  784. if (k % 4 == 3)
  785. printk(" ");
  786. }
  787. if (lf)
  788. printk("\n");
  789. }
  790. }
  791. #if defined(PTD_TRACE)
  792. static void dump_ptd(struct ptd *ptd)
  793. {
  794. DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n",
  795. container_of(ptd, struct isp1362_ep, ptd),
  796. PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd),
  797. PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
  798. PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd),
  799. PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd));
  800. DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr);
  801. }
  802. static void dump_ptd_out_data(struct ptd *ptd, u8 *buf)
  803. {
  804. if (dbg_level > 0) {
  805. if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
  806. DBG(0, "--out->\n");
  807. dump_data(buf, PTD_GET_LEN(ptd));
  808. }
  809. }
  810. }
  811. static void dump_ptd_in_data(struct ptd *ptd, u8 *buf)
  812. {
  813. if (dbg_level > 0) {
  814. if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
  815. DBG(0, "<--in--\n");
  816. dump_data(buf, PTD_GET_COUNT(ptd));
  817. }
  818. DBG(0, "-----\n");
  819. }
  820. }
  821. static void dump_ptd_queue(struct isp1362_ep_queue *epq)
  822. {
  823. struct isp1362_ep *ep;
  824. int dbg = dbg_level;
  825. dbg_level = 1;
  826. list_for_each_entry(ep, &epq->active, active) {
  827. dump_ptd(&ep->ptd);
  828. dump_data(ep->data, ep->length);
  829. }
  830. dbg_level = dbg;
  831. }
  832. #else
  833. #define dump_ptd(ptd) do {} while (0)
  834. #define dump_ptd_in_data(ptd, buf) do {} while (0)
  835. #define dump_ptd_out_data(ptd, buf) do {} while (0)
  836. #define dump_ptd_data(ptd, buf) do {} while (0)
  837. #define dump_ptd_queue(epq) do {} while (0)
  838. #endif