ehci-mv.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
  4. * Author: Chao Xie <chao.xie@marvell.com>
  5. * Neil Zhang <zhangwm@marvell.com>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/usb/otg.h>
  13. #include <linux/usb/of.h>
  14. #include <linux/platform_data/mv_usb.h>
  15. #include <linux/io.h>
  16. #include <linux/usb/hcd.h>
  17. #include "ehci.h"
  18. /* registers */
  19. #define U2x_CAPREGS_OFFSET 0x100
  20. #define CAPLENGTH_MASK (0xff)
  21. #define hcd_to_ehci_hcd_mv(h) ((struct ehci_hcd_mv *)hcd_to_ehci(h)->priv)
  22. struct ehci_hcd_mv {
  23. /* Which mode does this ehci running OTG/Host ? */
  24. int mode;
  25. void __iomem *base;
  26. void __iomem *cap_regs;
  27. void __iomem *op_regs;
  28. struct usb_phy *otg;
  29. struct clk *clk;
  30. struct phy *phy;
  31. int (*set_vbus)(unsigned int vbus);
  32. };
  33. static int mv_ehci_enable(struct ehci_hcd_mv *ehci_mv)
  34. {
  35. int retval;
  36. retval = clk_prepare_enable(ehci_mv->clk);
  37. if (retval)
  38. return retval;
  39. retval = phy_init(ehci_mv->phy);
  40. if (retval)
  41. clk_disable_unprepare(ehci_mv->clk);
  42. return retval;
  43. }
  44. static void mv_ehci_disable(struct ehci_hcd_mv *ehci_mv)
  45. {
  46. phy_exit(ehci_mv->phy);
  47. clk_disable_unprepare(ehci_mv->clk);
  48. }
  49. static int mv_ehci_reset(struct usb_hcd *hcd)
  50. {
  51. struct device *dev = hcd->self.controller;
  52. struct ehci_hcd_mv *ehci_mv = hcd_to_ehci_hcd_mv(hcd);
  53. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  54. u32 status;
  55. int retval;
  56. if (ehci_mv == NULL) {
  57. dev_err(dev, "Can not find private ehci data\n");
  58. return -ENODEV;
  59. }
  60. hcd->has_tt = 1;
  61. retval = ehci_setup(hcd);
  62. if (retval)
  63. dev_err(dev, "ehci_setup failed %d\n", retval);
  64. if (of_usb_get_phy_mode(dev->of_node) == USBPHY_INTERFACE_MODE_HSIC) {
  65. status = ehci_readl(ehci, &ehci->regs->port_status[0]);
  66. status |= PORT_TEST_FORCE;
  67. ehci_writel(ehci, status, &ehci->regs->port_status[0]);
  68. status &= ~PORT_TEST_FORCE;
  69. ehci_writel(ehci, status, &ehci->regs->port_status[0]);
  70. }
  71. return retval;
  72. }
  73. static struct hc_driver __read_mostly ehci_platform_hc_driver;
  74. static const struct ehci_driver_overrides platform_overrides __initconst = {
  75. .reset = mv_ehci_reset,
  76. .extra_priv_size = sizeof(struct ehci_hcd_mv),
  77. };
  78. static int mv_ehci_probe(struct platform_device *pdev)
  79. {
  80. struct mv_usb_platform_data *pdata = dev_get_platdata(&pdev->dev);
  81. struct usb_hcd *hcd;
  82. struct ehci_hcd *ehci;
  83. struct ehci_hcd_mv *ehci_mv;
  84. struct resource *r;
  85. int retval;
  86. u32 offset;
  87. u32 status;
  88. if (usb_disabled())
  89. return -ENODEV;
  90. hcd = usb_create_hcd(&ehci_platform_hc_driver, &pdev->dev, dev_name(&pdev->dev));
  91. if (!hcd)
  92. return -ENOMEM;
  93. platform_set_drvdata(pdev, hcd);
  94. ehci_mv = hcd_to_ehci_hcd_mv(hcd);
  95. ehci_mv->mode = MV_USB_MODE_HOST;
  96. if (pdata) {
  97. ehci_mv->mode = pdata->mode;
  98. ehci_mv->set_vbus = pdata->set_vbus;
  99. }
  100. ehci_mv->phy = devm_phy_optional_get(&pdev->dev, "usb");
  101. if (IS_ERR(ehci_mv->phy)) {
  102. retval = PTR_ERR(ehci_mv->phy);
  103. if (retval != -EPROBE_DEFER)
  104. dev_err(&pdev->dev, "Failed to get phy.\n");
  105. goto err_put_hcd;
  106. }
  107. ehci_mv->clk = devm_clk_get(&pdev->dev, NULL);
  108. if (IS_ERR(ehci_mv->clk)) {
  109. dev_err(&pdev->dev, "error getting clock\n");
  110. retval = PTR_ERR(ehci_mv->clk);
  111. goto err_put_hcd;
  112. }
  113. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  114. ehci_mv->base = devm_ioremap_resource(&pdev->dev, r);
  115. if (IS_ERR(ehci_mv->base)) {
  116. retval = PTR_ERR(ehci_mv->base);
  117. goto err_put_hcd;
  118. }
  119. retval = mv_ehci_enable(ehci_mv);
  120. if (retval) {
  121. dev_err(&pdev->dev, "init phy error %d\n", retval);
  122. goto err_put_hcd;
  123. }
  124. ehci_mv->cap_regs =
  125. (void __iomem *) ((unsigned long) ehci_mv->base + U2x_CAPREGS_OFFSET);
  126. offset = readl(ehci_mv->cap_regs) & CAPLENGTH_MASK;
  127. ehci_mv->op_regs =
  128. (void __iomem *) ((unsigned long) ehci_mv->cap_regs + offset);
  129. hcd->rsrc_start = r->start;
  130. hcd->rsrc_len = resource_size(r);
  131. hcd->regs = ehci_mv->op_regs;
  132. retval = platform_get_irq(pdev, 0);
  133. if (retval < 0)
  134. goto err_disable_clk;
  135. hcd->irq = retval;
  136. ehci = hcd_to_ehci(hcd);
  137. ehci->caps = (struct ehci_caps __iomem *) ehci_mv->cap_regs;
  138. if (ehci_mv->mode == MV_USB_MODE_OTG) {
  139. ehci_mv->otg = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
  140. if (IS_ERR(ehci_mv->otg)) {
  141. retval = PTR_ERR(ehci_mv->otg);
  142. if (retval == -ENXIO)
  143. dev_info(&pdev->dev, "MV_USB_MODE_OTG "
  144. "must have CONFIG_USB_PHY enabled\n");
  145. else
  146. dev_err(&pdev->dev,
  147. "unable to find transceiver\n");
  148. goto err_disable_clk;
  149. }
  150. retval = otg_set_host(ehci_mv->otg->otg, &hcd->self);
  151. if (retval < 0) {
  152. dev_err(&pdev->dev,
  153. "unable to register with transceiver\n");
  154. retval = -ENODEV;
  155. goto err_disable_clk;
  156. }
  157. /* otg will enable clock before use as host */
  158. mv_ehci_disable(ehci_mv);
  159. } else {
  160. if (ehci_mv->set_vbus)
  161. ehci_mv->set_vbus(1);
  162. retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
  163. if (retval) {
  164. dev_err(&pdev->dev,
  165. "failed to add hcd with err %d\n", retval);
  166. goto err_set_vbus;
  167. }
  168. device_wakeup_enable(hcd->self.controller);
  169. }
  170. if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_HSIC) {
  171. status = ehci_readl(ehci, &ehci->regs->port_status[0]);
  172. /* These "reserved" bits actually enable HSIC mode. */
  173. status |= BIT(25);
  174. status &= ~GENMASK(31, 30);
  175. ehci_writel(ehci, status, &ehci->regs->port_status[0]);
  176. }
  177. dev_info(&pdev->dev,
  178. "successful find EHCI device with regs 0x%p irq %d"
  179. " working in %s mode\n", hcd->regs, hcd->irq,
  180. ehci_mv->mode == MV_USB_MODE_OTG ? "OTG" : "Host");
  181. return 0;
  182. err_set_vbus:
  183. if (ehci_mv->set_vbus)
  184. ehci_mv->set_vbus(0);
  185. err_disable_clk:
  186. mv_ehci_disable(ehci_mv);
  187. err_put_hcd:
  188. usb_put_hcd(hcd);
  189. return retval;
  190. }
  191. static int mv_ehci_remove(struct platform_device *pdev)
  192. {
  193. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  194. struct ehci_hcd_mv *ehci_mv = hcd_to_ehci_hcd_mv(hcd);
  195. if (hcd->rh_registered)
  196. usb_remove_hcd(hcd);
  197. if (!IS_ERR_OR_NULL(ehci_mv->otg))
  198. otg_set_host(ehci_mv->otg->otg, NULL);
  199. if (ehci_mv->mode == MV_USB_MODE_HOST) {
  200. if (ehci_mv->set_vbus)
  201. ehci_mv->set_vbus(0);
  202. mv_ehci_disable(ehci_mv);
  203. }
  204. usb_put_hcd(hcd);
  205. return 0;
  206. }
  207. MODULE_ALIAS("mv-ehci");
  208. static const struct platform_device_id ehci_id_table[] = {
  209. {"pxa-u2oehci", 0},
  210. {"pxa-sph", 0},
  211. {},
  212. };
  213. static void mv_ehci_shutdown(struct platform_device *pdev)
  214. {
  215. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  216. if (!hcd->rh_registered)
  217. return;
  218. if (hcd->driver->shutdown)
  219. hcd->driver->shutdown(hcd);
  220. }
  221. static const struct of_device_id ehci_mv_dt_ids[] = {
  222. { .compatible = "marvell,pxau2o-ehci", },
  223. {},
  224. };
  225. static struct platform_driver ehci_mv_driver = {
  226. .probe = mv_ehci_probe,
  227. .remove = mv_ehci_remove,
  228. .shutdown = mv_ehci_shutdown,
  229. .driver = {
  230. .name = "mv-ehci",
  231. .bus = &platform_bus_type,
  232. .of_match_table = ehci_mv_dt_ids,
  233. },
  234. .id_table = ehci_id_table,
  235. };
  236. static int __init ehci_platform_init(void)
  237. {
  238. if (usb_disabled())
  239. return -ENODEV;
  240. ehci_init_driver(&ehci_platform_hc_driver, &platform_overrides);
  241. return platform_driver_register(&ehci_mv_driver);
  242. }
  243. module_init(ehci_platform_init);
  244. static void __exit ehci_platform_cleanup(void)
  245. {
  246. platform_driver_unregister(&ehci_mv_driver);
  247. }
  248. module_exit(ehci_platform_cleanup);
  249. MODULE_DESCRIPTION("Marvell EHCI driver");
  250. MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
  251. MODULE_AUTHOR("Neil Zhang <zhangwm@marvell.com>");
  252. MODULE_ALIAS("mv-ehci");
  253. MODULE_LICENSE("GPL");
  254. MODULE_DEVICE_TABLE(of, ehci_mv_dt_ids);