platform.c 20 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * platform.c - DesignWare HS OTG Controller platform driver
  4. *
  5. * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. The names of the above-listed copyright holders may not be used
  17. * to endorse or promote products derived from this software without
  18. * specific prior written permission.
  19. *
  20. * ALTERNATIVELY, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") as published by the Free Software
  22. * Foundation; either version 2 of the License, or (at your option) any
  23. * later version.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. */
  37. #include <linux/kernel.h>
  38. #include <linux/module.h>
  39. #include <linux/slab.h>
  40. #include <linux/clk.h>
  41. #include <linux/device.h>
  42. #include <linux/dma-mapping.h>
  43. #include <linux/of_device.h>
  44. #include <linux/mutex.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/phy/phy.h>
  47. #include <linux/platform_data/s3c-hsotg.h>
  48. #include <linux/reset.h>
  49. #include <linux/usb/of.h>
  50. #include "core.h"
  51. #include "hcd.h"
  52. #include "debug.h"
  53. static const char dwc2_driver_name[] = "dwc2";
  54. /*
  55. * Check the dr_mode against the module configuration and hardware
  56. * capabilities.
  57. *
  58. * The hardware, module, and dr_mode, can each be set to host, device,
  59. * or otg. Check that all these values are compatible and adjust the
  60. * value of dr_mode if possible.
  61. *
  62. * actual
  63. * HW MOD dr_mode dr_mode
  64. * ------------------------------
  65. * HST HST any : HST
  66. * HST DEV any : ---
  67. * HST OTG any : HST
  68. *
  69. * DEV HST any : ---
  70. * DEV DEV any : DEV
  71. * DEV OTG any : DEV
  72. *
  73. * OTG HST any : HST
  74. * OTG DEV any : DEV
  75. * OTG OTG any : dr_mode
  76. */
  77. static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
  78. {
  79. enum usb_dr_mode mode;
  80. hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
  81. if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
  82. hsotg->dr_mode = USB_DR_MODE_OTG;
  83. mode = hsotg->dr_mode;
  84. if (dwc2_hw_is_device(hsotg)) {
  85. if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
  86. dev_err(hsotg->dev,
  87. "Controller does not support host mode.\n");
  88. return -EINVAL;
  89. }
  90. mode = USB_DR_MODE_PERIPHERAL;
  91. } else if (dwc2_hw_is_host(hsotg)) {
  92. if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
  93. dev_err(hsotg->dev,
  94. "Controller does not support device mode.\n");
  95. return -EINVAL;
  96. }
  97. mode = USB_DR_MODE_HOST;
  98. } else {
  99. if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
  100. mode = USB_DR_MODE_HOST;
  101. else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
  102. mode = USB_DR_MODE_PERIPHERAL;
  103. }
  104. if (mode != hsotg->dr_mode) {
  105. dev_warn(hsotg->dev,
  106. "Configuration mismatch. dr_mode forced to %s\n",
  107. mode == USB_DR_MODE_HOST ? "host" : "device");
  108. hsotg->dr_mode = mode;
  109. }
  110. return 0;
  111. }
  112. static void __dwc2_disable_regulators(void *data)
  113. {
  114. struct dwc2_hsotg *hsotg = data;
  115. regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
  116. }
  117. static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  118. {
  119. struct platform_device *pdev = to_platform_device(hsotg->dev);
  120. int ret;
  121. ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
  122. hsotg->supplies);
  123. if (ret)
  124. return ret;
  125. ret = devm_add_action_or_reset(&pdev->dev,
  126. __dwc2_disable_regulators, hsotg);
  127. if (ret)
  128. return ret;
  129. if (hsotg->clk) {
  130. ret = clk_prepare_enable(hsotg->clk);
  131. if (ret)
  132. return ret;
  133. }
  134. if (hsotg->uphy) {
  135. ret = usb_phy_init(hsotg->uphy);
  136. } else if (hsotg->plat && hsotg->plat->phy_init) {
  137. ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
  138. } else {
  139. ret = phy_power_on(hsotg->phy);
  140. if (ret == 0)
  141. ret = phy_init(hsotg->phy);
  142. }
  143. return ret;
  144. }
  145. /**
  146. * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
  147. * @hsotg: The driver state
  148. *
  149. * A wrapper for platform code responsible for controlling
  150. * low-level USB platform resources (phy, clock, regulators)
  151. */
  152. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  153. {
  154. int ret = __dwc2_lowlevel_hw_enable(hsotg);
  155. if (ret == 0)
  156. hsotg->ll_hw_enabled = true;
  157. return ret;
  158. }
  159. static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  160. {
  161. struct platform_device *pdev = to_platform_device(hsotg->dev);
  162. int ret = 0;
  163. if (hsotg->uphy) {
  164. usb_phy_shutdown(hsotg->uphy);
  165. } else if (hsotg->plat && hsotg->plat->phy_exit) {
  166. ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
  167. } else {
  168. ret = phy_exit(hsotg->phy);
  169. if (ret == 0)
  170. ret = phy_power_off(hsotg->phy);
  171. }
  172. if (ret)
  173. return ret;
  174. if (hsotg->clk)
  175. clk_disable_unprepare(hsotg->clk);
  176. return 0;
  177. }
  178. /**
  179. * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
  180. * @hsotg: The driver state
  181. *
  182. * A wrapper for platform code responsible for controlling
  183. * low-level USB platform resources (phy, clock, regulators)
  184. */
  185. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  186. {
  187. int ret = __dwc2_lowlevel_hw_disable(hsotg);
  188. if (ret == 0)
  189. hsotg->ll_hw_enabled = false;
  190. return ret;
  191. }
  192. static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
  193. {
  194. int i, ret;
  195. hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
  196. if (IS_ERR(hsotg->reset)) {
  197. ret = PTR_ERR(hsotg->reset);
  198. dev_err(hsotg->dev, "error getting reset control %d\n", ret);
  199. return ret;
  200. }
  201. reset_control_deassert(hsotg->reset);
  202. hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
  203. if (IS_ERR(hsotg->reset_ecc)) {
  204. ret = PTR_ERR(hsotg->reset_ecc);
  205. dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
  206. return ret;
  207. }
  208. reset_control_deassert(hsotg->reset_ecc);
  209. /*
  210. * Attempt to find a generic PHY, then look for an old style
  211. * USB PHY and then fall back to pdata
  212. */
  213. hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
  214. if (IS_ERR(hsotg->phy)) {
  215. ret = PTR_ERR(hsotg->phy);
  216. switch (ret) {
  217. case -ENODEV:
  218. case -ENOSYS:
  219. hsotg->phy = NULL;
  220. break;
  221. case -EPROBE_DEFER:
  222. return ret;
  223. default:
  224. dev_err(hsotg->dev, "error getting phy %d\n", ret);
  225. return ret;
  226. }
  227. }
  228. if (!hsotg->phy) {
  229. hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
  230. if (IS_ERR(hsotg->uphy)) {
  231. ret = PTR_ERR(hsotg->uphy);
  232. switch (ret) {
  233. case -ENODEV:
  234. case -ENXIO:
  235. hsotg->uphy = NULL;
  236. break;
  237. case -EPROBE_DEFER:
  238. return ret;
  239. default:
  240. dev_err(hsotg->dev, "error getting usb phy %d\n",
  241. ret);
  242. return ret;
  243. }
  244. }
  245. }
  246. hsotg->plat = dev_get_platdata(hsotg->dev);
  247. /* Clock */
  248. hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
  249. if (IS_ERR(hsotg->clk)) {
  250. dev_err(hsotg->dev, "cannot get otg clock\n");
  251. return PTR_ERR(hsotg->clk);
  252. }
  253. /* Regulators */
  254. for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
  255. hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
  256. ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
  257. hsotg->supplies);
  258. if (ret) {
  259. if (ret != -EPROBE_DEFER)
  260. dev_err(hsotg->dev, "failed to request supplies: %d\n",
  261. ret);
  262. return ret;
  263. }
  264. return 0;
  265. }
  266. /**
  267. * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  268. * DWC_otg driver
  269. *
  270. * @dev: Platform device
  271. *
  272. * This routine is called, for example, when the rmmod command is executed. The
  273. * device may or may not be electrically present. If it is present, the driver
  274. * stops device processing. Any resources used on behalf of this device are
  275. * freed.
  276. */
  277. static int dwc2_driver_remove(struct platform_device *dev)
  278. {
  279. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  280. dwc2_debugfs_exit(hsotg);
  281. if (hsotg->hcd_enabled)
  282. dwc2_hcd_remove(hsotg);
  283. if (hsotg->gadget_enabled)
  284. dwc2_hsotg_remove(hsotg);
  285. dwc2_drd_exit(hsotg);
  286. if (hsotg->params.activate_stm_id_vb_detection)
  287. regulator_disable(hsotg->usb33d);
  288. if (hsotg->ll_hw_enabled)
  289. dwc2_lowlevel_hw_disable(hsotg);
  290. reset_control_assert(hsotg->reset);
  291. reset_control_assert(hsotg->reset_ecc);
  292. return 0;
  293. }
  294. /**
  295. * dwc2_driver_shutdown() - Called on device shutdown
  296. *
  297. * @dev: Platform device
  298. *
  299. * In specific conditions (involving usb hubs) dwc2 devices can create a
  300. * lot of interrupts, even to the point of overwhelming devices running
  301. * at low frequencies. Some devices need to do special clock handling
  302. * at shutdown-time which may bring the system clock below the threshold
  303. * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
  304. * prevents reboots/poweroffs from getting stuck in such cases.
  305. */
  306. static void dwc2_driver_shutdown(struct platform_device *dev)
  307. {
  308. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  309. dwc2_disable_global_interrupts(hsotg);
  310. synchronize_irq(hsotg->irq);
  311. }
  312. /**
  313. * dwc2_check_core_endianness() - Returns true if core and AHB have
  314. * opposite endianness.
  315. * @hsotg: Programming view of the DWC_otg controller.
  316. */
  317. static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
  318. {
  319. u32 snpsid;
  320. snpsid = ioread32(hsotg->regs + GSNPSID);
  321. if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
  322. (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
  323. (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
  324. return false;
  325. return true;
  326. }
  327. /**
  328. * Check core version
  329. *
  330. * @hsotg: Programming view of the DWC_otg controller
  331. *
  332. */
  333. int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
  334. {
  335. struct dwc2_hw_params *hw = &hsotg->hw_params;
  336. /*
  337. * Attempt to ensure this device is really a DWC_otg Controller.
  338. * Read and verify the GSNPSID register contents. The value should be
  339. * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
  340. */
  341. hw->snpsid = dwc2_readl(hsotg, GSNPSID);
  342. if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
  343. (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
  344. (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
  345. dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
  346. hw->snpsid);
  347. return -ENODEV;
  348. }
  349. dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
  350. hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
  351. hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
  352. return 0;
  353. }
  354. /**
  355. * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
  356. * driver
  357. *
  358. * @dev: Platform device
  359. *
  360. * This routine creates the driver components required to control the device
  361. * (core, HCD, and PCD) and initializes the device. The driver components are
  362. * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
  363. * in the device private data. This allows the driver to access the dwc2_hsotg
  364. * structure on subsequent calls to driver methods for this device.
  365. */
  366. static int dwc2_driver_probe(struct platform_device *dev)
  367. {
  368. struct dwc2_hsotg *hsotg;
  369. struct resource *res;
  370. int retval;
  371. hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
  372. if (!hsotg)
  373. return -ENOMEM;
  374. hsotg->dev = &dev->dev;
  375. /*
  376. * Use reasonable defaults so platforms don't have to provide these.
  377. */
  378. if (!dev->dev.dma_mask)
  379. dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
  380. retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  381. if (retval) {
  382. dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
  383. return retval;
  384. }
  385. hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
  386. if (IS_ERR(hsotg->regs))
  387. return PTR_ERR(hsotg->regs);
  388. dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
  389. (unsigned long)res->start, hsotg->regs);
  390. retval = dwc2_lowlevel_hw_init(hsotg);
  391. if (retval)
  392. return retval;
  393. spin_lock_init(&hsotg->lock);
  394. hsotg->irq = platform_get_irq(dev, 0);
  395. if (hsotg->irq < 0)
  396. return hsotg->irq;
  397. dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
  398. hsotg->irq);
  399. retval = devm_request_irq(hsotg->dev, hsotg->irq,
  400. dwc2_handle_common_intr, IRQF_SHARED,
  401. dev_name(hsotg->dev), hsotg);
  402. if (retval)
  403. return retval;
  404. hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
  405. if (IS_ERR(hsotg->vbus_supply)) {
  406. retval = PTR_ERR(hsotg->vbus_supply);
  407. hsotg->vbus_supply = NULL;
  408. if (retval != -ENODEV)
  409. return retval;
  410. }
  411. retval = dwc2_lowlevel_hw_enable(hsotg);
  412. if (retval)
  413. return retval;
  414. hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
  415. retval = dwc2_get_dr_mode(hsotg);
  416. if (retval)
  417. goto error;
  418. hsotg->need_phy_for_wake =
  419. of_property_read_bool(dev->dev.of_node,
  420. "snps,need-phy-for-wake");
  421. /*
  422. * Before performing any core related operations
  423. * check core version.
  424. */
  425. retval = dwc2_check_core_version(hsotg);
  426. if (retval)
  427. goto error;
  428. /*
  429. * Reset before dwc2_get_hwparams() then it could get power-on real
  430. * reset value form registers.
  431. */
  432. retval = dwc2_core_reset(hsotg, false);
  433. if (retval)
  434. goto error;
  435. /* Detect config values from hardware */
  436. retval = dwc2_get_hwparams(hsotg);
  437. if (retval)
  438. goto error;
  439. /*
  440. * For OTG cores, set the force mode bits to reflect the value
  441. * of dr_mode. Force mode bits should not be touched at any
  442. * other time after this.
  443. */
  444. dwc2_force_dr_mode(hsotg);
  445. retval = dwc2_init_params(hsotg);
  446. if (retval)
  447. goto error;
  448. if (hsotg->params.activate_stm_id_vb_detection) {
  449. u32 ggpio;
  450. hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
  451. if (IS_ERR(hsotg->usb33d)) {
  452. retval = PTR_ERR(hsotg->usb33d);
  453. if (retval != -EPROBE_DEFER)
  454. dev_err(hsotg->dev,
  455. "failed to request usb33d supply: %d\n",
  456. retval);
  457. goto error;
  458. }
  459. retval = regulator_enable(hsotg->usb33d);
  460. if (retval) {
  461. dev_err(hsotg->dev,
  462. "failed to enable usb33d supply: %d\n", retval);
  463. goto error;
  464. }
  465. ggpio = dwc2_readl(hsotg, GGPIO);
  466. ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
  467. ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
  468. dwc2_writel(hsotg, ggpio, GGPIO);
  469. /* ID/VBUS detection startup time */
  470. usleep_range(5000, 7000);
  471. }
  472. retval = dwc2_drd_init(hsotg);
  473. if (retval) {
  474. if (retval != -EPROBE_DEFER)
  475. dev_err(hsotg->dev, "failed to initialize dual-role\n");
  476. goto error_init;
  477. }
  478. if (hsotg->dr_mode != USB_DR_MODE_HOST) {
  479. retval = dwc2_gadget_init(hsotg);
  480. if (retval)
  481. goto error_drd;
  482. hsotg->gadget_enabled = 1;
  483. }
  484. /*
  485. * If we need PHY for wakeup we must be wakeup capable.
  486. * When we have a device that can wake without the PHY we
  487. * can adjust this condition.
  488. */
  489. if (hsotg->need_phy_for_wake)
  490. device_set_wakeup_capable(&dev->dev, true);
  491. hsotg->reset_phy_on_wake =
  492. of_property_read_bool(dev->dev.of_node,
  493. "snps,reset-phy-on-wake");
  494. if (hsotg->reset_phy_on_wake && !hsotg->phy) {
  495. dev_warn(hsotg->dev,
  496. "Quirk reset-phy-on-wake only supports generic PHYs\n");
  497. hsotg->reset_phy_on_wake = false;
  498. }
  499. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  500. retval = dwc2_hcd_init(hsotg);
  501. if (retval) {
  502. if (hsotg->gadget_enabled)
  503. dwc2_hsotg_remove(hsotg);
  504. goto error_drd;
  505. }
  506. hsotg->hcd_enabled = 1;
  507. }
  508. platform_set_drvdata(dev, hsotg);
  509. hsotg->hibernated = 0;
  510. dwc2_debugfs_init(hsotg);
  511. /* Gadget code manages lowlevel hw on its own */
  512. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  513. dwc2_lowlevel_hw_disable(hsotg);
  514. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  515. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  516. /* Postponed adding a new gadget to the udc class driver list */
  517. if (hsotg->gadget_enabled) {
  518. retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
  519. if (retval) {
  520. hsotg->gadget.udc = NULL;
  521. dwc2_hsotg_remove(hsotg);
  522. goto error_debugfs;
  523. }
  524. }
  525. #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
  526. return 0;
  527. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  528. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  529. error_debugfs:
  530. dwc2_debugfs_exit(hsotg);
  531. if (hsotg->hcd_enabled)
  532. dwc2_hcd_remove(hsotg);
  533. #endif
  534. error_drd:
  535. dwc2_drd_exit(hsotg);
  536. error_init:
  537. if (hsotg->params.activate_stm_id_vb_detection)
  538. regulator_disable(hsotg->usb33d);
  539. error:
  540. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
  541. dwc2_lowlevel_hw_disable(hsotg);
  542. return retval;
  543. }
  544. static int __maybe_unused dwc2_suspend(struct device *dev)
  545. {
  546. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  547. bool is_device_mode = dwc2_is_device_mode(dwc2);
  548. int ret = 0;
  549. if (is_device_mode)
  550. dwc2_hsotg_suspend(dwc2);
  551. dwc2_drd_suspend(dwc2);
  552. if (dwc2->params.activate_stm_id_vb_detection) {
  553. unsigned long flags;
  554. u32 ggpio, gotgctl;
  555. /*
  556. * Need to force the mode to the current mode to avoid Mode
  557. * Mismatch Interrupt when ID detection will be disabled.
  558. */
  559. dwc2_force_mode(dwc2, !is_device_mode);
  560. spin_lock_irqsave(&dwc2->lock, flags);
  561. gotgctl = dwc2_readl(dwc2, GOTGCTL);
  562. /* bypass debounce filter, enable overrides */
  563. gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
  564. gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
  565. /* Force A / B session if needed */
  566. if (gotgctl & GOTGCTL_ASESVLD)
  567. gotgctl |= GOTGCTL_AVALOVAL;
  568. if (gotgctl & GOTGCTL_BSESVLD)
  569. gotgctl |= GOTGCTL_BVALOVAL;
  570. dwc2_writel(dwc2, gotgctl, GOTGCTL);
  571. spin_unlock_irqrestore(&dwc2->lock, flags);
  572. ggpio = dwc2_readl(dwc2, GGPIO);
  573. ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
  574. ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
  575. dwc2_writel(dwc2, ggpio, GGPIO);
  576. regulator_disable(dwc2->usb33d);
  577. }
  578. if (dwc2->ll_hw_enabled &&
  579. (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
  580. ret = __dwc2_lowlevel_hw_disable(dwc2);
  581. dwc2->phy_off_for_suspend = true;
  582. }
  583. return ret;
  584. }
  585. static int __maybe_unused dwc2_resume(struct device *dev)
  586. {
  587. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  588. int ret = 0;
  589. if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
  590. ret = __dwc2_lowlevel_hw_enable(dwc2);
  591. if (ret)
  592. return ret;
  593. }
  594. dwc2->phy_off_for_suspend = false;
  595. if (dwc2->params.activate_stm_id_vb_detection) {
  596. unsigned long flags;
  597. u32 ggpio, gotgctl;
  598. ret = regulator_enable(dwc2->usb33d);
  599. if (ret)
  600. return ret;
  601. ggpio = dwc2_readl(dwc2, GGPIO);
  602. ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
  603. ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
  604. dwc2_writel(dwc2, ggpio, GGPIO);
  605. /* ID/VBUS detection startup time */
  606. usleep_range(5000, 7000);
  607. spin_lock_irqsave(&dwc2->lock, flags);
  608. gotgctl = dwc2_readl(dwc2, GOTGCTL);
  609. gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
  610. gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
  611. GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
  612. dwc2_writel(dwc2, gotgctl, GOTGCTL);
  613. spin_unlock_irqrestore(&dwc2->lock, flags);
  614. }
  615. /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
  616. dwc2_force_dr_mode(dwc2);
  617. dwc2_drd_resume(dwc2);
  618. if (dwc2_is_device_mode(dwc2))
  619. ret = dwc2_hsotg_resume(dwc2);
  620. return ret;
  621. }
  622. static const struct dev_pm_ops dwc2_dev_pm_ops = {
  623. SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
  624. };
  625. static struct platform_driver dwc2_platform_driver = {
  626. .driver = {
  627. .name = dwc2_driver_name,
  628. .of_match_table = dwc2_of_match_table,
  629. .pm = &dwc2_dev_pm_ops,
  630. },
  631. .probe = dwc2_driver_probe,
  632. .remove = dwc2_driver_remove,
  633. .shutdown = dwc2_driver_shutdown,
  634. };
  635. module_platform_driver(dwc2_platform_driver);
  636. MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
  637. MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
  638. MODULE_LICENSE("Dual BSD/GPL");