hcd_queue.c 65 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
  4. *
  5. * Copyright (C) 2004-2013 Synopsys, Inc.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. The names of the above-listed copyright holders may not be used
  17. * to endorse or promote products derived from this software without
  18. * specific prior written permission.
  19. *
  20. * ALTERNATIVELY, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") as published by the Free Software
  22. * Foundation; either version 2 of the License, or (at your option) any
  23. * later version.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. */
  37. /*
  38. * This file contains the functions to manage Queue Heads and Queue
  39. * Transfer Descriptors for Host mode
  40. */
  41. #include <linux/gcd.h>
  42. #include <linux/kernel.h>
  43. #include <linux/module.h>
  44. #include <linux/spinlock.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/dma-mapping.h>
  47. #include <linux/io.h>
  48. #include <linux/slab.h>
  49. #include <linux/usb.h>
  50. #include <linux/usb/hcd.h>
  51. #include <linux/usb/ch11.h>
  52. #include "core.h"
  53. #include "hcd.h"
  54. /* Wait this long before releasing periodic reservation */
  55. #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
  56. /* If we get a NAK, wait this long before retrying */
  57. #define DWC2_RETRY_WAIT_DELAY (1 * NSEC_PER_MSEC)
  58. /**
  59. * dwc2_periodic_channel_available() - Checks that a channel is available for a
  60. * periodic transfer
  61. *
  62. * @hsotg: The HCD state structure for the DWC OTG controller
  63. *
  64. * Return: 0 if successful, negative error code otherwise
  65. */
  66. static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
  67. {
  68. /*
  69. * Currently assuming that there is a dedicated host channel for
  70. * each periodic transaction plus at least one host channel for
  71. * non-periodic transactions
  72. */
  73. int status;
  74. int num_channels;
  75. num_channels = hsotg->params.host_channels;
  76. if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
  77. num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
  78. status = 0;
  79. } else {
  80. dev_dbg(hsotg->dev,
  81. "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
  82. __func__, num_channels,
  83. hsotg->periodic_channels, hsotg->non_periodic_channels);
  84. status = -ENOSPC;
  85. }
  86. return status;
  87. }
  88. /**
  89. * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
  90. * for the specified QH in the periodic schedule
  91. *
  92. * @hsotg: The HCD state structure for the DWC OTG controller
  93. * @qh: QH containing periodic bandwidth required
  94. *
  95. * Return: 0 if successful, negative error code otherwise
  96. *
  97. * For simplicity, this calculation assumes that all the transfers in the
  98. * periodic schedule may occur in the same (micro)frame
  99. */
  100. static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
  101. struct dwc2_qh *qh)
  102. {
  103. int status;
  104. s16 max_claimed_usecs;
  105. status = 0;
  106. if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
  107. /*
  108. * High speed mode
  109. * Max periodic usecs is 80% x 125 usec = 100 usec
  110. */
  111. max_claimed_usecs = 100 - qh->host_us;
  112. } else {
  113. /*
  114. * Full speed mode
  115. * Max periodic usecs is 90% x 1000 usec = 900 usec
  116. */
  117. max_claimed_usecs = 900 - qh->host_us;
  118. }
  119. if (hsotg->periodic_usecs > max_claimed_usecs) {
  120. dev_err(hsotg->dev,
  121. "%s: already claimed usecs %d, required usecs %d\n",
  122. __func__, hsotg->periodic_usecs, qh->host_us);
  123. status = -ENOSPC;
  124. }
  125. return status;
  126. }
  127. /**
  128. * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
  129. *
  130. * @map: The bitmap representing the schedule; will be updated
  131. * upon success.
  132. * @bits_per_period: The schedule represents several periods. This is how many
  133. * bits are in each period. It's assumed that the beginning
  134. * of the schedule will repeat after its end.
  135. * @periods_in_map: The number of periods in the schedule.
  136. * @num_bits: The number of bits we need per period we want to reserve
  137. * in this function call.
  138. * @interval: How often we need to be scheduled for the reservation this
  139. * time. 1 means every period. 2 means every other period.
  140. * ...you get the picture?
  141. * @start: The bit number to start at. Normally 0. Must be within
  142. * the interval or we return failure right away.
  143. * @only_one_period: Normally we'll allow picking a start anywhere within the
  144. * first interval, since we can still make all repetition
  145. * requirements by doing that. However, if you pass true
  146. * here then we'll return failure if we can't fit within
  147. * the period that "start" is in.
  148. *
  149. * The idea here is that we want to schedule time for repeating events that all
  150. * want the same resource. The resource is divided into fixed-sized periods
  151. * and the events want to repeat every "interval" periods. The schedule
  152. * granularity is one bit.
  153. *
  154. * To keep things "simple", we'll represent our schedule with a bitmap that
  155. * contains a fixed number of periods. This gets rid of a lot of complexity
  156. * but does mean that we need to handle things specially (and non-ideally) if
  157. * the number of the periods in the schedule doesn't match well with the
  158. * intervals that we're trying to schedule.
  159. *
  160. * Here's an explanation of the scheme we'll implement, assuming 8 periods.
  161. * - If interval is 1, we need to take up space in each of the 8
  162. * periods we're scheduling. Easy.
  163. * - If interval is 2, we need to take up space in half of the
  164. * periods. Again, easy.
  165. * - If interval is 3, we actually need to fall back to interval 1.
  166. * Why? Because we might need time in any period. AKA for the
  167. * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
  168. * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
  169. * 0, 3, and 6. Since we could be in any frame we need to reserve
  170. * for all of them. Sucks, but that's what you gotta do. Note that
  171. * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
  172. * then we need more memory and time to do scheduling.
  173. * - If interval is 4, easy.
  174. * - If interval is 5, we again need interval 1. The schedule will be
  175. * 0, 5, 2, 7, 4, 1, 6, 3, 0
  176. * - If interval is 6, we need interval 2. 0, 6, 4, 2.
  177. * - If interval is 7, we need interval 1.
  178. * - If interval is 8, we need interval 8.
  179. *
  180. * If you do the math, you'll see that we need to pretend that interval is
  181. * equal to the greatest_common_divisor(interval, periods_in_map).
  182. *
  183. * Note that at the moment this function tends to front-pack the schedule.
  184. * In some cases that's really non-ideal (it's hard to schedule things that
  185. * need to repeat every period). In other cases it's perfect (you can easily
  186. * schedule bigger, less often repeating things).
  187. *
  188. * Here's the algorithm in action (8 periods, 5 bits per period):
  189. * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
  190. * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
  191. * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
  192. * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
  193. * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
  194. * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
  195. * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
  196. * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
  197. * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
  198. * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
  199. * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
  200. * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
  201. * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
  202. * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
  203. * | | | | | | | | | Remv 1 bits, intv 1 at 4
  204. * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
  205. * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
  206. * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
  207. * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
  208. * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
  209. * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
  210. * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
  211. *
  212. * This function is pretty generic and could be easily abstracted if anything
  213. * needed similar scheduling.
  214. *
  215. * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
  216. * unschedule routine. The map bitmap will be updated on a non-error result.
  217. */
  218. static int pmap_schedule(unsigned long *map, int bits_per_period,
  219. int periods_in_map, int num_bits,
  220. int interval, int start, bool only_one_period)
  221. {
  222. int interval_bits;
  223. int to_reserve;
  224. int first_end;
  225. int i;
  226. if (num_bits > bits_per_period)
  227. return -ENOSPC;
  228. /* Adjust interval as per description */
  229. interval = gcd(interval, periods_in_map);
  230. interval_bits = bits_per_period * interval;
  231. to_reserve = periods_in_map / interval;
  232. /* If start has gotten us past interval then we can't schedule */
  233. if (start >= interval_bits)
  234. return -ENOSPC;
  235. if (only_one_period)
  236. /* Must fit within same period as start; end at begin of next */
  237. first_end = (start / bits_per_period + 1) * bits_per_period;
  238. else
  239. /* Can fit anywhere in the first interval */
  240. first_end = interval_bits;
  241. /*
  242. * We'll try to pick the first repetition, then see if that time
  243. * is free for each of the subsequent repetitions. If it's not
  244. * we'll adjust the start time for the next search of the first
  245. * repetition.
  246. */
  247. while (start + num_bits <= first_end) {
  248. int end;
  249. /* Need to stay within this period */
  250. end = (start / bits_per_period + 1) * bits_per_period;
  251. /* Look for num_bits us in this microframe starting at start */
  252. start = bitmap_find_next_zero_area(map, end, start, num_bits,
  253. 0);
  254. /*
  255. * We should get start >= end if we fail. We might be
  256. * able to check the next microframe depending on the
  257. * interval, so continue on (start already updated).
  258. */
  259. if (start >= end) {
  260. start = end;
  261. continue;
  262. }
  263. /* At this point we have a valid point for first one */
  264. for (i = 1; i < to_reserve; i++) {
  265. int ith_start = start + interval_bits * i;
  266. int ith_end = end + interval_bits * i;
  267. int ret;
  268. /* Use this as a dumb "check if bits are 0" */
  269. ret = bitmap_find_next_zero_area(
  270. map, ith_start + num_bits, ith_start, num_bits,
  271. 0);
  272. /* We got the right place, continue checking */
  273. if (ret == ith_start)
  274. continue;
  275. /* Move start up for next time and exit for loop */
  276. ith_start = bitmap_find_next_zero_area(
  277. map, ith_end, ith_start, num_bits, 0);
  278. if (ith_start >= ith_end)
  279. /* Need a while new period next time */
  280. start = end;
  281. else
  282. start = ith_start - interval_bits * i;
  283. break;
  284. }
  285. /* If didn't exit the for loop with a break, we have success */
  286. if (i == to_reserve)
  287. break;
  288. }
  289. if (start + num_bits > first_end)
  290. return -ENOSPC;
  291. for (i = 0; i < to_reserve; i++) {
  292. int ith_start = start + interval_bits * i;
  293. bitmap_set(map, ith_start, num_bits);
  294. }
  295. return start;
  296. }
  297. /**
  298. * pmap_unschedule() - Undo work done by pmap_schedule()
  299. *
  300. * @map: See pmap_schedule().
  301. * @bits_per_period: See pmap_schedule().
  302. * @periods_in_map: See pmap_schedule().
  303. * @num_bits: The number of bits that was passed to schedule.
  304. * @interval: The interval that was passed to schedule.
  305. * @start: The return value from pmap_schedule().
  306. */
  307. static void pmap_unschedule(unsigned long *map, int bits_per_period,
  308. int periods_in_map, int num_bits,
  309. int interval, int start)
  310. {
  311. int interval_bits;
  312. int to_release;
  313. int i;
  314. /* Adjust interval as per description in pmap_schedule() */
  315. interval = gcd(interval, periods_in_map);
  316. interval_bits = bits_per_period * interval;
  317. to_release = periods_in_map / interval;
  318. for (i = 0; i < to_release; i++) {
  319. int ith_start = start + interval_bits * i;
  320. bitmap_clear(map, ith_start, num_bits);
  321. }
  322. }
  323. /**
  324. * dwc2_get_ls_map() - Get the map used for the given qh
  325. *
  326. * @hsotg: The HCD state structure for the DWC OTG controller.
  327. * @qh: QH for the periodic transfer.
  328. *
  329. * We'll always get the periodic map out of our TT. Note that even if we're
  330. * running the host straight in low speed / full speed mode it appears as if
  331. * a TT is allocated for us, so we'll use it. If that ever changes we can
  332. * add logic here to get a map out of "hsotg" if !qh->do_split.
  333. *
  334. * Returns: the map or NULL if a map couldn't be found.
  335. */
  336. static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
  337. struct dwc2_qh *qh)
  338. {
  339. unsigned long *map;
  340. /* Don't expect to be missing a TT and be doing low speed scheduling */
  341. if (WARN_ON(!qh->dwc_tt))
  342. return NULL;
  343. /* Get the map and adjust if this is a multi_tt hub */
  344. map = qh->dwc_tt->periodic_bitmaps;
  345. if (qh->dwc_tt->usb_tt->multi)
  346. map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1);
  347. return map;
  348. }
  349. #ifdef DWC2_PRINT_SCHEDULE
  350. /*
  351. * cat_printf() - A printf() + strcat() helper
  352. *
  353. * This is useful for concatenating a bunch of strings where each string is
  354. * constructed using printf.
  355. *
  356. * @buf: The destination buffer; will be updated to point after the printed
  357. * data.
  358. * @size: The number of bytes in the buffer (includes space for '\0').
  359. * @fmt: The format for printf.
  360. * @...: The args for printf.
  361. */
  362. static __printf(3, 4)
  363. void cat_printf(char **buf, size_t *size, const char *fmt, ...)
  364. {
  365. va_list args;
  366. int i;
  367. if (*size == 0)
  368. return;
  369. va_start(args, fmt);
  370. i = vsnprintf(*buf, *size, fmt, args);
  371. va_end(args);
  372. if (i >= *size) {
  373. (*buf)[*size - 1] = '\0';
  374. *buf += *size;
  375. *size = 0;
  376. } else {
  377. *buf += i;
  378. *size -= i;
  379. }
  380. }
  381. /*
  382. * pmap_print() - Print the given periodic map
  383. *
  384. * Will attempt to print out the periodic schedule.
  385. *
  386. * @map: See pmap_schedule().
  387. * @bits_per_period: See pmap_schedule().
  388. * @periods_in_map: See pmap_schedule().
  389. * @period_name: The name of 1 period, like "uFrame"
  390. * @units: The name of the units, like "us".
  391. * @print_fn: The function to call for printing.
  392. * @print_data: Opaque data to pass to the print function.
  393. */
  394. static void pmap_print(unsigned long *map, int bits_per_period,
  395. int periods_in_map, const char *period_name,
  396. const char *units,
  397. void (*print_fn)(const char *str, void *data),
  398. void *print_data)
  399. {
  400. int period;
  401. for (period = 0; period < periods_in_map; period++) {
  402. char tmp[64];
  403. char *buf = tmp;
  404. size_t buf_size = sizeof(tmp);
  405. int period_start = period * bits_per_period;
  406. int period_end = period_start + bits_per_period;
  407. int start = 0;
  408. int count = 0;
  409. bool printed = false;
  410. int i;
  411. for (i = period_start; i < period_end + 1; i++) {
  412. /* Handle case when ith bit is set */
  413. if (i < period_end &&
  414. bitmap_find_next_zero_area(map, i + 1,
  415. i, 1, 0) != i) {
  416. if (count == 0)
  417. start = i - period_start;
  418. count++;
  419. continue;
  420. }
  421. /* ith bit isn't set; don't care if count == 0 */
  422. if (count == 0)
  423. continue;
  424. if (!printed)
  425. cat_printf(&buf, &buf_size, "%s %d: ",
  426. period_name, period);
  427. else
  428. cat_printf(&buf, &buf_size, ", ");
  429. printed = true;
  430. cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
  431. units, start + count - 1, units);
  432. count = 0;
  433. }
  434. if (printed)
  435. print_fn(tmp, print_data);
  436. }
  437. }
  438. struct dwc2_qh_print_data {
  439. struct dwc2_hsotg *hsotg;
  440. struct dwc2_qh *qh;
  441. };
  442. /**
  443. * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
  444. *
  445. * @str: The string to print
  446. * @data: A pointer to a struct dwc2_qh_print_data
  447. */
  448. static void dwc2_qh_print(const char *str, void *data)
  449. {
  450. struct dwc2_qh_print_data *print_data = data;
  451. dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
  452. }
  453. /**
  454. * dwc2_qh_schedule_print() - Print the periodic schedule
  455. *
  456. * @hsotg: The HCD state structure for the DWC OTG controller.
  457. * @qh: QH to print.
  458. */
  459. static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
  460. struct dwc2_qh *qh)
  461. {
  462. struct dwc2_qh_print_data print_data = { hsotg, qh };
  463. int i;
  464. /*
  465. * The printing functions are quite slow and inefficient.
  466. * If we don't have tracing turned on, don't run unless the special
  467. * define is turned on.
  468. */
  469. if (qh->schedule_low_speed) {
  470. unsigned long *map = dwc2_get_ls_map(hsotg, qh);
  471. dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
  472. qh, qh->device_us,
  473. DWC2_ROUND_US_TO_SLICE(qh->device_us),
  474. DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
  475. if (map) {
  476. dwc2_sch_dbg(hsotg,
  477. "QH=%p Whole low/full speed map %p now:\n",
  478. qh, map);
  479. pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
  480. DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
  481. dwc2_qh_print, &print_data);
  482. }
  483. }
  484. for (i = 0; i < qh->num_hs_transfers; i++) {
  485. struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
  486. int uframe = trans_time->start_schedule_us /
  487. DWC2_HS_PERIODIC_US_PER_UFRAME;
  488. int rel_us = trans_time->start_schedule_us %
  489. DWC2_HS_PERIODIC_US_PER_UFRAME;
  490. dwc2_sch_dbg(hsotg,
  491. "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
  492. qh, i, trans_time->duration_us, uframe, rel_us);
  493. }
  494. if (qh->num_hs_transfers) {
  495. dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
  496. pmap_print(hsotg->hs_periodic_bitmap,
  497. DWC2_HS_PERIODIC_US_PER_UFRAME,
  498. DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
  499. dwc2_qh_print, &print_data);
  500. }
  501. }
  502. #else
  503. static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
  504. struct dwc2_qh *qh) {};
  505. #endif
  506. /**
  507. * dwc2_ls_pmap_schedule() - Schedule a low speed QH
  508. *
  509. * @hsotg: The HCD state structure for the DWC OTG controller.
  510. * @qh: QH for the periodic transfer.
  511. * @search_slice: We'll start trying to schedule at the passed slice.
  512. * Remember that slices are the units of the low speed
  513. * schedule (think 25us or so).
  514. *
  515. * Wraps pmap_schedule() with the right parameters for low speed scheduling.
  516. *
  517. * Normally we schedule low speed devices on the map associated with the TT.
  518. *
  519. * Returns: 0 for success or an error code.
  520. */
  521. static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
  522. int search_slice)
  523. {
  524. int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
  525. unsigned long *map = dwc2_get_ls_map(hsotg, qh);
  526. int slice;
  527. if (!map)
  528. return -EINVAL;
  529. /*
  530. * Schedule on the proper low speed map with our low speed scheduling
  531. * parameters. Note that we use the "device_interval" here since
  532. * we want the low speed interval and the only way we'd be in this
  533. * function is if the device is low speed.
  534. *
  535. * If we happen to be doing low speed and high speed scheduling for the
  536. * same transaction (AKA we have a split) we always do low speed first.
  537. * That means we can always pass "false" for only_one_period (that
  538. * parameters is only useful when we're trying to get one schedule to
  539. * match what we already planned in the other schedule).
  540. */
  541. slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
  542. DWC2_LS_SCHEDULE_FRAMES, slices,
  543. qh->device_interval, search_slice, false);
  544. if (slice < 0)
  545. return slice;
  546. qh->ls_start_schedule_slice = slice;
  547. return 0;
  548. }
  549. /**
  550. * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
  551. *
  552. * @hsotg: The HCD state structure for the DWC OTG controller.
  553. * @qh: QH for the periodic transfer.
  554. */
  555. static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
  556. struct dwc2_qh *qh)
  557. {
  558. int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
  559. unsigned long *map = dwc2_get_ls_map(hsotg, qh);
  560. /* Schedule should have failed, so no worries about no error code */
  561. if (!map)
  562. return;
  563. pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
  564. DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
  565. qh->ls_start_schedule_slice);
  566. }
  567. /**
  568. * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
  569. *
  570. * This will schedule something on the main dwc2 schedule.
  571. *
  572. * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
  573. * update this with the result upon success. We also use the duration from
  574. * the same structure.
  575. *
  576. * @hsotg: The HCD state structure for the DWC OTG controller.
  577. * @qh: QH for the periodic transfer.
  578. * @only_one_period: If true we will limit ourselves to just looking at
  579. * one period (aka one 100us chunk). This is used if we have
  580. * already scheduled something on the low speed schedule and
  581. * need to find something that matches on the high speed one.
  582. * @index: The index into qh->hs_transfers that we're working with.
  583. *
  584. * Returns: 0 for success or an error code. Upon success the
  585. * dwc2_hs_transfer_time specified by "index" will be updated.
  586. */
  587. static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
  588. bool only_one_period, int index)
  589. {
  590. struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
  591. int us;
  592. us = pmap_schedule(hsotg->hs_periodic_bitmap,
  593. DWC2_HS_PERIODIC_US_PER_UFRAME,
  594. DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
  595. qh->host_interval, trans_time->start_schedule_us,
  596. only_one_period);
  597. if (us < 0)
  598. return us;
  599. trans_time->start_schedule_us = us;
  600. return 0;
  601. }
  602. /**
  603. * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
  604. *
  605. * @hsotg: The HCD state structure for the DWC OTG controller.
  606. * @qh: QH for the periodic transfer.
  607. * @index: Transfer index
  608. */
  609. static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
  610. struct dwc2_qh *qh, int index)
  611. {
  612. struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
  613. pmap_unschedule(hsotg->hs_periodic_bitmap,
  614. DWC2_HS_PERIODIC_US_PER_UFRAME,
  615. DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
  616. qh->host_interval, trans_time->start_schedule_us);
  617. }
  618. /**
  619. * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
  620. *
  621. * This is the most complicated thing in USB. We have to find matching time
  622. * in both the global high speed schedule for the port and the low speed
  623. * schedule for the TT associated with the given device.
  624. *
  625. * Being here means that the host must be running in high speed mode and the
  626. * device is in low or full speed mode (and behind a hub).
  627. *
  628. * @hsotg: The HCD state structure for the DWC OTG controller.
  629. * @qh: QH for the periodic transfer.
  630. */
  631. static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
  632. struct dwc2_qh *qh)
  633. {
  634. int bytecount = qh->maxp_mult * qh->maxp;
  635. int ls_search_slice;
  636. int err = 0;
  637. int host_interval_in_sched;
  638. /*
  639. * The interval (how often to repeat) in the actual host schedule.
  640. * See pmap_schedule() for gcd() explanation.
  641. */
  642. host_interval_in_sched = gcd(qh->host_interval,
  643. DWC2_HS_SCHEDULE_UFRAMES);
  644. /*
  645. * We always try to find space in the low speed schedule first, then
  646. * try to find high speed time that matches. If we don't, we'll bump
  647. * up the place we start searching in the low speed schedule and try
  648. * again. To start we'll look right at the beginning of the low speed
  649. * schedule.
  650. *
  651. * Note that this will tend to front-load the high speed schedule.
  652. * We may eventually want to try to avoid this by either considering
  653. * both schedules together or doing some sort of round robin.
  654. */
  655. ls_search_slice = 0;
  656. while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
  657. int start_s_uframe;
  658. int ssplit_s_uframe;
  659. int second_s_uframe;
  660. int rel_uframe;
  661. int first_count;
  662. int middle_count;
  663. int end_count;
  664. int first_data_bytes;
  665. int other_data_bytes;
  666. int i;
  667. if (qh->schedule_low_speed) {
  668. err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
  669. /*
  670. * If we got an error here there's no other magic we
  671. * can do, so bail. All the looping above is only
  672. * helpful to redo things if we got a low speed slot
  673. * and then couldn't find a matching high speed slot.
  674. */
  675. if (err)
  676. return err;
  677. } else {
  678. /* Must be missing the tt structure? Why? */
  679. WARN_ON_ONCE(1);
  680. }
  681. /*
  682. * This will give us a number 0 - 7 if
  683. * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
  684. */
  685. start_s_uframe = qh->ls_start_schedule_slice /
  686. DWC2_SLICES_PER_UFRAME;
  687. /* Get a number that's always 0 - 7 */
  688. rel_uframe = (start_s_uframe % 8);
  689. /*
  690. * If we were going to start in uframe 7 then we would need to
  691. * issue a start split in uframe 6, which spec says is not OK.
  692. * Move on to the next full frame (assuming there is one).
  693. *
  694. * See 11.18.4 Host Split Transaction Scheduling Requirements
  695. * bullet 1.
  696. */
  697. if (rel_uframe == 7) {
  698. if (qh->schedule_low_speed)
  699. dwc2_ls_pmap_unschedule(hsotg, qh);
  700. ls_search_slice =
  701. (qh->ls_start_schedule_slice /
  702. DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
  703. DWC2_LS_PERIODIC_SLICES_PER_FRAME;
  704. continue;
  705. }
  706. /*
  707. * For ISOC in:
  708. * - start split (frame -1)
  709. * - complete split w/ data (frame +1)
  710. * - complete split w/ data (frame +2)
  711. * - ...
  712. * - complete split w/ data (frame +num_data_packets)
  713. * - complete split w/ data (frame +num_data_packets+1)
  714. * - complete split w/ data (frame +num_data_packets+2, max 8)
  715. * ...though if frame was "0" then max is 7...
  716. *
  717. * For ISOC out we might need to do:
  718. * - start split w/ data (frame -1)
  719. * - start split w/ data (frame +0)
  720. * - ...
  721. * - start split w/ data (frame +num_data_packets-2)
  722. *
  723. * For INTERRUPT in we might need to do:
  724. * - start split (frame -1)
  725. * - complete split w/ data (frame +1)
  726. * - complete split w/ data (frame +2)
  727. * - complete split w/ data (frame +3, max 8)
  728. *
  729. * For INTERRUPT out we might need to do:
  730. * - start split w/ data (frame -1)
  731. * - complete split (frame +1)
  732. * - complete split (frame +2)
  733. * - complete split (frame +3, max 8)
  734. *
  735. * Start adjusting!
  736. */
  737. ssplit_s_uframe = (start_s_uframe +
  738. host_interval_in_sched - 1) %
  739. host_interval_in_sched;
  740. if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
  741. second_s_uframe = start_s_uframe;
  742. else
  743. second_s_uframe = start_s_uframe + 1;
  744. /* First data transfer might not be all 188 bytes. */
  745. first_data_bytes = 188 -
  746. DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
  747. DWC2_SLICES_PER_UFRAME),
  748. DWC2_SLICES_PER_UFRAME);
  749. if (first_data_bytes > bytecount)
  750. first_data_bytes = bytecount;
  751. other_data_bytes = bytecount - first_data_bytes;
  752. /*
  753. * For now, skip OUT xfers where first xfer is partial
  754. *
  755. * Main dwc2 code assumes:
  756. * - INT transfers never get split in two.
  757. * - ISOC transfers can always transfer 188 bytes the first
  758. * time.
  759. *
  760. * Until that code is fixed, try again if the first transfer
  761. * couldn't transfer everything.
  762. *
  763. * This code can be removed if/when the rest of dwc2 handles
  764. * the above cases. Until it's fixed we just won't be able
  765. * to schedule quite as tightly.
  766. */
  767. if (!qh->ep_is_in &&
  768. (first_data_bytes != min_t(int, 188, bytecount))) {
  769. dwc2_sch_dbg(hsotg,
  770. "QH=%p avoiding broken 1st xfer (%d, %d)\n",
  771. qh, first_data_bytes, bytecount);
  772. if (qh->schedule_low_speed)
  773. dwc2_ls_pmap_unschedule(hsotg, qh);
  774. ls_search_slice = (start_s_uframe + 1) *
  775. DWC2_SLICES_PER_UFRAME;
  776. continue;
  777. }
  778. /* Start by assuming transfers for the bytes */
  779. qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
  780. /*
  781. * Everything except ISOC OUT has extra transfers. Rules are
  782. * complicated. See 11.18.4 Host Split Transaction Scheduling
  783. * Requirements bullet 3.
  784. */
  785. if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
  786. if (rel_uframe == 6)
  787. qh->num_hs_transfers += 2;
  788. else
  789. qh->num_hs_transfers += 3;
  790. if (qh->ep_is_in) {
  791. /*
  792. * First is start split, middle/end is data.
  793. * Allocate full data bytes for all data.
  794. */
  795. first_count = 4;
  796. middle_count = bytecount;
  797. end_count = bytecount;
  798. } else {
  799. /*
  800. * First is data, middle/end is complete.
  801. * First transfer and second can have data.
  802. * Rest should just have complete split.
  803. */
  804. first_count = first_data_bytes;
  805. middle_count = max_t(int, 4, other_data_bytes);
  806. end_count = 4;
  807. }
  808. } else {
  809. if (qh->ep_is_in) {
  810. int last;
  811. /* Account for the start split */
  812. qh->num_hs_transfers++;
  813. /* Calculate "L" value from spec */
  814. last = rel_uframe + qh->num_hs_transfers + 1;
  815. /* Start with basic case */
  816. if (last <= 6)
  817. qh->num_hs_transfers += 2;
  818. else
  819. qh->num_hs_transfers += 1;
  820. /* Adjust downwards */
  821. if (last >= 6 && rel_uframe == 0)
  822. qh->num_hs_transfers--;
  823. /* 1st = start; rest can contain data */
  824. first_count = 4;
  825. middle_count = min_t(int, 188, bytecount);
  826. end_count = middle_count;
  827. } else {
  828. /* All contain data, last might be smaller */
  829. first_count = first_data_bytes;
  830. middle_count = min_t(int, 188,
  831. other_data_bytes);
  832. end_count = other_data_bytes % 188;
  833. }
  834. }
  835. /* Assign durations per uFrame */
  836. qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
  837. for (i = 1; i < qh->num_hs_transfers - 1; i++)
  838. qh->hs_transfers[i].duration_us =
  839. HS_USECS_ISO(middle_count);
  840. if (qh->num_hs_transfers > 1)
  841. qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
  842. HS_USECS_ISO(end_count);
  843. /*
  844. * Assign start us. The call below to dwc2_hs_pmap_schedule()
  845. * will start with these numbers but may adjust within the same
  846. * microframe.
  847. */
  848. qh->hs_transfers[0].start_schedule_us =
  849. ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
  850. for (i = 1; i < qh->num_hs_transfers; i++)
  851. qh->hs_transfers[i].start_schedule_us =
  852. ((second_s_uframe + i - 1) %
  853. DWC2_HS_SCHEDULE_UFRAMES) *
  854. DWC2_HS_PERIODIC_US_PER_UFRAME;
  855. /* Try to schedule with filled in hs_transfers above */
  856. for (i = 0; i < qh->num_hs_transfers; i++) {
  857. err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
  858. if (err)
  859. break;
  860. }
  861. /* If we scheduled all w/out breaking out then we're all good */
  862. if (i == qh->num_hs_transfers)
  863. break;
  864. for (; i >= 0; i--)
  865. dwc2_hs_pmap_unschedule(hsotg, qh, i);
  866. if (qh->schedule_low_speed)
  867. dwc2_ls_pmap_unschedule(hsotg, qh);
  868. /* Try again starting in the next microframe */
  869. ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
  870. }
  871. if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
  872. return -ENOSPC;
  873. return 0;
  874. }
  875. /**
  876. * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
  877. *
  878. * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
  879. * interface.
  880. *
  881. * @hsotg: The HCD state structure for the DWC OTG controller.
  882. * @qh: QH for the periodic transfer.
  883. */
  884. static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  885. {
  886. /* In non-split host and device time are the same */
  887. WARN_ON(qh->host_us != qh->device_us);
  888. WARN_ON(qh->host_interval != qh->device_interval);
  889. WARN_ON(qh->num_hs_transfers != 1);
  890. /* We'll have one transfer; init start to 0 before calling scheduler */
  891. qh->hs_transfers[0].start_schedule_us = 0;
  892. qh->hs_transfers[0].duration_us = qh->host_us;
  893. return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
  894. }
  895. /**
  896. * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
  897. *
  898. * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
  899. * interface.
  900. *
  901. * @hsotg: The HCD state structure for the DWC OTG controller.
  902. * @qh: QH for the periodic transfer.
  903. */
  904. static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  905. {
  906. /* In non-split host and device time are the same */
  907. WARN_ON(qh->host_us != qh->device_us);
  908. WARN_ON(qh->host_interval != qh->device_interval);
  909. WARN_ON(!qh->schedule_low_speed);
  910. /* Run on the main low speed schedule (no split = no hub = no TT) */
  911. return dwc2_ls_pmap_schedule(hsotg, qh, 0);
  912. }
  913. /**
  914. * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
  915. *
  916. * Calls one of the 3 sub-function depending on what type of transfer this QH
  917. * is for. Also adds some printing.
  918. *
  919. * @hsotg: The HCD state structure for the DWC OTG controller.
  920. * @qh: QH for the periodic transfer.
  921. */
  922. static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  923. {
  924. int ret;
  925. if (qh->dev_speed == USB_SPEED_HIGH)
  926. ret = dwc2_uframe_schedule_hs(hsotg, qh);
  927. else if (!qh->do_split)
  928. ret = dwc2_uframe_schedule_ls(hsotg, qh);
  929. else
  930. ret = dwc2_uframe_schedule_split(hsotg, qh);
  931. if (ret)
  932. dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
  933. else
  934. dwc2_qh_schedule_print(hsotg, qh);
  935. return ret;
  936. }
  937. /**
  938. * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
  939. *
  940. * @hsotg: The HCD state structure for the DWC OTG controller.
  941. * @qh: QH for the periodic transfer.
  942. */
  943. static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  944. {
  945. int i;
  946. for (i = 0; i < qh->num_hs_transfers; i++)
  947. dwc2_hs_pmap_unschedule(hsotg, qh, i);
  948. if (qh->schedule_low_speed)
  949. dwc2_ls_pmap_unschedule(hsotg, qh);
  950. dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
  951. }
  952. /**
  953. * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
  954. *
  955. * Takes a qh that has already been scheduled (which means we know we have the
  956. * bandwdith reserved for us) and set the next_active_frame and the
  957. * start_active_frame.
  958. *
  959. * This is expected to be called on qh's that weren't previously actively
  960. * running. It just picks the next frame that we can fit into without any
  961. * thought about the past.
  962. *
  963. * @hsotg: The HCD state structure for the DWC OTG controller
  964. * @qh: QH for a periodic endpoint
  965. *
  966. */
  967. static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  968. {
  969. u16 frame_number;
  970. u16 earliest_frame;
  971. u16 next_active_frame;
  972. u16 relative_frame;
  973. u16 interval;
  974. /*
  975. * Use the real frame number rather than the cached value as of the
  976. * last SOF to give us a little extra slop.
  977. */
  978. frame_number = dwc2_hcd_get_frame_number(hsotg);
  979. /*
  980. * We wouldn't want to start any earlier than the next frame just in
  981. * case the frame number ticks as we're doing this calculation.
  982. *
  983. * NOTE: if we could quantify how long till we actually get scheduled
  984. * we might be able to avoid the "+ 1" by looking at the upper part of
  985. * HFNUM (the FRREM field). For now we'll just use the + 1 though.
  986. */
  987. earliest_frame = dwc2_frame_num_inc(frame_number, 1);
  988. next_active_frame = earliest_frame;
  989. /* Get the "no microframe schduler" out of the way... */
  990. if (!hsotg->params.uframe_sched) {
  991. if (qh->do_split)
  992. /* Splits are active at microframe 0 minus 1 */
  993. next_active_frame |= 0x7;
  994. goto exit;
  995. }
  996. if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
  997. /*
  998. * We're either at high speed or we're doing a split (which
  999. * means we're talking high speed to a hub). In any case
  1000. * the first frame should be based on when the first scheduled
  1001. * event is.
  1002. */
  1003. WARN_ON(qh->num_hs_transfers < 1);
  1004. relative_frame = qh->hs_transfers[0].start_schedule_us /
  1005. DWC2_HS_PERIODIC_US_PER_UFRAME;
  1006. /* Adjust interval as per high speed schedule */
  1007. interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
  1008. } else {
  1009. /*
  1010. * Low or full speed directly on dwc2. Just about the same
  1011. * as high speed but on a different schedule and with slightly
  1012. * different adjustments. Note that this works because when
  1013. * the host and device are both low speed then frames in the
  1014. * controller tick at low speed.
  1015. */
  1016. relative_frame = qh->ls_start_schedule_slice /
  1017. DWC2_LS_PERIODIC_SLICES_PER_FRAME;
  1018. interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
  1019. }
  1020. /* Scheduler messed up if frame is past interval */
  1021. WARN_ON(relative_frame >= interval);
  1022. /*
  1023. * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
  1024. * done the gcd(), so it's safe to move to the beginning of the current
  1025. * interval like this.
  1026. *
  1027. * After this we might be before earliest_frame, but don't worry,
  1028. * we'll fix it...
  1029. */
  1030. next_active_frame = (next_active_frame / interval) * interval;
  1031. /*
  1032. * Actually choose to start at the frame number we've been
  1033. * scheduled for.
  1034. */
  1035. next_active_frame = dwc2_frame_num_inc(next_active_frame,
  1036. relative_frame);
  1037. /*
  1038. * We actually need 1 frame before since the next_active_frame is
  1039. * the frame number we'll be put on the ready list and we won't be on
  1040. * the bus until 1 frame later.
  1041. */
  1042. next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
  1043. /*
  1044. * By now we might actually be before the earliest_frame. Let's move
  1045. * up intervals until we're not.
  1046. */
  1047. while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
  1048. next_active_frame = dwc2_frame_num_inc(next_active_frame,
  1049. interval);
  1050. exit:
  1051. qh->next_active_frame = next_active_frame;
  1052. qh->start_active_frame = next_active_frame;
  1053. dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
  1054. qh, frame_number, qh->next_active_frame);
  1055. }
  1056. /**
  1057. * dwc2_do_reserve() - Make a periodic reservation
  1058. *
  1059. * Try to allocate space in the periodic schedule. Depending on parameters
  1060. * this might use the microframe scheduler or the dumb scheduler.
  1061. *
  1062. * @hsotg: The HCD state structure for the DWC OTG controller
  1063. * @qh: QH for the periodic transfer.
  1064. *
  1065. * Returns: 0 upon success; error upon failure.
  1066. */
  1067. static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  1068. {
  1069. int status;
  1070. if (hsotg->params.uframe_sched) {
  1071. status = dwc2_uframe_schedule(hsotg, qh);
  1072. } else {
  1073. status = dwc2_periodic_channel_available(hsotg);
  1074. if (status) {
  1075. dev_info(hsotg->dev,
  1076. "%s: No host channel available for periodic transfer\n",
  1077. __func__);
  1078. return status;
  1079. }
  1080. status = dwc2_check_periodic_bandwidth(hsotg, qh);
  1081. }
  1082. if (status) {
  1083. dev_dbg(hsotg->dev,
  1084. "%s: Insufficient periodic bandwidth for periodic transfer\n",
  1085. __func__);
  1086. return status;
  1087. }
  1088. if (!hsotg->params.uframe_sched)
  1089. /* Reserve periodic channel */
  1090. hsotg->periodic_channels++;
  1091. /* Update claimed usecs per (micro)frame */
  1092. hsotg->periodic_usecs += qh->host_us;
  1093. dwc2_pick_first_frame(hsotg, qh);
  1094. return 0;
  1095. }
  1096. /**
  1097. * dwc2_do_unreserve() - Actually release the periodic reservation
  1098. *
  1099. * This function actually releases the periodic bandwidth that was reserved
  1100. * by the given qh.
  1101. *
  1102. * @hsotg: The HCD state structure for the DWC OTG controller
  1103. * @qh: QH for the periodic transfer.
  1104. */
  1105. static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  1106. {
  1107. assert_spin_locked(&hsotg->lock);
  1108. WARN_ON(!qh->unreserve_pending);
  1109. /* No more unreserve pending--we're doing it */
  1110. qh->unreserve_pending = false;
  1111. if (WARN_ON(!list_empty(&qh->qh_list_entry)))
  1112. list_del_init(&qh->qh_list_entry);
  1113. /* Update claimed usecs per (micro)frame */
  1114. hsotg->periodic_usecs -= qh->host_us;
  1115. if (hsotg->params.uframe_sched) {
  1116. dwc2_uframe_unschedule(hsotg, qh);
  1117. } else {
  1118. /* Release periodic channel reservation */
  1119. hsotg->periodic_channels--;
  1120. }
  1121. }
  1122. /**
  1123. * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
  1124. *
  1125. * According to the kernel doc for usb_submit_urb() (specifically the part about
  1126. * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
  1127. * long as a device driver keeps submitting. Since we're using HCD_BH to give
  1128. * back the URB we need to give the driver a little bit of time before we
  1129. * release the reservation. This worker is called after the appropriate
  1130. * delay.
  1131. *
  1132. * @t: Address to a qh unreserve_work.
  1133. */
  1134. static void dwc2_unreserve_timer_fn(struct timer_list *t)
  1135. {
  1136. struct dwc2_qh *qh = from_timer(qh, t, unreserve_timer);
  1137. struct dwc2_hsotg *hsotg = qh->hsotg;
  1138. unsigned long flags;
  1139. /*
  1140. * Wait for the lock, or for us to be scheduled again. We
  1141. * could be scheduled again if:
  1142. * - We started executing but didn't get the lock yet.
  1143. * - A new reservation came in, but cancel didn't take effect
  1144. * because we already started executing.
  1145. * - The timer has been kicked again.
  1146. * In that case cancel and wait for the next call.
  1147. */
  1148. while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
  1149. if (timer_pending(&qh->unreserve_timer))
  1150. return;
  1151. }
  1152. /*
  1153. * Might be no more unreserve pending if:
  1154. * - We started executing but didn't get the lock yet.
  1155. * - A new reservation came in, but cancel didn't take effect
  1156. * because we already started executing.
  1157. *
  1158. * We can't put this in the loop above because unreserve_pending needs
  1159. * to be accessed under lock, so we can only check it once we got the
  1160. * lock.
  1161. */
  1162. if (qh->unreserve_pending)
  1163. dwc2_do_unreserve(hsotg, qh);
  1164. spin_unlock_irqrestore(&hsotg->lock, flags);
  1165. }
  1166. /**
  1167. * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
  1168. * host channel is large enough to handle the maximum data transfer in a single
  1169. * (micro)frame for a periodic transfer
  1170. *
  1171. * @hsotg: The HCD state structure for the DWC OTG controller
  1172. * @qh: QH for a periodic endpoint
  1173. *
  1174. * Return: 0 if successful, negative error code otherwise
  1175. */
  1176. static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
  1177. struct dwc2_qh *qh)
  1178. {
  1179. u32 max_xfer_size;
  1180. u32 max_channel_xfer_size;
  1181. int status = 0;
  1182. max_xfer_size = qh->maxp * qh->maxp_mult;
  1183. max_channel_xfer_size = hsotg->params.max_transfer_size;
  1184. if (max_xfer_size > max_channel_xfer_size) {
  1185. dev_err(hsotg->dev,
  1186. "%s: Periodic xfer length %d > max xfer length for channel %d\n",
  1187. __func__, max_xfer_size, max_channel_xfer_size);
  1188. status = -ENOSPC;
  1189. }
  1190. return status;
  1191. }
  1192. /**
  1193. * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
  1194. * the periodic schedule
  1195. *
  1196. * @hsotg: The HCD state structure for the DWC OTG controller
  1197. * @qh: QH for the periodic transfer. The QH should already contain the
  1198. * scheduling information.
  1199. *
  1200. * Return: 0 if successful, negative error code otherwise
  1201. */
  1202. static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  1203. {
  1204. int status;
  1205. status = dwc2_check_max_xfer_size(hsotg, qh);
  1206. if (status) {
  1207. dev_dbg(hsotg->dev,
  1208. "%s: Channel max transfer size too small for periodic transfer\n",
  1209. __func__);
  1210. return status;
  1211. }
  1212. /* Cancel pending unreserve; if canceled OK, unreserve was pending */
  1213. if (del_timer(&qh->unreserve_timer))
  1214. WARN_ON(!qh->unreserve_pending);
  1215. /*
  1216. * Only need to reserve if there's not an unreserve pending, since if an
  1217. * unreserve is pending then by definition our old reservation is still
  1218. * valid. Unreserve might still be pending even if we didn't cancel if
  1219. * dwc2_unreserve_timer_fn() already started. Code in the timer handles
  1220. * that case.
  1221. */
  1222. if (!qh->unreserve_pending) {
  1223. status = dwc2_do_reserve(hsotg, qh);
  1224. if (status)
  1225. return status;
  1226. } else {
  1227. /*
  1228. * It might have been a while, so make sure that frame_number
  1229. * is still good. Note: we could also try to use the similar
  1230. * dwc2_next_periodic_start() but that schedules much more
  1231. * tightly and we might need to hurry and queue things up.
  1232. */
  1233. if (dwc2_frame_num_le(qh->next_active_frame,
  1234. hsotg->frame_number))
  1235. dwc2_pick_first_frame(hsotg, qh);
  1236. }
  1237. qh->unreserve_pending = 0;
  1238. if (hsotg->params.dma_desc_enable)
  1239. /* Don't rely on SOF and start in ready schedule */
  1240. list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
  1241. else
  1242. /* Always start in inactive schedule */
  1243. list_add_tail(&qh->qh_list_entry,
  1244. &hsotg->periodic_sched_inactive);
  1245. return 0;
  1246. }
  1247. /**
  1248. * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
  1249. * from the periodic schedule
  1250. *
  1251. * @hsotg: The HCD state structure for the DWC OTG controller
  1252. * @qh: QH for the periodic transfer
  1253. */
  1254. static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
  1255. struct dwc2_qh *qh)
  1256. {
  1257. bool did_modify;
  1258. assert_spin_locked(&hsotg->lock);
  1259. /*
  1260. * Schedule the unreserve to happen in a little bit. Cases here:
  1261. * - Unreserve worker might be sitting there waiting to grab the lock.
  1262. * In this case it will notice it's been schedule again and will
  1263. * quit.
  1264. * - Unreserve worker might not be scheduled.
  1265. *
  1266. * We should never already be scheduled since dwc2_schedule_periodic()
  1267. * should have canceled the scheduled unreserve timer (hence the
  1268. * warning on did_modify).
  1269. *
  1270. * We add + 1 to the timer to guarantee that at least 1 jiffy has
  1271. * passed (otherwise if the jiffy counter might tick right after we
  1272. * read it and we'll get no delay).
  1273. */
  1274. did_modify = mod_timer(&qh->unreserve_timer,
  1275. jiffies + DWC2_UNRESERVE_DELAY + 1);
  1276. WARN_ON(did_modify);
  1277. qh->unreserve_pending = 1;
  1278. list_del_init(&qh->qh_list_entry);
  1279. }
  1280. /**
  1281. * dwc2_wait_timer_fn() - Timer function to re-queue after waiting
  1282. *
  1283. * As per the spec, a NAK indicates that "a function is temporarily unable to
  1284. * transmit or receive data, but will eventually be able to do so without need
  1285. * of host intervention".
  1286. *
  1287. * That means that when we encounter a NAK we're supposed to retry.
  1288. *
  1289. * ...but if we retry right away (from the interrupt handler that saw the NAK)
  1290. * then we can end up with an interrupt storm (if the other side keeps NAKing
  1291. * us) because on slow enough CPUs it could take us longer to get out of the
  1292. * interrupt routine than it takes for the device to send another NAK. That
  1293. * leads to a constant stream of NAK interrupts and the CPU locks.
  1294. *
  1295. * ...so instead of retrying right away in the case of a NAK we'll set a timer
  1296. * to retry some time later. This function handles that timer and moves the
  1297. * qh back to the "inactive" list, then queues transactions.
  1298. *
  1299. * @t: Pointer to wait_timer in a qh.
  1300. *
  1301. * Return: HRTIMER_NORESTART to not automatically restart this timer.
  1302. */
  1303. static enum hrtimer_restart dwc2_wait_timer_fn(struct hrtimer *t)
  1304. {
  1305. struct dwc2_qh *qh = container_of(t, struct dwc2_qh, wait_timer);
  1306. struct dwc2_hsotg *hsotg = qh->hsotg;
  1307. unsigned long flags;
  1308. spin_lock_irqsave(&hsotg->lock, flags);
  1309. /*
  1310. * We'll set wait_timer_cancel to true if we want to cancel this
  1311. * operation in dwc2_hcd_qh_unlink().
  1312. */
  1313. if (!qh->wait_timer_cancel) {
  1314. enum dwc2_transaction_type tr_type;
  1315. qh->want_wait = false;
  1316. list_move(&qh->qh_list_entry,
  1317. &hsotg->non_periodic_sched_inactive);
  1318. tr_type = dwc2_hcd_select_transactions(hsotg);
  1319. if (tr_type != DWC2_TRANSACTION_NONE)
  1320. dwc2_hcd_queue_transactions(hsotg, tr_type);
  1321. }
  1322. spin_unlock_irqrestore(&hsotg->lock, flags);
  1323. return HRTIMER_NORESTART;
  1324. }
  1325. /**
  1326. * dwc2_qh_init() - Initializes a QH structure
  1327. *
  1328. * @hsotg: The HCD state structure for the DWC OTG controller
  1329. * @qh: The QH to init
  1330. * @urb: Holds the information about the device/endpoint needed to initialize
  1331. * the QH
  1332. * @mem_flags: Flags for allocating memory.
  1333. */
  1334. static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
  1335. struct dwc2_hcd_urb *urb, gfp_t mem_flags)
  1336. {
  1337. int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
  1338. u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
  1339. bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
  1340. bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
  1341. bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
  1342. u32 hprt = dwc2_readl(hsotg, HPRT0);
  1343. u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
  1344. bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
  1345. dev_speed != USB_SPEED_HIGH);
  1346. int maxp = dwc2_hcd_get_maxp(&urb->pipe_info);
  1347. int maxp_mult = dwc2_hcd_get_maxp_mult(&urb->pipe_info);
  1348. int bytecount = maxp_mult * maxp;
  1349. char *speed, *type;
  1350. /* Initialize QH */
  1351. qh->hsotg = hsotg;
  1352. timer_setup(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 0);
  1353. hrtimer_init(&qh->wait_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
  1354. qh->wait_timer.function = &dwc2_wait_timer_fn;
  1355. qh->ep_type = ep_type;
  1356. qh->ep_is_in = ep_is_in;
  1357. qh->data_toggle = DWC2_HC_PID_DATA0;
  1358. qh->maxp = maxp;
  1359. qh->maxp_mult = maxp_mult;
  1360. INIT_LIST_HEAD(&qh->qtd_list);
  1361. INIT_LIST_HEAD(&qh->qh_list_entry);
  1362. qh->do_split = do_split;
  1363. qh->dev_speed = dev_speed;
  1364. if (ep_is_int || ep_is_isoc) {
  1365. /* Compute scheduling parameters once and save them */
  1366. int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
  1367. struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
  1368. mem_flags,
  1369. &qh->ttport);
  1370. int device_ns;
  1371. qh->dwc_tt = dwc_tt;
  1372. qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
  1373. ep_is_isoc, bytecount));
  1374. device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
  1375. ep_is_isoc, bytecount);
  1376. if (do_split && dwc_tt)
  1377. device_ns += dwc_tt->usb_tt->think_time;
  1378. qh->device_us = NS_TO_US(device_ns);
  1379. qh->device_interval = urb->interval;
  1380. qh->host_interval = urb->interval * (do_split ? 8 : 1);
  1381. /*
  1382. * Schedule low speed if we're running the host in low or
  1383. * full speed OR if we've got a "TT" to deal with to access this
  1384. * device.
  1385. */
  1386. qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
  1387. dwc_tt;
  1388. if (do_split) {
  1389. /* We won't know num transfers until we schedule */
  1390. qh->num_hs_transfers = -1;
  1391. } else if (dev_speed == USB_SPEED_HIGH) {
  1392. qh->num_hs_transfers = 1;
  1393. } else {
  1394. qh->num_hs_transfers = 0;
  1395. }
  1396. /* We'll schedule later when we have something to do */
  1397. }
  1398. switch (dev_speed) {
  1399. case USB_SPEED_LOW:
  1400. speed = "low";
  1401. break;
  1402. case USB_SPEED_FULL:
  1403. speed = "full";
  1404. break;
  1405. case USB_SPEED_HIGH:
  1406. speed = "high";
  1407. break;
  1408. default:
  1409. speed = "?";
  1410. break;
  1411. }
  1412. switch (qh->ep_type) {
  1413. case USB_ENDPOINT_XFER_ISOC:
  1414. type = "isochronous";
  1415. break;
  1416. case USB_ENDPOINT_XFER_INT:
  1417. type = "interrupt";
  1418. break;
  1419. case USB_ENDPOINT_XFER_CONTROL:
  1420. type = "control";
  1421. break;
  1422. case USB_ENDPOINT_XFER_BULK:
  1423. type = "bulk";
  1424. break;
  1425. default:
  1426. type = "?";
  1427. break;
  1428. }
  1429. dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
  1430. speed, bytecount);
  1431. dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
  1432. dwc2_hcd_get_dev_addr(&urb->pipe_info),
  1433. dwc2_hcd_get_ep_num(&urb->pipe_info),
  1434. ep_is_in ? "IN" : "OUT");
  1435. if (ep_is_int || ep_is_isoc) {
  1436. dwc2_sch_dbg(hsotg,
  1437. "QH=%p ...duration: host=%d us, device=%d us\n",
  1438. qh, qh->host_us, qh->device_us);
  1439. dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
  1440. qh, qh->host_interval, qh->device_interval);
  1441. if (qh->schedule_low_speed)
  1442. dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
  1443. qh, dwc2_get_ls_map(hsotg, qh));
  1444. }
  1445. }
  1446. /**
  1447. * dwc2_hcd_qh_create() - Allocates and initializes a QH
  1448. *
  1449. * @hsotg: The HCD state structure for the DWC OTG controller
  1450. * @urb: Holds the information about the device/endpoint needed
  1451. * to initialize the QH
  1452. * @mem_flags: Flags for allocating memory.
  1453. *
  1454. * Return: Pointer to the newly allocated QH, or NULL on error
  1455. */
  1456. struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
  1457. struct dwc2_hcd_urb *urb,
  1458. gfp_t mem_flags)
  1459. {
  1460. struct dwc2_qh *qh;
  1461. if (!urb->priv)
  1462. return NULL;
  1463. /* Allocate memory */
  1464. qh = kzalloc(sizeof(*qh), mem_flags);
  1465. if (!qh)
  1466. return NULL;
  1467. dwc2_qh_init(hsotg, qh, urb, mem_flags);
  1468. if (hsotg->params.dma_desc_enable &&
  1469. dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
  1470. dwc2_hcd_qh_free(hsotg, qh);
  1471. return NULL;
  1472. }
  1473. return qh;
  1474. }
  1475. /**
  1476. * dwc2_hcd_qh_free() - Frees the QH
  1477. *
  1478. * @hsotg: HCD instance
  1479. * @qh: The QH to free
  1480. *
  1481. * QH should already be removed from the list. QTD list should already be empty
  1482. * if called from URB Dequeue.
  1483. *
  1484. * Must NOT be called with interrupt disabled or spinlock held
  1485. */
  1486. void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  1487. {
  1488. /* Make sure any unreserve work is finished. */
  1489. if (del_timer_sync(&qh->unreserve_timer)) {
  1490. unsigned long flags;
  1491. spin_lock_irqsave(&hsotg->lock, flags);
  1492. dwc2_do_unreserve(hsotg, qh);
  1493. spin_unlock_irqrestore(&hsotg->lock, flags);
  1494. }
  1495. /*
  1496. * We don't have the lock so we can safely wait until the wait timer
  1497. * finishes. Of course, at this point in time we'd better have set
  1498. * wait_timer_active to false so if this timer was still pending it
  1499. * won't do anything anyway, but we want it to finish before we free
  1500. * memory.
  1501. */
  1502. hrtimer_cancel(&qh->wait_timer);
  1503. dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
  1504. if (qh->desc_list)
  1505. dwc2_hcd_qh_free_ddma(hsotg, qh);
  1506. else if (hsotg->unaligned_cache && qh->dw_align_buf)
  1507. kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf);
  1508. kfree(qh);
  1509. }
  1510. /**
  1511. * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
  1512. * schedule if it is not already in the schedule. If the QH is already in
  1513. * the schedule, no action is taken.
  1514. *
  1515. * @hsotg: The HCD state structure for the DWC OTG controller
  1516. * @qh: The QH to add
  1517. *
  1518. * Return: 0 if successful, negative error code otherwise
  1519. */
  1520. int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  1521. {
  1522. int status;
  1523. u32 intr_mask;
  1524. ktime_t delay;
  1525. if (dbg_qh(qh))
  1526. dev_vdbg(hsotg->dev, "%s()\n", __func__);
  1527. if (!list_empty(&qh->qh_list_entry))
  1528. /* QH already in a schedule */
  1529. return 0;
  1530. /* Add the new QH to the appropriate schedule */
  1531. if (dwc2_qh_is_non_per(qh)) {
  1532. /* Schedule right away */
  1533. qh->start_active_frame = hsotg->frame_number;
  1534. qh->next_active_frame = qh->start_active_frame;
  1535. if (qh->want_wait) {
  1536. list_add_tail(&qh->qh_list_entry,
  1537. &hsotg->non_periodic_sched_waiting);
  1538. qh->wait_timer_cancel = false;
  1539. delay = ktime_set(0, DWC2_RETRY_WAIT_DELAY);
  1540. hrtimer_start(&qh->wait_timer, delay, HRTIMER_MODE_REL);
  1541. } else {
  1542. list_add_tail(&qh->qh_list_entry,
  1543. &hsotg->non_periodic_sched_inactive);
  1544. }
  1545. return 0;
  1546. }
  1547. status = dwc2_schedule_periodic(hsotg, qh);
  1548. if (status)
  1549. return status;
  1550. if (!hsotg->periodic_qh_count) {
  1551. intr_mask = dwc2_readl(hsotg, GINTMSK);
  1552. intr_mask |= GINTSTS_SOF;
  1553. dwc2_writel(hsotg, intr_mask, GINTMSK);
  1554. }
  1555. hsotg->periodic_qh_count++;
  1556. return 0;
  1557. }
  1558. /**
  1559. * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
  1560. * schedule. Memory is not freed.
  1561. *
  1562. * @hsotg: The HCD state structure
  1563. * @qh: QH to remove from schedule
  1564. */
  1565. void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
  1566. {
  1567. u32 intr_mask;
  1568. dev_vdbg(hsotg->dev, "%s()\n", __func__);
  1569. /* If the wait_timer is pending, this will stop it from acting */
  1570. qh->wait_timer_cancel = true;
  1571. if (list_empty(&qh->qh_list_entry))
  1572. /* QH is not in a schedule */
  1573. return;
  1574. if (dwc2_qh_is_non_per(qh)) {
  1575. if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
  1576. hsotg->non_periodic_qh_ptr =
  1577. hsotg->non_periodic_qh_ptr->next;
  1578. list_del_init(&qh->qh_list_entry);
  1579. return;
  1580. }
  1581. dwc2_deschedule_periodic(hsotg, qh);
  1582. hsotg->periodic_qh_count--;
  1583. if (!hsotg->periodic_qh_count &&
  1584. !hsotg->params.dma_desc_enable) {
  1585. intr_mask = dwc2_readl(hsotg, GINTMSK);
  1586. intr_mask &= ~GINTSTS_SOF;
  1587. dwc2_writel(hsotg, intr_mask, GINTMSK);
  1588. }
  1589. }
  1590. /**
  1591. * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
  1592. *
  1593. * This is called for setting next_active_frame for periodic splits for all but
  1594. * the first packet of the split. Confusing? I thought so...
  1595. *
  1596. * Periodic splits are single low/full speed transfers that we end up splitting
  1597. * up into several high speed transfers. They always fit into one full (1 ms)
  1598. * frame but might be split over several microframes (125 us each). We to put
  1599. * each of the parts on a very specific high speed frame.
  1600. *
  1601. * This function figures out where the next active uFrame needs to be.
  1602. *
  1603. * @hsotg: The HCD state structure
  1604. * @qh: QH for the periodic transfer.
  1605. * @frame_number: The current frame number.
  1606. *
  1607. * Return: number missed by (or 0 if we didn't miss).
  1608. */
  1609. static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
  1610. struct dwc2_qh *qh, u16 frame_number)
  1611. {
  1612. u16 old_frame = qh->next_active_frame;
  1613. u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
  1614. int missed = 0;
  1615. u16 incr;
  1616. /*
  1617. * See dwc2_uframe_schedule_split() for split scheduling.
  1618. *
  1619. * Basically: increment 1 normally, but 2 right after the start split
  1620. * (except for ISOC out).
  1621. */
  1622. if (old_frame == qh->start_active_frame &&
  1623. !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
  1624. incr = 2;
  1625. else
  1626. incr = 1;
  1627. qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
  1628. /*
  1629. * Note that it's OK for frame_number to be 1 frame past
  1630. * next_active_frame. Remember that next_active_frame is supposed to
  1631. * be 1 frame _before_ when we want to be scheduled. If we're 1 frame
  1632. * past it just means schedule ASAP.
  1633. *
  1634. * It's _not_ OK, however, if we're more than one frame past.
  1635. */
  1636. if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
  1637. /*
  1638. * OOPS, we missed. That's actually pretty bad since
  1639. * the hub will be unhappy; try ASAP I guess.
  1640. */
  1641. missed = dwc2_frame_num_dec(prev_frame_number,
  1642. qh->next_active_frame);
  1643. qh->next_active_frame = frame_number;
  1644. }
  1645. return missed;
  1646. }
  1647. /**
  1648. * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
  1649. *
  1650. * This is called for setting next_active_frame for a periodic transfer for
  1651. * all cases other than midway through a periodic split. This will also update
  1652. * start_active_frame.
  1653. *
  1654. * Since we _always_ keep start_active_frame as the start of the previous
  1655. * transfer this is normally pretty easy: we just add our interval to
  1656. * start_active_frame and we've got our answer.
  1657. *
  1658. * The tricks come into play if we miss. In that case we'll look for the next
  1659. * slot we can fit into.
  1660. *
  1661. * @hsotg: The HCD state structure
  1662. * @qh: QH for the periodic transfer.
  1663. * @frame_number: The current frame number.
  1664. *
  1665. * Return: number missed by (or 0 if we didn't miss).
  1666. */
  1667. static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
  1668. struct dwc2_qh *qh, u16 frame_number)
  1669. {
  1670. int missed = 0;
  1671. u16 interval = qh->host_interval;
  1672. u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
  1673. qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
  1674. interval);
  1675. /*
  1676. * The dwc2_frame_num_gt() function used below won't work terribly well
  1677. * with if we just incremented by a really large intervals since the
  1678. * frame counter only goes to 0x3fff. It's terribly unlikely that we
  1679. * will have missed in this case anyway. Just go to exit. If we want
  1680. * to try to do better we'll need to keep track of a bigger counter
  1681. * somewhere in the driver and handle overflows.
  1682. */
  1683. if (interval >= 0x1000)
  1684. goto exit;
  1685. /*
  1686. * Test for misses, which is when it's too late to schedule.
  1687. *
  1688. * A few things to note:
  1689. * - We compare against prev_frame_number since start_active_frame
  1690. * and next_active_frame are always 1 frame before we want things
  1691. * to be active and we assume we can still get scheduled in the
  1692. * current frame number.
  1693. * - It's possible for start_active_frame (now incremented) to be
  1694. * next_active_frame if we got an EO MISS (even_odd miss) which
  1695. * basically means that we detected there wasn't enough time for
  1696. * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
  1697. * at the last second. We want to make sure we don't schedule
  1698. * another transfer for the same frame. My test webcam doesn't seem
  1699. * terribly upset by missing a transfer but really doesn't like when
  1700. * we do two transfers in the same frame.
  1701. * - Some misses are expected. Specifically, in order to work
  1702. * perfectly dwc2 really needs quite spectacular interrupt latency
  1703. * requirements. It needs to be able to handle its interrupts
  1704. * completely within 125 us of them being asserted. That not only
  1705. * means that the dwc2 interrupt handler needs to be fast but it
  1706. * means that nothing else in the system has to block dwc2 for a long
  1707. * time. We can help with the dwc2 parts of this, but it's hard to
  1708. * guarantee that a system will have interrupt latency < 125 us, so
  1709. * we have to be robust to some misses.
  1710. */
  1711. if (qh->start_active_frame == qh->next_active_frame ||
  1712. dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
  1713. u16 ideal_start = qh->start_active_frame;
  1714. int periods_in_map;
  1715. /*
  1716. * Adjust interval as per gcd with map size.
  1717. * See pmap_schedule() for more details here.
  1718. */
  1719. if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
  1720. periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
  1721. else
  1722. periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
  1723. interval = gcd(interval, periods_in_map);
  1724. do {
  1725. qh->start_active_frame = dwc2_frame_num_inc(
  1726. qh->start_active_frame, interval);
  1727. } while (dwc2_frame_num_gt(prev_frame_number,
  1728. qh->start_active_frame));
  1729. missed = dwc2_frame_num_dec(qh->start_active_frame,
  1730. ideal_start);
  1731. }
  1732. exit:
  1733. qh->next_active_frame = qh->start_active_frame;
  1734. return missed;
  1735. }
  1736. /*
  1737. * Deactivates a QH. For non-periodic QHs, removes the QH from the active
  1738. * non-periodic schedule. The QH is added to the inactive non-periodic
  1739. * schedule if any QTDs are still attached to the QH.
  1740. *
  1741. * For periodic QHs, the QH is removed from the periodic queued schedule. If
  1742. * there are any QTDs still attached to the QH, the QH is added to either the
  1743. * periodic inactive schedule or the periodic ready schedule and its next
  1744. * scheduled frame is calculated. The QH is placed in the ready schedule if
  1745. * the scheduled frame has been reached already. Otherwise it's placed in the
  1746. * inactive schedule. If there are no QTDs attached to the QH, the QH is
  1747. * completely removed from the periodic schedule.
  1748. */
  1749. void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
  1750. int sched_next_periodic_split)
  1751. {
  1752. u16 old_frame = qh->next_active_frame;
  1753. u16 frame_number;
  1754. int missed;
  1755. if (dbg_qh(qh))
  1756. dev_vdbg(hsotg->dev, "%s()\n", __func__);
  1757. if (dwc2_qh_is_non_per(qh)) {
  1758. dwc2_hcd_qh_unlink(hsotg, qh);
  1759. if (!list_empty(&qh->qtd_list))
  1760. /* Add back to inactive/waiting non-periodic schedule */
  1761. dwc2_hcd_qh_add(hsotg, qh);
  1762. return;
  1763. }
  1764. /*
  1765. * Use the real frame number rather than the cached value as of the
  1766. * last SOF just to get us a little closer to reality. Note that
  1767. * means we don't actually know if we've already handled the SOF
  1768. * interrupt for this frame.
  1769. */
  1770. frame_number = dwc2_hcd_get_frame_number(hsotg);
  1771. if (sched_next_periodic_split)
  1772. missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
  1773. else
  1774. missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
  1775. dwc2_sch_vdbg(hsotg,
  1776. "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
  1777. qh, sched_next_periodic_split, frame_number, old_frame,
  1778. qh->next_active_frame,
  1779. dwc2_frame_num_dec(qh->next_active_frame, old_frame),
  1780. missed, missed ? "MISS" : "");
  1781. if (list_empty(&qh->qtd_list)) {
  1782. dwc2_hcd_qh_unlink(hsotg, qh);
  1783. return;
  1784. }
  1785. /*
  1786. * Remove from periodic_sched_queued and move to
  1787. * appropriate queue
  1788. *
  1789. * Note: we purposely use the frame_number from the "hsotg" structure
  1790. * since we know SOF interrupt will handle future frames.
  1791. */
  1792. if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
  1793. list_move_tail(&qh->qh_list_entry,
  1794. &hsotg->periodic_sched_ready);
  1795. else
  1796. list_move_tail(&qh->qh_list_entry,
  1797. &hsotg->periodic_sched_inactive);
  1798. }
  1799. /**
  1800. * dwc2_hcd_qtd_init() - Initializes a QTD structure
  1801. *
  1802. * @qtd: The QTD to initialize
  1803. * @urb: The associated URB
  1804. */
  1805. void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
  1806. {
  1807. qtd->urb = urb;
  1808. if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
  1809. USB_ENDPOINT_XFER_CONTROL) {
  1810. /*
  1811. * The only time the QTD data toggle is used is on the data
  1812. * phase of control transfers. This phase always starts with
  1813. * DATA1.
  1814. */
  1815. qtd->data_toggle = DWC2_HC_PID_DATA1;
  1816. qtd->control_phase = DWC2_CONTROL_SETUP;
  1817. }
  1818. /* Start split */
  1819. qtd->complete_split = 0;
  1820. qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
  1821. qtd->isoc_split_offset = 0;
  1822. qtd->in_process = 0;
  1823. /* Store the qtd ptr in the urb to reference the QTD */
  1824. urb->qtd = qtd;
  1825. }
  1826. /**
  1827. * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
  1828. * Caller must hold driver lock.
  1829. *
  1830. * @hsotg: The DWC HCD structure
  1831. * @qtd: The QTD to add
  1832. * @qh: Queue head to add qtd to
  1833. *
  1834. * Return: 0 if successful, negative error code otherwise
  1835. *
  1836. * If the QH to which the QTD is added is not currently scheduled, it is placed
  1837. * into the proper schedule based on its EP type.
  1838. */
  1839. int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
  1840. struct dwc2_qh *qh)
  1841. {
  1842. int retval;
  1843. if (unlikely(!qh)) {
  1844. dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
  1845. retval = -EINVAL;
  1846. goto fail;
  1847. }
  1848. retval = dwc2_hcd_qh_add(hsotg, qh);
  1849. if (retval)
  1850. goto fail;
  1851. qtd->qh = qh;
  1852. list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
  1853. return 0;
  1854. fail:
  1855. return retval;
  1856. }