core_intr.c 24 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * core_intr.c - DesignWare HS OTG Controller common interrupt handling
  4. *
  5. * Copyright (C) 2004-2013 Synopsys, Inc.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. The names of the above-listed copyright holders may not be used
  17. * to endorse or promote products derived from this software without
  18. * specific prior written permission.
  19. *
  20. * ALTERNATIVELY, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") as published by the Free Software
  22. * Foundation; either version 2 of the License, or (at your option) any
  23. * later version.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. */
  37. /*
  38. * This file contains the common interrupt handlers
  39. */
  40. #include <linux/kernel.h>
  41. #include <linux/module.h>
  42. #include <linux/moduleparam.h>
  43. #include <linux/spinlock.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/dma-mapping.h>
  46. #include <linux/io.h>
  47. #include <linux/slab.h>
  48. #include <linux/usb.h>
  49. #include <linux/usb/hcd.h>
  50. #include <linux/usb/ch11.h>
  51. #include "core.h"
  52. #include "hcd.h"
  53. static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  54. {
  55. switch (hsotg->op_state) {
  56. case OTG_STATE_A_HOST:
  57. return "a_host";
  58. case OTG_STATE_A_SUSPEND:
  59. return "a_suspend";
  60. case OTG_STATE_A_PERIPHERAL:
  61. return "a_peripheral";
  62. case OTG_STATE_B_PERIPHERAL:
  63. return "b_peripheral";
  64. case OTG_STATE_B_HOST:
  65. return "b_host";
  66. default:
  67. return "unknown";
  68. }
  69. }
  70. /**
  71. * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  72. * When the PRTINT interrupt fires, there are certain status bits in the Host
  73. * Port that needs to get cleared.
  74. *
  75. * @hsotg: Programming view of DWC_otg controller
  76. */
  77. static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  78. {
  79. u32 hprt0 = dwc2_readl(hsotg, HPRT0);
  80. if (hprt0 & HPRT0_ENACHG) {
  81. hprt0 &= ~HPRT0_ENA;
  82. dwc2_writel(hsotg, hprt0, HPRT0);
  83. }
  84. }
  85. /**
  86. * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  87. *
  88. * @hsotg: Programming view of DWC_otg controller
  89. */
  90. static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  91. {
  92. /* Clear interrupt */
  93. dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
  94. dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
  95. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  96. }
  97. /**
  98. * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
  99. * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
  100. *
  101. * @hsotg: Programming view of DWC_otg controller
  102. */
  103. static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
  104. {
  105. u32 gotgint;
  106. u32 gotgctl;
  107. u32 gintmsk;
  108. gotgint = dwc2_readl(hsotg, GOTGINT);
  109. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  110. dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
  111. dwc2_op_state_str(hsotg));
  112. if (gotgint & GOTGINT_SES_END_DET) {
  113. dev_dbg(hsotg->dev,
  114. " ++OTG Interrupt: Session End Detected++ (%s)\n",
  115. dwc2_op_state_str(hsotg));
  116. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  117. if (dwc2_is_device_mode(hsotg))
  118. dwc2_hsotg_disconnect(hsotg);
  119. if (hsotg->op_state == OTG_STATE_B_HOST) {
  120. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  121. } else {
  122. /*
  123. * If not B_HOST and Device HNP still set, HNP did
  124. * not succeed!
  125. */
  126. if (gotgctl & GOTGCTL_DEVHNPEN) {
  127. dev_dbg(hsotg->dev, "Session End Detected\n");
  128. dev_err(hsotg->dev,
  129. "Device Not Connected/Responding!\n");
  130. }
  131. /*
  132. * If Session End Detected the B-Cable has been
  133. * disconnected
  134. */
  135. /* Reset to a clean state */
  136. hsotg->lx_state = DWC2_L0;
  137. }
  138. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  139. gotgctl &= ~GOTGCTL_DEVHNPEN;
  140. dwc2_writel(hsotg, gotgctl, GOTGCTL);
  141. }
  142. if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
  143. dev_dbg(hsotg->dev,
  144. " ++OTG Interrupt: Session Request Success Status Change++\n");
  145. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  146. if (gotgctl & GOTGCTL_SESREQSCS) {
  147. if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
  148. hsotg->params.i2c_enable) {
  149. hsotg->srp_success = 1;
  150. } else {
  151. /* Clear Session Request */
  152. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  153. gotgctl &= ~GOTGCTL_SESREQ;
  154. dwc2_writel(hsotg, gotgctl, GOTGCTL);
  155. }
  156. }
  157. }
  158. if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
  159. /*
  160. * Print statements during the HNP interrupt handling
  161. * can cause it to fail
  162. */
  163. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  164. /*
  165. * WA for 3.00a- HW is not setting cur_mode, even sometimes
  166. * this does not help
  167. */
  168. if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
  169. udelay(100);
  170. if (gotgctl & GOTGCTL_HSTNEGSCS) {
  171. if (dwc2_is_host_mode(hsotg)) {
  172. hsotg->op_state = OTG_STATE_B_HOST;
  173. /*
  174. * Need to disable SOF interrupt immediately.
  175. * When switching from device to host, the PCD
  176. * interrupt handler won't handle the interrupt
  177. * if host mode is already set. The HCD
  178. * interrupt handler won't get called if the
  179. * HCD state is HALT. This means that the
  180. * interrupt does not get handled and Linux
  181. * complains loudly.
  182. */
  183. gintmsk = dwc2_readl(hsotg, GINTMSK);
  184. gintmsk &= ~GINTSTS_SOF;
  185. dwc2_writel(hsotg, gintmsk, GINTMSK);
  186. /*
  187. * Call callback function with spin lock
  188. * released
  189. */
  190. spin_unlock(&hsotg->lock);
  191. /* Initialize the Core for Host mode */
  192. dwc2_hcd_start(hsotg);
  193. spin_lock(&hsotg->lock);
  194. hsotg->op_state = OTG_STATE_B_HOST;
  195. }
  196. } else {
  197. gotgctl = dwc2_readl(hsotg, GOTGCTL);
  198. gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
  199. dwc2_writel(hsotg, gotgctl, GOTGCTL);
  200. dev_dbg(hsotg->dev, "HNP Failed\n");
  201. dev_err(hsotg->dev,
  202. "Device Not Connected/Responding\n");
  203. }
  204. }
  205. if (gotgint & GOTGINT_HST_NEG_DET) {
  206. /*
  207. * The disconnect interrupt is set at the same time as
  208. * Host Negotiation Detected. During the mode switch all
  209. * interrupts are cleared so the disconnect interrupt
  210. * handler will not get executed.
  211. */
  212. dev_dbg(hsotg->dev,
  213. " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
  214. (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
  215. if (dwc2_is_device_mode(hsotg)) {
  216. dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
  217. hsotg->op_state);
  218. spin_unlock(&hsotg->lock);
  219. dwc2_hcd_disconnect(hsotg, false);
  220. spin_lock(&hsotg->lock);
  221. hsotg->op_state = OTG_STATE_A_PERIPHERAL;
  222. } else {
  223. /* Need to disable SOF interrupt immediately */
  224. gintmsk = dwc2_readl(hsotg, GINTMSK);
  225. gintmsk &= ~GINTSTS_SOF;
  226. dwc2_writel(hsotg, gintmsk, GINTMSK);
  227. spin_unlock(&hsotg->lock);
  228. dwc2_hcd_start(hsotg);
  229. spin_lock(&hsotg->lock);
  230. hsotg->op_state = OTG_STATE_A_HOST;
  231. }
  232. }
  233. if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
  234. dev_dbg(hsotg->dev,
  235. " ++OTG Interrupt: A-Device Timeout Change++\n");
  236. if (gotgint & GOTGINT_DBNCE_DONE)
  237. dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
  238. /* Clear GOTGINT */
  239. dwc2_writel(hsotg, gotgint, GOTGINT);
  240. }
  241. /**
  242. * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
  243. * Change Interrupt
  244. *
  245. * @hsotg: Programming view of DWC_otg controller
  246. *
  247. * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
  248. * Device to Host Mode transition or a Host to Device Mode transition. This only
  249. * occurs when the cable is connected/removed from the PHY connector.
  250. */
  251. static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
  252. {
  253. u32 gintmsk;
  254. /* Clear interrupt */
  255. dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
  256. /* Need to disable SOF interrupt immediately */
  257. gintmsk = dwc2_readl(hsotg, GINTMSK);
  258. gintmsk &= ~GINTSTS_SOF;
  259. dwc2_writel(hsotg, gintmsk, GINTMSK);
  260. dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
  261. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  262. /*
  263. * Need to schedule a work, as there are possible DELAY function calls.
  264. */
  265. if (hsotg->wq_otg)
  266. queue_work(hsotg->wq_otg, &hsotg->wf_otg);
  267. }
  268. /**
  269. * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
  270. * initiating the Session Request Protocol to request the host to turn on bus
  271. * power so a new session can begin
  272. *
  273. * @hsotg: Programming view of DWC_otg controller
  274. *
  275. * This handler responds by turning on bus power. If the DWC_otg controller is
  276. * in low power mode, this handler brings the controller out of low power mode
  277. * before turning on bus power.
  278. */
  279. static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
  280. {
  281. int ret;
  282. u32 hprt0;
  283. /* Clear interrupt */
  284. dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
  285. dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
  286. hsotg->lx_state);
  287. if (dwc2_is_device_mode(hsotg)) {
  288. if (hsotg->lx_state == DWC2_L2) {
  289. ret = dwc2_exit_partial_power_down(hsotg, true);
  290. if (ret && (ret != -ENOTSUPP))
  291. dev_err(hsotg->dev,
  292. "exit power_down failed\n");
  293. }
  294. /*
  295. * Report disconnect if there is any previous session
  296. * established
  297. */
  298. dwc2_hsotg_disconnect(hsotg);
  299. } else {
  300. /* Turn on the port power bit. */
  301. hprt0 = dwc2_read_hprt0(hsotg);
  302. hprt0 |= HPRT0_PWR;
  303. dwc2_writel(hsotg, hprt0, HPRT0);
  304. /* Connect hcd after port power is set. */
  305. dwc2_hcd_connect(hsotg);
  306. }
  307. }
  308. /**
  309. * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
  310. *
  311. * @hsotg: Programming view of DWC_otg controller
  312. *
  313. */
  314. static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
  315. {
  316. u32 glpmcfg;
  317. u32 i = 0;
  318. if (hsotg->lx_state != DWC2_L1) {
  319. dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
  320. return;
  321. }
  322. glpmcfg = dwc2_readl(hsotg, GLPMCFG);
  323. if (dwc2_is_device_mode(hsotg)) {
  324. dev_dbg(hsotg->dev, "Exit from L1 state\n");
  325. glpmcfg &= ~GLPMCFG_ENBLSLPM;
  326. glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
  327. dwc2_writel(hsotg, glpmcfg, GLPMCFG);
  328. do {
  329. glpmcfg = dwc2_readl(hsotg, GLPMCFG);
  330. if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
  331. GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
  332. break;
  333. udelay(1);
  334. } while (++i < 200);
  335. if (i == 200) {
  336. dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
  337. return;
  338. }
  339. dwc2_gadget_init_lpm(hsotg);
  340. } else {
  341. /* TODO */
  342. dev_err(hsotg->dev, "Host side LPM is not supported.\n");
  343. return;
  344. }
  345. /* Change to L0 state */
  346. hsotg->lx_state = DWC2_L0;
  347. /* Inform gadget to exit from L1 */
  348. call_gadget(hsotg, resume);
  349. }
  350. /*
  351. * This interrupt indicates that the DWC_otg controller has detected a
  352. * resume or remote wakeup sequence. If the DWC_otg controller is in
  353. * low power mode, the handler must brings the controller out of low
  354. * power mode. The controller automatically begins resume signaling.
  355. * The handler schedules a time to stop resume signaling.
  356. */
  357. static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
  358. {
  359. int ret;
  360. /* Clear interrupt */
  361. dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
  362. dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
  363. dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
  364. if (hsotg->lx_state == DWC2_L1) {
  365. dwc2_wakeup_from_lpm_l1(hsotg);
  366. return;
  367. }
  368. if (dwc2_is_device_mode(hsotg)) {
  369. dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
  370. dwc2_readl(hsotg, DSTS));
  371. if (hsotg->lx_state == DWC2_L2) {
  372. u32 dctl = dwc2_readl(hsotg, DCTL);
  373. /* Clear Remote Wakeup Signaling */
  374. dctl &= ~DCTL_RMTWKUPSIG;
  375. dwc2_writel(hsotg, dctl, DCTL);
  376. ret = dwc2_exit_partial_power_down(hsotg, true);
  377. if (ret && (ret != -ENOTSUPP))
  378. dev_err(hsotg->dev, "exit power_down failed\n");
  379. /* Change to L0 state */
  380. hsotg->lx_state = DWC2_L0;
  381. call_gadget(hsotg, resume);
  382. } else {
  383. /* Change to L0 state */
  384. hsotg->lx_state = DWC2_L0;
  385. }
  386. } else {
  387. if (hsotg->params.power_down)
  388. return;
  389. if (hsotg->lx_state != DWC2_L1) {
  390. u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
  391. /* Restart the Phy Clock */
  392. pcgcctl &= ~PCGCTL_STOPPCLK;
  393. dwc2_writel(hsotg, pcgcctl, PCGCTL);
  394. /*
  395. * If we've got this quirk then the PHY is stuck upon
  396. * wakeup. Assert reset. This will propagate out and
  397. * eventually we'll re-enumerate the device. Not great
  398. * but the best we can do. We can't call phy_reset()
  399. * at interrupt time but there's no hurry, so we'll
  400. * schedule it for later.
  401. */
  402. if (hsotg->reset_phy_on_wake)
  403. dwc2_host_schedule_phy_reset(hsotg);
  404. mod_timer(&hsotg->wkp_timer,
  405. jiffies + msecs_to_jiffies(71));
  406. } else {
  407. /* Change to L0 state */
  408. hsotg->lx_state = DWC2_L0;
  409. }
  410. }
  411. }
  412. /*
  413. * This interrupt indicates that a device has been disconnected from the
  414. * root port
  415. */
  416. static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
  417. {
  418. dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
  419. dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
  420. dwc2_is_host_mode(hsotg) ? "Host" : "Device",
  421. dwc2_op_state_str(hsotg));
  422. if (hsotg->op_state == OTG_STATE_A_HOST)
  423. dwc2_hcd_disconnect(hsotg, false);
  424. }
  425. /*
  426. * This interrupt indicates that SUSPEND state has been detected on the USB.
  427. *
  428. * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
  429. * to "a_host".
  430. *
  431. * When power management is enabled the core will be put in low power mode.
  432. */
  433. static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
  434. {
  435. u32 dsts;
  436. int ret;
  437. /* Clear interrupt */
  438. dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
  439. dev_dbg(hsotg->dev, "USB SUSPEND\n");
  440. if (dwc2_is_device_mode(hsotg)) {
  441. /*
  442. * Check the Device status register to determine if the Suspend
  443. * state is active
  444. */
  445. dsts = dwc2_readl(hsotg, DSTS);
  446. dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
  447. dev_dbg(hsotg->dev,
  448. "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
  449. !!(dsts & DSTS_SUSPSTS),
  450. hsotg->hw_params.power_optimized,
  451. hsotg->hw_params.hibernation);
  452. /* Ignore suspend request before enumeration */
  453. if (!dwc2_is_device_connected(hsotg)) {
  454. dev_dbg(hsotg->dev,
  455. "ignore suspend request before enumeration\n");
  456. return;
  457. }
  458. if (dsts & DSTS_SUSPSTS) {
  459. if (hsotg->hw_params.power_optimized) {
  460. ret = dwc2_enter_partial_power_down(hsotg);
  461. if (ret) {
  462. if (ret != -ENOTSUPP)
  463. dev_err(hsotg->dev,
  464. "%s: enter partial_power_down failed\n",
  465. __func__);
  466. goto skip_power_saving;
  467. }
  468. udelay(100);
  469. /* Ask phy to be suspended */
  470. if (!IS_ERR_OR_NULL(hsotg->uphy))
  471. usb_phy_set_suspend(hsotg->uphy, true);
  472. }
  473. if (hsotg->hw_params.hibernation) {
  474. ret = dwc2_enter_hibernation(hsotg, 0);
  475. if (ret && ret != -ENOTSUPP)
  476. dev_err(hsotg->dev,
  477. "%s: enter hibernation failed\n",
  478. __func__);
  479. }
  480. skip_power_saving:
  481. /*
  482. * Change to L2 (suspend) state before releasing
  483. * spinlock
  484. */
  485. hsotg->lx_state = DWC2_L2;
  486. /* Call gadget suspend callback */
  487. call_gadget(hsotg, suspend);
  488. }
  489. } else {
  490. if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
  491. dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
  492. /* Change to L2 (suspend) state */
  493. hsotg->lx_state = DWC2_L2;
  494. /* Clear the a_peripheral flag, back to a_host */
  495. spin_unlock(&hsotg->lock);
  496. dwc2_hcd_start(hsotg);
  497. spin_lock(&hsotg->lock);
  498. hsotg->op_state = OTG_STATE_A_HOST;
  499. }
  500. }
  501. }
  502. /**
  503. * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
  504. *
  505. * @hsotg: Programming view of DWC_otg controller
  506. *
  507. */
  508. static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
  509. {
  510. u32 glpmcfg;
  511. u32 pcgcctl;
  512. u32 hird;
  513. u32 hird_thres;
  514. u32 hird_thres_en;
  515. u32 enslpm;
  516. /* Clear interrupt */
  517. dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
  518. glpmcfg = dwc2_readl(hsotg, GLPMCFG);
  519. if (!(glpmcfg & GLPMCFG_LPMCAP)) {
  520. dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
  521. return;
  522. }
  523. hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
  524. hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
  525. ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
  526. hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
  527. enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
  528. if (dwc2_is_device_mode(hsotg)) {
  529. dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
  530. if (hird_thres_en && hird >= hird_thres) {
  531. dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
  532. } else if (enslpm) {
  533. dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
  534. } else {
  535. dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
  536. pcgcctl = dwc2_readl(hsotg, PCGCTL);
  537. pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
  538. dwc2_writel(hsotg, pcgcctl, PCGCTL);
  539. }
  540. /**
  541. * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
  542. */
  543. udelay(10);
  544. glpmcfg = dwc2_readl(hsotg, GLPMCFG);
  545. if (glpmcfg & GLPMCFG_SLPSTS) {
  546. /* Save the current state */
  547. hsotg->lx_state = DWC2_L1;
  548. dev_dbg(hsotg->dev,
  549. "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
  550. /* Inform gadget that we are in L1 state */
  551. call_gadget(hsotg, suspend);
  552. }
  553. }
  554. }
  555. #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
  556. GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
  557. GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
  558. GINTSTS_USBSUSP | GINTSTS_PRTINT | \
  559. GINTSTS_LPMTRANRCVD)
  560. /*
  561. * This function returns the Core Interrupt register
  562. */
  563. static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
  564. {
  565. u32 gintsts;
  566. u32 gintmsk;
  567. u32 gahbcfg;
  568. u32 gintmsk_common = GINTMSK_COMMON;
  569. gintsts = dwc2_readl(hsotg, GINTSTS);
  570. gintmsk = dwc2_readl(hsotg, GINTMSK);
  571. gahbcfg = dwc2_readl(hsotg, GAHBCFG);
  572. /* If any common interrupts set */
  573. if (gintsts & gintmsk_common)
  574. dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
  575. gintsts, gintmsk);
  576. if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
  577. return gintsts & gintmsk & gintmsk_common;
  578. else
  579. return 0;
  580. }
  581. /**
  582. * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
  583. * Exits hibernation without restoring registers.
  584. *
  585. * @hsotg: Programming view of DWC_otg controller
  586. * @gpwrdn: GPWRDN register
  587. */
  588. static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
  589. u32 gpwrdn)
  590. {
  591. u32 gpwrdn_tmp;
  592. /* Switch-on voltage to the core */
  593. gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
  594. gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
  595. dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
  596. udelay(5);
  597. /* Reset core */
  598. gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
  599. gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
  600. dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
  601. udelay(5);
  602. /* Disable Power Down Clamp */
  603. gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
  604. gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
  605. dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
  606. udelay(5);
  607. /* Deassert reset core */
  608. gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
  609. gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
  610. dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
  611. udelay(5);
  612. /* Disable PMU interrupt */
  613. gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
  614. gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
  615. dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
  616. /* De-assert Wakeup Logic */
  617. gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
  618. gpwrdn_tmp &= ~GPWRDN_PMUACTV;
  619. dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
  620. hsotg->hibernated = 0;
  621. #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
  622. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  623. hsotg->bus_suspended = 0;
  624. #endif
  625. if (gpwrdn & GPWRDN_IDSTS) {
  626. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  627. dwc2_core_init(hsotg, false);
  628. dwc2_enable_global_interrupts(hsotg);
  629. dwc2_hsotg_core_init_disconnected(hsotg, false);
  630. dwc2_hsotg_core_connect(hsotg);
  631. } else {
  632. hsotg->op_state = OTG_STATE_A_HOST;
  633. /* Initialize the Core for Host mode */
  634. dwc2_core_init(hsotg, false);
  635. dwc2_enable_global_interrupts(hsotg);
  636. dwc2_hcd_start(hsotg);
  637. }
  638. }
  639. /*
  640. * GPWRDN interrupt handler.
  641. *
  642. * The GPWRDN interrupts are those that occur in both Host and
  643. * Device mode while core is in hibernated state.
  644. */
  645. static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
  646. {
  647. u32 gpwrdn;
  648. int linestate;
  649. gpwrdn = dwc2_readl(hsotg, GPWRDN);
  650. /* clear all interrupt */
  651. dwc2_writel(hsotg, gpwrdn, GPWRDN);
  652. linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
  653. dev_dbg(hsotg->dev,
  654. "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
  655. gpwrdn);
  656. if ((gpwrdn & GPWRDN_DISCONN_DET) &&
  657. (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
  658. dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
  659. /*
  660. * Call disconnect detect function to exit from
  661. * hibernation
  662. */
  663. dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
  664. } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
  665. (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
  666. dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
  667. if (hsotg->hw_params.hibernation &&
  668. hsotg->hibernated) {
  669. if (gpwrdn & GPWRDN_IDSTS) {
  670. dwc2_exit_hibernation(hsotg, 0, 0, 0);
  671. call_gadget(hsotg, resume);
  672. } else {
  673. dwc2_exit_hibernation(hsotg, 1, 0, 1);
  674. }
  675. }
  676. } else if ((gpwrdn & GPWRDN_RST_DET) &&
  677. (gpwrdn & GPWRDN_RST_DET_MSK)) {
  678. dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
  679. if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
  680. dwc2_exit_hibernation(hsotg, 0, 1, 0);
  681. } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
  682. (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
  683. dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
  684. /*
  685. * As GPWRDN_STS_CHGINT exit from hibernation flow is
  686. * the same as in GPWRDN_DISCONN_DET flow. Call
  687. * disconnect detect helper function to exit from
  688. * hibernation.
  689. */
  690. dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
  691. }
  692. }
  693. /*
  694. * Common interrupt handler
  695. *
  696. * The common interrupts are those that occur in both Host and Device mode.
  697. * This handler handles the following interrupts:
  698. * - Mode Mismatch Interrupt
  699. * - OTG Interrupt
  700. * - Connector ID Status Change Interrupt
  701. * - Disconnect Interrupt
  702. * - Session Request Interrupt
  703. * - Resume / Remote Wakeup Detected Interrupt
  704. * - Suspend Interrupt
  705. */
  706. irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
  707. {
  708. struct dwc2_hsotg *hsotg = dev;
  709. u32 gintsts;
  710. irqreturn_t retval = IRQ_NONE;
  711. spin_lock(&hsotg->lock);
  712. if (!dwc2_is_controller_alive(hsotg)) {
  713. dev_warn(hsotg->dev, "Controller is dead\n");
  714. goto out;
  715. }
  716. /* Reading current frame number value in device or host modes. */
  717. if (dwc2_is_device_mode(hsotg))
  718. hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
  719. & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
  720. else
  721. hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
  722. & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
  723. gintsts = dwc2_read_common_intr(hsotg);
  724. if (gintsts & ~GINTSTS_PRTINT)
  725. retval = IRQ_HANDLED;
  726. /* In case of hibernated state gintsts must not work */
  727. if (hsotg->hibernated) {
  728. dwc2_handle_gpwrdn_intr(hsotg);
  729. retval = IRQ_HANDLED;
  730. goto out;
  731. }
  732. if (gintsts & GINTSTS_MODEMIS)
  733. dwc2_handle_mode_mismatch_intr(hsotg);
  734. if (gintsts & GINTSTS_OTGINT)
  735. dwc2_handle_otg_intr(hsotg);
  736. if (gintsts & GINTSTS_CONIDSTSCHNG)
  737. dwc2_handle_conn_id_status_change_intr(hsotg);
  738. if (gintsts & GINTSTS_DISCONNINT)
  739. dwc2_handle_disconnect_intr(hsotg);
  740. if (gintsts & GINTSTS_SESSREQINT)
  741. dwc2_handle_session_req_intr(hsotg);
  742. if (gintsts & GINTSTS_WKUPINT)
  743. dwc2_handle_wakeup_detected_intr(hsotg);
  744. if (gintsts & GINTSTS_USBSUSP)
  745. dwc2_handle_usb_suspend_intr(hsotg);
  746. if (gintsts & GINTSTS_LPMTRANRCVD)
  747. dwc2_handle_lpm_intr(hsotg);
  748. if (gintsts & GINTSTS_PRTINT) {
  749. /*
  750. * The port interrupt occurs while in device mode with HPRT0
  751. * Port Enable/Disable
  752. */
  753. if (dwc2_is_device_mode(hsotg)) {
  754. dev_dbg(hsotg->dev,
  755. " --Port interrupt received in Device mode--\n");
  756. dwc2_handle_usb_port_intr(hsotg);
  757. retval = IRQ_HANDLED;
  758. }
  759. }
  760. out:
  761. spin_unlock(&hsotg->lock);
  762. return retval;
  763. }