core.h 61 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
  2. /*
  3. * core.h - DesignWare HS OTG Controller common declarations
  4. *
  5. * Copyright (C) 2004-2013 Synopsys, Inc.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * 3. The names of the above-listed copyright holders may not be used
  17. * to endorse or promote products derived from this software without
  18. * specific prior written permission.
  19. *
  20. * ALTERNATIVELY, this software may be distributed under the terms of the
  21. * GNU General Public License ("GPL") as published by the Free Software
  22. * Foundation; either version 2 of the License, or (at your option) any
  23. * later version.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. */
  37. #ifndef __DWC2_CORE_H__
  38. #define __DWC2_CORE_H__
  39. #include <linux/phy/phy.h>
  40. #include <linux/regulator/consumer.h>
  41. #include <linux/usb/gadget.h>
  42. #include <linux/usb/otg.h>
  43. #include <linux/usb/phy.h>
  44. #include "hw.h"
  45. /*
  46. * Suggested defines for tracers:
  47. * - no_printk: Disable tracing
  48. * - pr_info: Print this info to the console
  49. * - trace_printk: Print this info to trace buffer (good for verbose logging)
  50. */
  51. #define DWC2_TRACE_SCHEDULER no_printk
  52. #define DWC2_TRACE_SCHEDULER_VB no_printk
  53. /* Detailed scheduler tracing, but won't overwhelm console */
  54. #define dwc2_sch_dbg(hsotg, fmt, ...) \
  55. DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
  56. dev_name(hsotg->dev), ##__VA_ARGS__)
  57. /* Verbose scheduler tracing */
  58. #define dwc2_sch_vdbg(hsotg, fmt, ...) \
  59. DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
  60. dev_name(hsotg->dev), ##__VA_ARGS__)
  61. /* Maximum number of Endpoints/HostChannels */
  62. #define MAX_EPS_CHANNELS 16
  63. /* dwc2-hsotg declarations */
  64. static const char * const dwc2_hsotg_supply_names[] = {
  65. "vusb_d", /* digital USB supply, 1.2V */
  66. "vusb_a", /* analog USB supply, 1.1V */
  67. };
  68. #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
  69. /*
  70. * EP0_MPS_LIMIT
  71. *
  72. * Unfortunately there seems to be a limit of the amount of data that can
  73. * be transferred by IN transactions on EP0. This is either 127 bytes or 3
  74. * packets (which practically means 1 packet and 63 bytes of data) when the
  75. * MPS is set to 64.
  76. *
  77. * This means if we are wanting to move >127 bytes of data, we need to
  78. * split the transactions up, but just doing one packet at a time does
  79. * not work (this may be an implicit DATA0 PID on first packet of the
  80. * transaction) and doing 2 packets is outside the controller's limits.
  81. *
  82. * If we try to lower the MPS size for EP0, then no transfers work properly
  83. * for EP0, and the system will fail basic enumeration. As no cause for this
  84. * has currently been found, we cannot support any large IN transfers for
  85. * EP0.
  86. */
  87. #define EP0_MPS_LIMIT 64
  88. struct dwc2_hsotg;
  89. struct dwc2_hsotg_req;
  90. /**
  91. * struct dwc2_hsotg_ep - driver endpoint definition.
  92. * @ep: The gadget layer representation of the endpoint.
  93. * @name: The driver generated name for the endpoint.
  94. * @queue: Queue of requests for this endpoint.
  95. * @parent: Reference back to the parent device structure.
  96. * @req: The current request that the endpoint is processing. This is
  97. * used to indicate an request has been loaded onto the endpoint
  98. * and has yet to be completed (maybe due to data move, or simply
  99. * awaiting an ack from the core all the data has been completed).
  100. * @debugfs: File entry for debugfs file for this endpoint.
  101. * @dir_in: Set to true if this endpoint is of the IN direction, which
  102. * means that it is sending data to the Host.
  103. * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
  104. * @index: The index for the endpoint registers.
  105. * @mc: Multi Count - number of transactions per microframe
  106. * @interval: Interval for periodic endpoints, in frames or microframes.
  107. * @name: The name array passed to the USB core.
  108. * @halted: Set if the endpoint has been halted.
  109. * @periodic: Set if this is a periodic ep, such as Interrupt
  110. * @isochronous: Set if this is a isochronous ep
  111. * @send_zlp: Set if we need to send a zero-length packet.
  112. * @desc_list_dma: The DMA address of descriptor chain currently in use.
  113. * @desc_list: Pointer to descriptor DMA chain head currently in use.
  114. * @desc_count: Count of entries within the DMA descriptor chain of EP.
  115. * @next_desc: index of next free descriptor in the ISOC chain under SW control.
  116. * @compl_desc: index of next descriptor to be completed by xFerComplete
  117. * @total_data: The total number of data bytes done.
  118. * @fifo_size: The size of the FIFO (for periodic IN endpoints)
  119. * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
  120. * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
  121. * @last_load: The offset of data for the last start of request.
  122. * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
  123. * @target_frame: Targeted frame num to setup next ISOC transfer
  124. * @frame_overrun: Indicates SOF number overrun in DSTS
  125. *
  126. * This is the driver's state for each registered endpoint, allowing it
  127. * to keep track of transactions that need doing. Each endpoint has a
  128. * lock to protect the state, to try and avoid using an overall lock
  129. * for the host controller as much as possible.
  130. *
  131. * For periodic IN endpoints, we have fifo_size and fifo_load to try
  132. * and keep track of the amount of data in the periodic FIFO for each
  133. * of these as we don't have a status register that tells us how much
  134. * is in each of them. (note, this may actually be useless information
  135. * as in shared-fifo mode periodic in acts like a single-frame packet
  136. * buffer than a fifo)
  137. */
  138. struct dwc2_hsotg_ep {
  139. struct usb_ep ep;
  140. struct list_head queue;
  141. struct dwc2_hsotg *parent;
  142. struct dwc2_hsotg_req *req;
  143. struct dentry *debugfs;
  144. unsigned long total_data;
  145. unsigned int size_loaded;
  146. unsigned int last_load;
  147. unsigned int fifo_load;
  148. unsigned short fifo_size;
  149. unsigned short fifo_index;
  150. unsigned char dir_in;
  151. unsigned char map_dir;
  152. unsigned char index;
  153. unsigned char mc;
  154. u16 interval;
  155. unsigned int halted:1;
  156. unsigned int periodic:1;
  157. unsigned int isochronous:1;
  158. unsigned int send_zlp:1;
  159. unsigned int target_frame;
  160. #define TARGET_FRAME_INITIAL 0xFFFFFFFF
  161. bool frame_overrun;
  162. dma_addr_t desc_list_dma;
  163. struct dwc2_dma_desc *desc_list;
  164. u8 desc_count;
  165. unsigned int next_desc;
  166. unsigned int compl_desc;
  167. char name[10];
  168. };
  169. /**
  170. * struct dwc2_hsotg_req - data transfer request
  171. * @req: The USB gadget request
  172. * @queue: The list of requests for the endpoint this is queued for.
  173. * @saved_req_buf: variable to save req.buf when bounce buffers are used.
  174. */
  175. struct dwc2_hsotg_req {
  176. struct usb_request req;
  177. struct list_head queue;
  178. void *saved_req_buf;
  179. };
  180. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  181. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  182. #define call_gadget(_hs, _entry) \
  183. do { \
  184. if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
  185. (_hs)->driver && (_hs)->driver->_entry) { \
  186. spin_unlock(&_hs->lock); \
  187. (_hs)->driver->_entry(&(_hs)->gadget); \
  188. spin_lock(&_hs->lock); \
  189. } \
  190. } while (0)
  191. #else
  192. #define call_gadget(_hs, _entry) do {} while (0)
  193. #endif
  194. struct dwc2_hsotg;
  195. struct dwc2_host_chan;
  196. /* Device States */
  197. enum dwc2_lx_state {
  198. DWC2_L0, /* On state */
  199. DWC2_L1, /* LPM sleep state */
  200. DWC2_L2, /* USB suspend state */
  201. DWC2_L3, /* Off state */
  202. };
  203. /* Gadget ep0 states */
  204. enum dwc2_ep0_state {
  205. DWC2_EP0_SETUP,
  206. DWC2_EP0_DATA_IN,
  207. DWC2_EP0_DATA_OUT,
  208. DWC2_EP0_STATUS_IN,
  209. DWC2_EP0_STATUS_OUT,
  210. };
  211. /**
  212. * struct dwc2_core_params - Parameters for configuring the core
  213. *
  214. * @otg_cap: Specifies the OTG capabilities.
  215. * 0 - HNP and SRP capable
  216. * 1 - SRP Only capable
  217. * 2 - No HNP/SRP capable (always available)
  218. * Defaults to best available option (0, 1, then 2)
  219. * @host_dma: Specifies whether to use slave or DMA mode for accessing
  220. * the data FIFOs. The driver will automatically detect the
  221. * value for this parameter if none is specified.
  222. * 0 - Slave (always available)
  223. * 1 - DMA (default, if available)
  224. * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
  225. * address DMA mode or descriptor DMA mode for accessing
  226. * the data FIFOs. The driver will automatically detect the
  227. * value for this if none is specified.
  228. * 0 - Address DMA
  229. * 1 - Descriptor DMA (default, if available)
  230. * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
  231. * address DMA mode or descriptor DMA mode for accessing
  232. * the data FIFOs in Full Speed mode only. The driver
  233. * will automatically detect the value for this if none is
  234. * specified.
  235. * 0 - Address DMA
  236. * 1 - Descriptor DMA in FS (default, if available)
  237. * @speed: Specifies the maximum speed of operation in host and
  238. * device mode. The actual speed depends on the speed of
  239. * the attached device and the value of phy_type.
  240. * 0 - High Speed
  241. * (default when phy_type is UTMI+ or ULPI)
  242. * 1 - Full Speed
  243. * (default when phy_type is Full Speed)
  244. * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
  245. * 1 - Allow dynamic FIFO sizing (default, if available)
  246. * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
  247. * are enabled for non-periodic IN endpoints in device
  248. * mode.
  249. * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
  250. * dynamic FIFO sizing is enabled
  251. * 16 to 32768
  252. * Actual maximum value is autodetected and also
  253. * the default.
  254. * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
  255. * in host mode when dynamic FIFO sizing is enabled
  256. * 16 to 32768
  257. * Actual maximum value is autodetected and also
  258. * the default.
  259. * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
  260. * host mode when dynamic FIFO sizing is enabled
  261. * 16 to 32768
  262. * Actual maximum value is autodetected and also
  263. * the default.
  264. * @max_transfer_size: The maximum transfer size supported, in bytes
  265. * 2047 to 65,535
  266. * Actual maximum value is autodetected and also
  267. * the default.
  268. * @max_packet_count: The maximum number of packets in a transfer
  269. * 15 to 511
  270. * Actual maximum value is autodetected and also
  271. * the default.
  272. * @host_channels: The number of host channel registers to use
  273. * 1 to 16
  274. * Actual maximum value is autodetected and also
  275. * the default.
  276. * @phy_type: Specifies the type of PHY interface to use. By default,
  277. * the driver will automatically detect the phy_type.
  278. * 0 - Full Speed Phy
  279. * 1 - UTMI+ Phy
  280. * 2 - ULPI Phy
  281. * Defaults to best available option (2, 1, then 0)
  282. * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
  283. * is applicable for a phy_type of UTMI+ or ULPI. (For a
  284. * ULPI phy_type, this parameter indicates the data width
  285. * between the MAC and the ULPI Wrapper.) Also, this
  286. * parameter is applicable only if the OTG_HSPHY_WIDTH cC
  287. * parameter was set to "8 and 16 bits", meaning that the
  288. * core has been configured to work at either data path
  289. * width.
  290. * 8 or 16 (default 16 if available)
  291. * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
  292. * data rate. This parameter is only applicable if phy_type
  293. * is ULPI.
  294. * 0 - single data rate ULPI interface with 8 bit wide
  295. * data bus (default)
  296. * 1 - double data rate ULPI interface with 4 bit wide
  297. * data bus
  298. * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
  299. * external supply to drive the VBus
  300. * 0 - Internal supply (default)
  301. * 1 - External supply
  302. * @i2c_enable: Specifies whether to use the I2Cinterface for a full
  303. * speed PHY. This parameter is only applicable if phy_type
  304. * is FS.
  305. * 0 - No (default)
  306. * 1 - Yes
  307. * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
  308. * 0 - Disable (default)
  309. * 1 - Enable
  310. * @acg_enable: For enabling Active Clock Gating in the controller
  311. * 0 - No
  312. * 1 - Yes
  313. * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
  314. * 0 - No (default)
  315. * 1 - Yes
  316. * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
  317. * when attached to a Full Speed or Low Speed device in
  318. * host mode.
  319. * 0 - Don't support low power mode (default)
  320. * 1 - Support low power mode
  321. * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
  322. * when connected to a Low Speed device in host
  323. * mode. This parameter is applicable only if
  324. * host_support_fs_ls_low_power is enabled.
  325. * 0 - 48 MHz
  326. * (default when phy_type is UTMI+ or ULPI)
  327. * 1 - 6 MHz
  328. * (default when phy_type is Full Speed)
  329. * @oc_disable: Flag to disable overcurrent condition.
  330. * 0 - Allow overcurrent condition to get detected
  331. * 1 - Disable overcurrent condtion to get detected
  332. * @ts_dline: Enable Term Select Dline pulsing
  333. * 0 - No (default)
  334. * 1 - Yes
  335. * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
  336. * 0 - No (default for core < 2.92a)
  337. * 1 - Yes (default for core >= 2.92a)
  338. * @ahbcfg: This field allows the default value of the GAHBCFG
  339. * register to be overridden
  340. * -1 - GAHBCFG value will be set to 0x06
  341. * (INCR, default)
  342. * all others - GAHBCFG value will be overridden with
  343. * this value
  344. * Not all bits can be controlled like this, the
  345. * bits defined by GAHBCFG_CTRL_MASK are controlled
  346. * by the driver and are ignored in this
  347. * configuration value.
  348. * @uframe_sched: True to enable the microframe scheduler
  349. * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
  350. * Disable CONIDSTSCHNG controller interrupt in such
  351. * case.
  352. * 0 - No (default)
  353. * 1 - Yes
  354. * @power_down: Specifies whether the controller support power_down.
  355. * If power_down is enabled, the controller will enter
  356. * power_down in both peripheral and host mode when
  357. * needed.
  358. * 0 - No (default)
  359. * 1 - Partial power down
  360. * 2 - Hibernation
  361. * @lpm: Enable LPM support.
  362. * 0 - No
  363. * 1 - Yes
  364. * @lpm_clock_gating: Enable core PHY clock gating.
  365. * 0 - No
  366. * 1 - Yes
  367. * @besl: Enable LPM Errata support.
  368. * 0 - No
  369. * 1 - Yes
  370. * @hird_threshold_en: HIRD or HIRD Threshold enable.
  371. * 0 - No
  372. * 1 - Yes
  373. * @hird_threshold: Value of BESL or HIRD Threshold.
  374. * @ref_clk_per: Indicates in terms of pico seconds the period
  375. * of ref_clk.
  376. * 62500 - 16MHz
  377. * 58823 - 17MHz
  378. * 52083 - 19.2MHz
  379. * 50000 - 20MHz
  380. * 41666 - 24MHz
  381. * 33333 - 30MHz (default)
  382. * 25000 - 40MHz
  383. * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
  384. * the controller should generate an interrupt if the
  385. * device had been in L1 state until that period.
  386. * This is used by SW to initiate Remote WakeUp in the
  387. * controller so as to sync to the uF number from the host.
  388. * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
  389. * register.
  390. * 0 - Deactivate the transceiver (default)
  391. * 1 - Activate the transceiver
  392. * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
  393. * detection using GGPIO register.
  394. * 0 - Deactivate the external level detection (default)
  395. * 1 - Activate the external level detection
  396. * @g_dma: Enables gadget dma usage (default: autodetect).
  397. * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
  398. * @g_rx_fifo_size: The periodic rx fifo size for the device, in
  399. * DWORDS from 16-32768 (default: 2048 if
  400. * possible, otherwise autodetect).
  401. * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
  402. * DWORDS from 16-32768 (default: 1024 if
  403. * possible, otherwise autodetect).
  404. * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
  405. * mode. Each value corresponds to one EP
  406. * starting from EP1 (max 15 values). Sizes are
  407. * in DWORDS with possible values from from
  408. * 16-32768 (default: 256, 256, 256, 256, 768,
  409. * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
  410. * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
  411. * while full&low speed device connect. And change speed
  412. * back to DWC2_SPEED_PARAM_HIGH while device is gone.
  413. * 0 - No (default)
  414. * 1 - Yes
  415. * @service_interval: Enable service interval based scheduling.
  416. * 0 - No
  417. * 1 - Yes
  418. *
  419. * The following parameters may be specified when starting the module. These
  420. * parameters define how the DWC_otg controller should be configured. A
  421. * value of -1 (or any other out of range value) for any parameter means
  422. * to read the value from hardware (if possible) or use the builtin
  423. * default described above.
  424. */
  425. struct dwc2_core_params {
  426. u8 otg_cap;
  427. #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
  428. #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
  429. #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
  430. u8 phy_type;
  431. #define DWC2_PHY_TYPE_PARAM_FS 0
  432. #define DWC2_PHY_TYPE_PARAM_UTMI 1
  433. #define DWC2_PHY_TYPE_PARAM_ULPI 2
  434. u8 speed;
  435. #define DWC2_SPEED_PARAM_HIGH 0
  436. #define DWC2_SPEED_PARAM_FULL 1
  437. #define DWC2_SPEED_PARAM_LOW 2
  438. u8 phy_utmi_width;
  439. bool phy_ulpi_ddr;
  440. bool phy_ulpi_ext_vbus;
  441. bool enable_dynamic_fifo;
  442. bool en_multiple_tx_fifo;
  443. bool i2c_enable;
  444. bool acg_enable;
  445. bool ulpi_fs_ls;
  446. bool ts_dline;
  447. bool reload_ctl;
  448. bool uframe_sched;
  449. bool external_id_pin_ctl;
  450. int power_down;
  451. #define DWC2_POWER_DOWN_PARAM_NONE 0
  452. #define DWC2_POWER_DOWN_PARAM_PARTIAL 1
  453. #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
  454. bool lpm;
  455. bool lpm_clock_gating;
  456. bool besl;
  457. bool hird_threshold_en;
  458. bool service_interval;
  459. u8 hird_threshold;
  460. bool activate_stm_fs_transceiver;
  461. bool activate_stm_id_vb_detection;
  462. bool ipg_isoc_en;
  463. u16 max_packet_count;
  464. u32 max_transfer_size;
  465. u32 ahbcfg;
  466. /* GREFCLK parameters */
  467. u32 ref_clk_per;
  468. u16 sof_cnt_wkup_alert;
  469. /* Host parameters */
  470. bool host_dma;
  471. bool dma_desc_enable;
  472. bool dma_desc_fs_enable;
  473. bool host_support_fs_ls_low_power;
  474. bool host_ls_low_power_phy_clk;
  475. bool oc_disable;
  476. u8 host_channels;
  477. u16 host_rx_fifo_size;
  478. u16 host_nperio_tx_fifo_size;
  479. u16 host_perio_tx_fifo_size;
  480. /* Gadget parameters */
  481. bool g_dma;
  482. bool g_dma_desc;
  483. u32 g_rx_fifo_size;
  484. u32 g_np_tx_fifo_size;
  485. u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
  486. bool change_speed_quirk;
  487. };
  488. /**
  489. * struct dwc2_hw_params - Autodetected parameters.
  490. *
  491. * These parameters are the various parameters read from hardware
  492. * registers during initialization. They typically contain the best
  493. * supported or maximum value that can be configured in the
  494. * corresponding dwc2_core_params value.
  495. *
  496. * The values that are not in dwc2_core_params are documented below.
  497. *
  498. * @op_mode: Mode of Operation
  499. * 0 - HNP- and SRP-Capable OTG (Host & Device)
  500. * 1 - SRP-Capable OTG (Host & Device)
  501. * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
  502. * 3 - SRP-Capable Device
  503. * 4 - Non-OTG Device
  504. * 5 - SRP-Capable Host
  505. * 6 - Non-OTG Host
  506. * @arch: Architecture
  507. * 0 - Slave only
  508. * 1 - External DMA
  509. * 2 - Internal DMA
  510. * @ipg_isoc_en: This feature indicates that the controller supports
  511. * the worst-case scenario of Rx followed by Rx
  512. * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
  513. * specification for any token following ISOC OUT token.
  514. * 0 - Don't support
  515. * 1 - Support
  516. * @power_optimized: Are power optimizations enabled?
  517. * @num_dev_ep: Number of device endpoints available
  518. * @num_dev_in_eps: Number of device IN endpoints available
  519. * @num_dev_perio_in_ep: Number of device periodic IN endpoints
  520. * available
  521. * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
  522. * Depth
  523. * 0 to 30
  524. * @host_perio_tx_q_depth:
  525. * Host Mode Periodic Request Queue Depth
  526. * 2, 4 or 8
  527. * @nperio_tx_q_depth:
  528. * Non-Periodic Request Queue Depth
  529. * 2, 4 or 8
  530. * @hs_phy_type: High-speed PHY interface type
  531. * 0 - High-speed interface not supported
  532. * 1 - UTMI+
  533. * 2 - ULPI
  534. * 3 - UTMI+ and ULPI
  535. * @fs_phy_type: Full-speed PHY interface type
  536. * 0 - Full speed interface not supported
  537. * 1 - Dedicated full speed interface
  538. * 2 - FS pins shared with UTMI+ pins
  539. * 3 - FS pins shared with ULPI pins
  540. * @total_fifo_size: Total internal RAM for FIFOs (bytes)
  541. * @hibernation: Is hibernation enabled?
  542. * @utmi_phy_data_width: UTMI+ PHY data width
  543. * 0 - 8 bits
  544. * 1 - 16 bits
  545. * 2 - 8 or 16 bits
  546. * @snpsid: Value from SNPSID register
  547. * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
  548. * @g_tx_fifo_size: Power-on values of TxFIFO sizes
  549. * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
  550. * address DMA mode or descriptor DMA mode for accessing
  551. * the data FIFOs. The driver will automatically detect the
  552. * value for this if none is specified.
  553. * 0 - Address DMA
  554. * 1 - Descriptor DMA (default, if available)
  555. * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
  556. * 1 - Allow dynamic FIFO sizing (default, if available)
  557. * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
  558. * are enabled for non-periodic IN endpoints in device
  559. * mode.
  560. * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
  561. * in host mode when dynamic FIFO sizing is enabled
  562. * 16 to 32768
  563. * Actual maximum value is autodetected and also
  564. * the default.
  565. * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
  566. * host mode when dynamic FIFO sizing is enabled
  567. * 16 to 32768
  568. * Actual maximum value is autodetected and also
  569. * the default.
  570. * @max_transfer_size: The maximum transfer size supported, in bytes
  571. * 2047 to 65,535
  572. * Actual maximum value is autodetected and also
  573. * the default.
  574. * @max_packet_count: The maximum number of packets in a transfer
  575. * 15 to 511
  576. * Actual maximum value is autodetected and also
  577. * the default.
  578. * @host_channels: The number of host channel registers to use
  579. * 1 to 16
  580. * Actual maximum value is autodetected and also
  581. * the default.
  582. * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
  583. * in device mode when dynamic FIFO sizing is enabled
  584. * 16 to 32768
  585. * Actual maximum value is autodetected and also
  586. * the default.
  587. * @i2c_enable: Specifies whether to use the I2Cinterface for a full
  588. * speed PHY. This parameter is only applicable if phy_type
  589. * is FS.
  590. * 0 - No (default)
  591. * 1 - Yes
  592. * @acg_enable: For enabling Active Clock Gating in the controller
  593. * 0 - Disable
  594. * 1 - Enable
  595. * @lpm_mode: For enabling Link Power Management in the controller
  596. * 0 - Disable
  597. * 1 - Enable
  598. * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
  599. * FIFO sizing is enabled 16 to 32768
  600. * Actual maximum value is autodetected and also
  601. * the default.
  602. * @service_interval_mode: For enabling service interval based scheduling in the
  603. * controller.
  604. * 0 - Disable
  605. * 1 - Enable
  606. */
  607. struct dwc2_hw_params {
  608. unsigned op_mode:3;
  609. unsigned arch:2;
  610. unsigned dma_desc_enable:1;
  611. unsigned enable_dynamic_fifo:1;
  612. unsigned en_multiple_tx_fifo:1;
  613. unsigned rx_fifo_size:16;
  614. unsigned host_nperio_tx_fifo_size:16;
  615. unsigned dev_nperio_tx_fifo_size:16;
  616. unsigned host_perio_tx_fifo_size:16;
  617. unsigned nperio_tx_q_depth:3;
  618. unsigned host_perio_tx_q_depth:3;
  619. unsigned dev_token_q_depth:5;
  620. unsigned max_transfer_size:26;
  621. unsigned max_packet_count:11;
  622. unsigned host_channels:5;
  623. unsigned hs_phy_type:2;
  624. unsigned fs_phy_type:2;
  625. unsigned i2c_enable:1;
  626. unsigned acg_enable:1;
  627. unsigned num_dev_ep:4;
  628. unsigned num_dev_in_eps : 4;
  629. unsigned num_dev_perio_in_ep:4;
  630. unsigned total_fifo_size:16;
  631. unsigned power_optimized:1;
  632. unsigned hibernation:1;
  633. unsigned utmi_phy_data_width:2;
  634. unsigned lpm_mode:1;
  635. unsigned ipg_isoc_en:1;
  636. unsigned service_interval_mode:1;
  637. u32 snpsid;
  638. u32 dev_ep_dirs;
  639. u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
  640. };
  641. /* Size of control and EP0 buffers */
  642. #define DWC2_CTRL_BUFF_SIZE 8
  643. /**
  644. * struct dwc2_gregs_backup - Holds global registers state before
  645. * entering partial power down
  646. * @gotgctl: Backup of GOTGCTL register
  647. * @gintmsk: Backup of GINTMSK register
  648. * @gahbcfg: Backup of GAHBCFG register
  649. * @gusbcfg: Backup of GUSBCFG register
  650. * @grxfsiz: Backup of GRXFSIZ register
  651. * @gnptxfsiz: Backup of GNPTXFSIZ register
  652. * @gi2cctl: Backup of GI2CCTL register
  653. * @glpmcfg: Backup of GLPMCFG register
  654. * @gdfifocfg: Backup of GDFIFOCFG register
  655. * @pcgcctl: Backup of PCGCCTL register
  656. * @pcgcctl1: Backup of PCGCCTL1 register
  657. * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
  658. * @gpwrdn: Backup of GPWRDN register
  659. * @valid: True if registers values backuped.
  660. */
  661. struct dwc2_gregs_backup {
  662. u32 gotgctl;
  663. u32 gintmsk;
  664. u32 gahbcfg;
  665. u32 gusbcfg;
  666. u32 grxfsiz;
  667. u32 gnptxfsiz;
  668. u32 gi2cctl;
  669. u32 glpmcfg;
  670. u32 pcgcctl;
  671. u32 pcgcctl1;
  672. u32 gdfifocfg;
  673. u32 gpwrdn;
  674. bool valid;
  675. };
  676. /**
  677. * struct dwc2_dregs_backup - Holds device registers state before
  678. * entering partial power down
  679. * @dcfg: Backup of DCFG register
  680. * @dctl: Backup of DCTL register
  681. * @daintmsk: Backup of DAINTMSK register
  682. * @diepmsk: Backup of DIEPMSK register
  683. * @doepmsk: Backup of DOEPMSK register
  684. * @diepctl: Backup of DIEPCTL register
  685. * @dieptsiz: Backup of DIEPTSIZ register
  686. * @diepdma: Backup of DIEPDMA register
  687. * @doepctl: Backup of DOEPCTL register
  688. * @doeptsiz: Backup of DOEPTSIZ register
  689. * @doepdma: Backup of DOEPDMA register
  690. * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
  691. * @valid: True if registers values backuped.
  692. */
  693. struct dwc2_dregs_backup {
  694. u32 dcfg;
  695. u32 dctl;
  696. u32 daintmsk;
  697. u32 diepmsk;
  698. u32 doepmsk;
  699. u32 diepctl[MAX_EPS_CHANNELS];
  700. u32 dieptsiz[MAX_EPS_CHANNELS];
  701. u32 diepdma[MAX_EPS_CHANNELS];
  702. u32 doepctl[MAX_EPS_CHANNELS];
  703. u32 doeptsiz[MAX_EPS_CHANNELS];
  704. u32 doepdma[MAX_EPS_CHANNELS];
  705. u32 dtxfsiz[MAX_EPS_CHANNELS];
  706. bool valid;
  707. };
  708. /**
  709. * struct dwc2_hregs_backup - Holds host registers state before
  710. * entering partial power down
  711. * @hcfg: Backup of HCFG register
  712. * @haintmsk: Backup of HAINTMSK register
  713. * @hcintmsk: Backup of HCINTMSK register
  714. * @hprt0: Backup of HPTR0 register
  715. * @hfir: Backup of HFIR register
  716. * @hptxfsiz: Backup of HPTXFSIZ register
  717. * @valid: True if registers values backuped.
  718. */
  719. struct dwc2_hregs_backup {
  720. u32 hcfg;
  721. u32 haintmsk;
  722. u32 hcintmsk[MAX_EPS_CHANNELS];
  723. u32 hprt0;
  724. u32 hfir;
  725. u32 hptxfsiz;
  726. bool valid;
  727. };
  728. /*
  729. * Constants related to high speed periodic scheduling
  730. *
  731. * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
  732. * reservation point of view it's assumed that the schedule goes right back to
  733. * the beginning after the end of the schedule.
  734. *
  735. * What does that mean for scheduling things with a long interval? It means
  736. * we'll reserve time for them in every possible microframe that they could
  737. * ever be scheduled in. ...but we'll still only actually schedule them as
  738. * often as they were requested.
  739. *
  740. * We keep our schedule in a "bitmap" structure. This simplifies having
  741. * to keep track of and merge intervals: we just let the bitmap code do most
  742. * of the heavy lifting. In a way scheduling is much like memory allocation.
  743. *
  744. * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
  745. * supposed to schedule for periodic transfers). That's according to spec.
  746. *
  747. * Note that though we only schedule 80% of each microframe, the bitmap that we
  748. * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
  749. * space for each uFrame).
  750. *
  751. * Requirements:
  752. * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
  753. * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
  754. * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
  755. * be bugs). The 8 comes from the USB spec: number of microframes per frame.
  756. */
  757. #define DWC2_US_PER_UFRAME 125
  758. #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
  759. #define DWC2_HS_SCHEDULE_UFRAMES 8
  760. #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
  761. DWC2_HS_PERIODIC_US_PER_UFRAME)
  762. /*
  763. * Constants related to low speed scheduling
  764. *
  765. * For high speed we schedule every 1us. For low speed that's a bit overkill,
  766. * so we make up a unit called a "slice" that's worth 25us. There are 40
  767. * slices in a full frame and we can schedule 36 of those (90%) for periodic
  768. * transfers.
  769. *
  770. * Our low speed schedule can be as short as 1 frame or could be longer. When
  771. * we only schedule 1 frame it means that we'll need to reserve a time every
  772. * frame even for things that only transfer very rarely, so something that runs
  773. * every 2048 frames will get time reserved in every frame. Our low speed
  774. * schedule can be longer and we'll be able to handle more overlap, but that
  775. * will come at increased memory cost and increased time to schedule.
  776. *
  777. * Note: one other advantage of a short low speed schedule is that if we mess
  778. * up and miss scheduling we can jump in and use any of the slots that we
  779. * happened to reserve.
  780. *
  781. * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
  782. * the schedule. There will be one schedule per TT.
  783. *
  784. * Requirements:
  785. * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
  786. */
  787. #define DWC2_US_PER_SLICE 25
  788. #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
  789. #define DWC2_ROUND_US_TO_SLICE(us) \
  790. (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
  791. DWC2_US_PER_SLICE)
  792. #define DWC2_LS_PERIODIC_US_PER_FRAME \
  793. 900
  794. #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
  795. (DWC2_LS_PERIODIC_US_PER_FRAME / \
  796. DWC2_US_PER_SLICE)
  797. #define DWC2_LS_SCHEDULE_FRAMES 1
  798. #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
  799. DWC2_LS_PERIODIC_SLICES_PER_FRAME)
  800. /**
  801. * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
  802. * and periodic schedules
  803. *
  804. * These are common for both host and peripheral modes:
  805. *
  806. * @dev: The struct device pointer
  807. * @regs: Pointer to controller regs
  808. * @hw_params: Parameters that were autodetected from the
  809. * hardware registers
  810. * @params: Parameters that define how the core should be configured
  811. * @op_state: The operational State, during transitions (a_host=>
  812. * a_peripheral and b_device=>b_host) this may not match
  813. * the core, but allows the software to determine
  814. * transitions
  815. * @dr_mode: Requested mode of operation, one of following:
  816. * - USB_DR_MODE_PERIPHERAL
  817. * - USB_DR_MODE_HOST
  818. * - USB_DR_MODE_OTG
  819. * @role_sw: usb_role_switch handle
  820. * @hcd_enabled: Host mode sub-driver initialization indicator.
  821. * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
  822. * @ll_hw_enabled: Status of low-level hardware resources.
  823. * @hibernated: True if core is hibernated
  824. * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
  825. * remote wakeup.
  826. * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
  827. * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
  828. * suspend if we need USB to wake us up.
  829. * @frame_number: Frame number read from the core. For both device
  830. * and host modes. The value ranges are from 0
  831. * to HFNUM_MAX_FRNUM.
  832. * @phy: The otg phy transceiver structure for phy control.
  833. * @uphy: The otg phy transceiver structure for old USB phy
  834. * control.
  835. * @plat: The platform specific configuration data. This can be
  836. * removed once all SoCs support usb transceiver.
  837. * @supplies: Definition of USB power supplies
  838. * @vbus_supply: Regulator supplying vbus.
  839. * @usb33d: Optional 3.3v regulator used on some stm32 devices to
  840. * supply ID and VBUS detection hardware.
  841. * @lock: Spinlock that protects all the driver data structures
  842. * @priv: Stores a pointer to the struct usb_hcd
  843. * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
  844. * transfer are in process of being queued
  845. * @srp_success: Stores status of SRP request in the case of a FS PHY
  846. * with an I2C interface
  847. * @wq_otg: Workqueue object used for handling of some interrupts
  848. * @wf_otg: Work object for handling Connector ID Status Change
  849. * interrupt
  850. * @wkp_timer: Timer object for handling Wakeup Detected interrupt
  851. * @lx_state: Lx state of connected device
  852. * @gr_backup: Backup of global registers during suspend
  853. * @dr_backup: Backup of device registers during suspend
  854. * @hr_backup: Backup of host registers during suspend
  855. * @needs_byte_swap: Specifies whether the opposite endianness.
  856. *
  857. * These are for host mode:
  858. *
  859. * @flags: Flags for handling root port state changes
  860. * @flags.d32: Contain all root port flags
  861. * @flags.b: Separate root port flags from each other
  862. * @flags.b.port_connect_status_change: True if root port connect status
  863. * changed
  864. * @flags.b.port_connect_status: True if device connected to root port
  865. * @flags.b.port_reset_change: True if root port reset status changed
  866. * @flags.b.port_enable_change: True if root port enable status changed
  867. * @flags.b.port_suspend_change: True if root port suspend status changed
  868. * @flags.b.port_over_current_change: True if root port over current state
  869. * changed.
  870. * @flags.b.port_l1_change: True if root port l1 status changed
  871. * @flags.b.reserved: Reserved bits of root port register
  872. * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
  873. * Transfers associated with these QHs are not currently
  874. * assigned to a host channel.
  875. * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
  876. * Transfers associated with these QHs are currently
  877. * assigned to a host channel.
  878. * @non_periodic_qh_ptr: Pointer to next QH to process in the active
  879. * non-periodic schedule
  880. * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
  881. * Transfers associated with these QHs are not currently
  882. * assigned to a host channel.
  883. * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
  884. * list of QHs for periodic transfers that are _not_
  885. * scheduled for the next frame. Each QH in the list has an
  886. * interval counter that determines when it needs to be
  887. * scheduled for execution. This scheduling mechanism
  888. * allows only a simple calculation for periodic bandwidth
  889. * used (i.e. must assume that all periodic transfers may
  890. * need to execute in the same frame). However, it greatly
  891. * simplifies scheduling and should be sufficient for the
  892. * vast majority of OTG hosts, which need to connect to a
  893. * small number of peripherals at one time. Items move from
  894. * this list to periodic_sched_ready when the QH interval
  895. * counter is 0 at SOF.
  896. * @periodic_sched_ready: List of periodic QHs that are ready for execution in
  897. * the next frame, but have not yet been assigned to host
  898. * channels. Items move from this list to
  899. * periodic_sched_assigned as host channels become
  900. * available during the current frame.
  901. * @periodic_sched_assigned: List of periodic QHs to be executed in the next
  902. * frame that are assigned to host channels. Items move
  903. * from this list to periodic_sched_queued as the
  904. * transactions for the QH are queued to the DWC_otg
  905. * controller.
  906. * @periodic_sched_queued: List of periodic QHs that have been queued for
  907. * execution. Items move from this list to either
  908. * periodic_sched_inactive or periodic_sched_ready when the
  909. * channel associated with the transfer is released. If the
  910. * interval for the QH is 1, the item moves to
  911. * periodic_sched_ready because it must be rescheduled for
  912. * the next frame. Otherwise, the item moves to
  913. * periodic_sched_inactive.
  914. * @split_order: List keeping track of channels doing splits, in order.
  915. * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
  916. * This value is in microseconds per (micro)frame. The
  917. * assumption is that all periodic transfers may occur in
  918. * the same (micro)frame.
  919. * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
  920. * host is in high speed mode; low speed schedules are
  921. * stored elsewhere since we need one per TT.
  922. * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
  923. * SOF enable/disable.
  924. * @free_hc_list: Free host channels in the controller. This is a list of
  925. * struct dwc2_host_chan items.
  926. * @periodic_channels: Number of host channels assigned to periodic transfers.
  927. * Currently assuming that there is a dedicated host
  928. * channel for each periodic transaction and at least one
  929. * host channel is available for non-periodic transactions.
  930. * @non_periodic_channels: Number of host channels assigned to non-periodic
  931. * transfers
  932. * @available_host_channels: Number of host channels available for the
  933. * microframe scheduler to use
  934. * @hc_ptr_array: Array of pointers to the host channel descriptors.
  935. * Allows accessing a host channel descriptor given the
  936. * host channel number. This is useful in interrupt
  937. * handlers.
  938. * @status_buf: Buffer used for data received during the status phase of
  939. * a control transfer.
  940. * @status_buf_dma: DMA address for status_buf
  941. * @start_work: Delayed work for handling host A-cable connection
  942. * @reset_work: Delayed work for handling a port reset
  943. * @phy_reset_work: Work structure for doing a PHY reset
  944. * @otg_port: OTG port number
  945. * @frame_list: Frame list
  946. * @frame_list_dma: Frame list DMA address
  947. * @frame_list_sz: Frame list size
  948. * @desc_gen_cache: Kmem cache for generic descriptors
  949. * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
  950. * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
  951. *
  952. * These are for peripheral mode:
  953. *
  954. * @driver: USB gadget driver
  955. * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
  956. * @num_of_eps: Number of available EPs (excluding EP0)
  957. * @debug_root: Root directrory for debugfs.
  958. * @ep0_reply: Request used for ep0 reply.
  959. * @ep0_buff: Buffer for EP0 reply data, if needed.
  960. * @ctrl_buff: Buffer for EP0 control requests.
  961. * @ctrl_req: Request for EP0 control packets.
  962. * @ep0_state: EP0 control transfers state
  963. * @delayed_status: true when gadget driver asks for delayed status
  964. * @test_mode: USB test mode requested by the host
  965. * @remote_wakeup_allowed: True if device is allowed to wake-up host by
  966. * remote-wakeup signalling
  967. * @setup_desc_dma: EP0 setup stage desc chain DMA address
  968. * @setup_desc: EP0 setup stage desc chain pointer
  969. * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
  970. * @ctrl_in_desc: EP0 IN data phase desc chain pointer
  971. * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
  972. * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
  973. * @irq: Interrupt request line number
  974. * @clk: Pointer to otg clock
  975. * @reset: Pointer to dwc2 reset controller
  976. * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
  977. * @regset: A pointer to a struct debugfs_regset32, which contains
  978. * a pointer to an array of register definitions, the
  979. * array size and the base address where the register bank
  980. * is to be found.
  981. * @bus_suspended: True if bus is suspended
  982. * @last_frame_num: Number of last frame. Range from 0 to 32768
  983. * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
  984. * defined, for missed SOFs tracking. Array holds that
  985. * frame numbers, which not equal to last_frame_num +1
  986. * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
  987. * defined, for missed SOFs tracking.
  988. * If current_frame_number != last_frame_num+1
  989. * then last_frame_num added to this array
  990. * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
  991. * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
  992. * 0 - if missed SOFs frame numbers not dumbed
  993. * @fifo_mem: Total internal RAM for FIFOs (bytes)
  994. * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
  995. * then that fifo is used
  996. * @gadget: Represents a usb gadget device
  997. * @connected: Used in slave mode. True if device connected with host
  998. * @eps_in: The IN endpoints being supplied to the gadget framework
  999. * @eps_out: The OUT endpoints being supplied to the gadget framework
  1000. * @new_connection: Used in host mode. True if there are new connected
  1001. * device
  1002. * @enabled: Indicates the enabling state of controller
  1003. *
  1004. */
  1005. struct dwc2_hsotg {
  1006. struct device *dev;
  1007. void __iomem *regs;
  1008. /** Params detected from hardware */
  1009. struct dwc2_hw_params hw_params;
  1010. /** Params to actually use */
  1011. struct dwc2_core_params params;
  1012. enum usb_otg_state op_state;
  1013. enum usb_dr_mode dr_mode;
  1014. struct usb_role_switch *role_sw;
  1015. unsigned int hcd_enabled:1;
  1016. unsigned int gadget_enabled:1;
  1017. unsigned int ll_hw_enabled:1;
  1018. unsigned int hibernated:1;
  1019. unsigned int reset_phy_on_wake:1;
  1020. unsigned int need_phy_for_wake:1;
  1021. unsigned int phy_off_for_suspend:1;
  1022. u16 frame_number;
  1023. struct phy *phy;
  1024. struct usb_phy *uphy;
  1025. struct dwc2_hsotg_plat *plat;
  1026. struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
  1027. struct regulator *vbus_supply;
  1028. struct regulator *usb33d;
  1029. spinlock_t lock;
  1030. void *priv;
  1031. int irq;
  1032. struct clk *clk;
  1033. struct reset_control *reset;
  1034. struct reset_control *reset_ecc;
  1035. unsigned int queuing_high_bandwidth:1;
  1036. unsigned int srp_success:1;
  1037. struct workqueue_struct *wq_otg;
  1038. struct work_struct wf_otg;
  1039. struct timer_list wkp_timer;
  1040. enum dwc2_lx_state lx_state;
  1041. struct dwc2_gregs_backup gr_backup;
  1042. struct dwc2_dregs_backup dr_backup;
  1043. struct dwc2_hregs_backup hr_backup;
  1044. struct dentry *debug_root;
  1045. struct debugfs_regset32 *regset;
  1046. bool needs_byte_swap;
  1047. /* DWC OTG HW Release versions */
  1048. #define DWC2_CORE_REV_2_71a 0x4f54271a
  1049. #define DWC2_CORE_REV_2_72a 0x4f54272a
  1050. #define DWC2_CORE_REV_2_80a 0x4f54280a
  1051. #define DWC2_CORE_REV_2_90a 0x4f54290a
  1052. #define DWC2_CORE_REV_2_91a 0x4f54291a
  1053. #define DWC2_CORE_REV_2_92a 0x4f54292a
  1054. #define DWC2_CORE_REV_2_94a 0x4f54294a
  1055. #define DWC2_CORE_REV_3_00a 0x4f54300a
  1056. #define DWC2_CORE_REV_3_10a 0x4f54310a
  1057. #define DWC2_CORE_REV_4_00a 0x4f54400a
  1058. #define DWC2_CORE_REV_4_20a 0x4f54420a
  1059. #define DWC2_FS_IOT_REV_1_00a 0x5531100a
  1060. #define DWC2_HS_IOT_REV_1_00a 0x5532100a
  1061. #define DWC2_CORE_REV_MASK 0x0000ffff
  1062. /* DWC OTG HW Core ID */
  1063. #define DWC2_OTG_ID 0x4f540000
  1064. #define DWC2_FS_IOT_ID 0x55310000
  1065. #define DWC2_HS_IOT_ID 0x55320000
  1066. #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  1067. union dwc2_hcd_internal_flags {
  1068. u32 d32;
  1069. struct {
  1070. unsigned port_connect_status_change:1;
  1071. unsigned port_connect_status:1;
  1072. unsigned port_reset_change:1;
  1073. unsigned port_enable_change:1;
  1074. unsigned port_suspend_change:1;
  1075. unsigned port_over_current_change:1;
  1076. unsigned port_l1_change:1;
  1077. unsigned reserved:25;
  1078. } b;
  1079. } flags;
  1080. struct list_head non_periodic_sched_inactive;
  1081. struct list_head non_periodic_sched_waiting;
  1082. struct list_head non_periodic_sched_active;
  1083. struct list_head *non_periodic_qh_ptr;
  1084. struct list_head periodic_sched_inactive;
  1085. struct list_head periodic_sched_ready;
  1086. struct list_head periodic_sched_assigned;
  1087. struct list_head periodic_sched_queued;
  1088. struct list_head split_order;
  1089. u16 periodic_usecs;
  1090. unsigned long hs_periodic_bitmap[
  1091. DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
  1092. u16 periodic_qh_count;
  1093. bool bus_suspended;
  1094. bool new_connection;
  1095. u16 last_frame_num;
  1096. #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  1097. #define FRAME_NUM_ARRAY_SIZE 1000
  1098. u16 *frame_num_array;
  1099. u16 *last_frame_num_array;
  1100. int frame_num_idx;
  1101. int dumped_frame_num_array;
  1102. #endif
  1103. struct list_head free_hc_list;
  1104. int periodic_channels;
  1105. int non_periodic_channels;
  1106. int available_host_channels;
  1107. struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
  1108. u8 *status_buf;
  1109. dma_addr_t status_buf_dma;
  1110. #define DWC2_HCD_STATUS_BUF_SIZE 64
  1111. struct delayed_work start_work;
  1112. struct delayed_work reset_work;
  1113. struct work_struct phy_reset_work;
  1114. u8 otg_port;
  1115. u32 *frame_list;
  1116. dma_addr_t frame_list_dma;
  1117. u32 frame_list_sz;
  1118. struct kmem_cache *desc_gen_cache;
  1119. struct kmem_cache *desc_hsisoc_cache;
  1120. struct kmem_cache *unaligned_cache;
  1121. #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
  1122. #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
  1123. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  1124. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  1125. /* Gadget structures */
  1126. struct usb_gadget_driver *driver;
  1127. int fifo_mem;
  1128. unsigned int dedicated_fifos:1;
  1129. unsigned char num_of_eps;
  1130. u32 fifo_map;
  1131. struct usb_request *ep0_reply;
  1132. struct usb_request *ctrl_req;
  1133. void *ep0_buff;
  1134. void *ctrl_buff;
  1135. enum dwc2_ep0_state ep0_state;
  1136. unsigned delayed_status : 1;
  1137. u8 test_mode;
  1138. dma_addr_t setup_desc_dma[2];
  1139. struct dwc2_dma_desc *setup_desc[2];
  1140. dma_addr_t ctrl_in_desc_dma;
  1141. struct dwc2_dma_desc *ctrl_in_desc;
  1142. dma_addr_t ctrl_out_desc_dma;
  1143. struct dwc2_dma_desc *ctrl_out_desc;
  1144. struct usb_gadget gadget;
  1145. unsigned int enabled:1;
  1146. unsigned int connected:1;
  1147. unsigned int remote_wakeup_allowed:1;
  1148. struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
  1149. struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
  1150. #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
  1151. };
  1152. /* Normal architectures just use readl/write */
  1153. static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
  1154. {
  1155. u32 val;
  1156. val = readl(hsotg->regs + offset);
  1157. if (hsotg->needs_byte_swap)
  1158. return swab32(val);
  1159. else
  1160. return val;
  1161. }
  1162. static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
  1163. {
  1164. if (hsotg->needs_byte_swap)
  1165. writel(swab32(value), hsotg->regs + offset);
  1166. else
  1167. writel(value, hsotg->regs + offset);
  1168. #ifdef DWC2_LOG_WRITES
  1169. pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
  1170. #endif
  1171. }
  1172. static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
  1173. void *buffer, unsigned int count)
  1174. {
  1175. if (count) {
  1176. u32 *buf = buffer;
  1177. do {
  1178. u32 x = dwc2_readl(hsotg, offset);
  1179. *buf++ = x;
  1180. } while (--count);
  1181. }
  1182. }
  1183. static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
  1184. const void *buffer, unsigned int count)
  1185. {
  1186. if (count) {
  1187. const u32 *buf = buffer;
  1188. do {
  1189. dwc2_writel(hsotg, *buf++, offset);
  1190. } while (--count);
  1191. }
  1192. }
  1193. /* Reasons for halting a host channel */
  1194. enum dwc2_halt_status {
  1195. DWC2_HC_XFER_NO_HALT_STATUS,
  1196. DWC2_HC_XFER_COMPLETE,
  1197. DWC2_HC_XFER_URB_COMPLETE,
  1198. DWC2_HC_XFER_ACK,
  1199. DWC2_HC_XFER_NAK,
  1200. DWC2_HC_XFER_NYET,
  1201. DWC2_HC_XFER_STALL,
  1202. DWC2_HC_XFER_XACT_ERR,
  1203. DWC2_HC_XFER_FRAME_OVERRUN,
  1204. DWC2_HC_XFER_BABBLE_ERR,
  1205. DWC2_HC_XFER_DATA_TOGGLE_ERR,
  1206. DWC2_HC_XFER_AHB_ERR,
  1207. DWC2_HC_XFER_PERIODIC_INCOMPLETE,
  1208. DWC2_HC_XFER_URB_DEQUEUE,
  1209. };
  1210. /* Core version information */
  1211. static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
  1212. {
  1213. return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
  1214. }
  1215. static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
  1216. {
  1217. return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
  1218. }
  1219. static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
  1220. {
  1221. return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
  1222. }
  1223. /*
  1224. * The following functions support initialization of the core driver component
  1225. * and the DWC_otg controller
  1226. */
  1227. int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
  1228. int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
  1229. int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
  1230. int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
  1231. int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
  1232. int reset, int is_host);
  1233. void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
  1234. int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
  1235. void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
  1236. void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
  1237. bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
  1238. int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
  1239. /*
  1240. * Common core Functions.
  1241. * The following functions support managing the DWC_otg controller in either
  1242. * device or host mode.
  1243. */
  1244. void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
  1245. void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
  1246. void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
  1247. void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
  1248. void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
  1249. void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
  1250. int is_host);
  1251. int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
  1252. int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
  1253. void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
  1254. /* This function should be called on every hardware interrupt. */
  1255. irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
  1256. /* The device ID match table */
  1257. extern const struct of_device_id dwc2_of_match_table[];
  1258. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
  1259. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
  1260. /* Common polling functions */
  1261. int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
  1262. u32 timeout);
  1263. int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
  1264. u32 timeout);
  1265. /* Parameters */
  1266. int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
  1267. int dwc2_init_params(struct dwc2_hsotg *hsotg);
  1268. /*
  1269. * The following functions check the controller's OTG operation mode
  1270. * capability (GHWCFG2.OTG_MODE).
  1271. *
  1272. * These functions can be used before the internal hsotg->hw_params
  1273. * are read in and cached so they always read directly from the
  1274. * GHWCFG2 register.
  1275. */
  1276. unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
  1277. bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
  1278. bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
  1279. bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
  1280. /*
  1281. * Returns the mode of operation, host or device
  1282. */
  1283. static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
  1284. {
  1285. return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
  1286. }
  1287. static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
  1288. {
  1289. return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
  1290. }
  1291. int dwc2_drd_init(struct dwc2_hsotg *hsotg);
  1292. void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
  1293. void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
  1294. void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
  1295. /*
  1296. * Dump core registers and SPRAM
  1297. */
  1298. void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
  1299. void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
  1300. void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
  1301. /* Gadget defines */
  1302. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  1303. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  1304. int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
  1305. int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
  1306. int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
  1307. int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
  1308. void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
  1309. bool reset);
  1310. void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
  1311. void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
  1312. void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
  1313. int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
  1314. #define dwc2_is_device_connected(hsotg) (hsotg->connected)
  1315. #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
  1316. int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
  1317. int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
  1318. int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
  1319. int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
  1320. int rem_wakeup, int reset);
  1321. int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
  1322. int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
  1323. int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
  1324. void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
  1325. void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
  1326. #else
  1327. static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
  1328. { return 0; }
  1329. static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
  1330. { return 0; }
  1331. static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
  1332. { return 0; }
  1333. static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
  1334. { return 0; }
  1335. static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
  1336. bool reset) {}
  1337. static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
  1338. static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
  1339. static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
  1340. static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
  1341. int testmode)
  1342. { return 0; }
  1343. #define dwc2_is_device_connected(hsotg) (0)
  1344. #define dwc2_is_device_enabled(hsotg) (0)
  1345. static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
  1346. { return 0; }
  1347. static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
  1348. int remote_wakeup)
  1349. { return 0; }
  1350. static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
  1351. { return 0; }
  1352. static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
  1353. int rem_wakeup, int reset)
  1354. { return 0; }
  1355. static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
  1356. { return 0; }
  1357. static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
  1358. { return 0; }
  1359. static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
  1360. { return 0; }
  1361. static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
  1362. static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
  1363. #endif
  1364. #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  1365. int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
  1366. int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
  1367. void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
  1368. void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
  1369. void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
  1370. int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
  1371. int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
  1372. int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
  1373. int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
  1374. int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
  1375. int rem_wakeup, int reset);
  1376. bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
  1377. static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
  1378. { schedule_work(&hsotg->phy_reset_work); }
  1379. #else
  1380. static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
  1381. { return 0; }
  1382. static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
  1383. int us)
  1384. { return 0; }
  1385. static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
  1386. static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
  1387. static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
  1388. static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
  1389. static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
  1390. { return 0; }
  1391. static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
  1392. { return 0; }
  1393. static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
  1394. { return 0; }
  1395. static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
  1396. { return 0; }
  1397. static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
  1398. { return 0; }
  1399. static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
  1400. int rem_wakeup, int reset)
  1401. { return 0; }
  1402. static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
  1403. { return false; }
  1404. static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
  1405. #endif
  1406. #endif /* __DWC2_CORE_H__ */